src/scoreboard/issue_unit.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Cat, Array, Const, Repl, Elaboratable
   4 from nmigen.lib.coding import Decoder
   5
   6 from scoreboard.group_picker import PriorityPicker
   7
   8
   9 class RegDecode(Elaboratable):
  10     """ decodes registers into unary
  11
  12         Inputs
  13
  14         * :wid:         register file width
  15     """
  16     def __init__(self, wid):
  17         self.reg_width = wid
  18
  19         # inputs
  20         self.enable_i = Signal(reset_less=True) # enable decoders
  21         self.dest_i = Signal(max=wid, reset_less=True) # Dest R# in
  22         self.src1_i = Signal(max=wid, reset_less=True) # oper1 R# in
  23         self.src2_i = Signal(max=wid, reset_less=True) # oper2 R# in
  24
  25         # outputs
  26         self.dest_o = Signal(wid, reset_less=True) # Dest unary out
  27         self.src1_o = Signal(wid, reset_less=True) # oper1 unary out
  28         self.src2_o = Signal(wid, reset_less=True) # oper2 unary out
  29
  30     def elaborate(self, platform):
  31         m = Module()
  32         m.submodules.dest_d = dest_d = Decoder(self.reg_width)
  33         m.submodules.src1_d = src1_d = Decoder(self.reg_width)
  34         m.submodules.src2_d = src2_d = Decoder(self.reg_width)
  35
  36         # dest decoder: write-pending
  37         for d, i, o in [(dest_d, self.dest_i, self.dest_o),
  38                      (src1_d, self.src1_i, self.src1_o),
  39                      (src2_d, self.src2_i, self.src2_o)]:
  40             m.d.comb += d.i.eq(i)
  41             m.d.comb += d.n.eq(~self.enable_i)
  42             m.d.comb += o.eq(d.o)
  43
  44         return m
  45
  46     def __iter__(self):
  47         yield self.enable_i
  48         yield self.dest_i
  49         yield self.src1_i
  50         yield self.src2_i
  51         yield self.dest_o
  52         yield self.src1_o
  53         yield self.src2_o
  54
  55     def ports(self):
  56         return list(self)
  57
  58
  59 class IssueUnitGroup(Elaboratable):
  60     """ Manages a batch of Computation Units all of which can do the same task
  61
  62         A priority picker will allocate one instruction in this cycle based
  63         on whether the others are busy.
  64
  65         insn_i indicates to this module that there is an instruction to be
  66         issued which this group can handle
  67
  68         busy_i is a vector of signals that indicate, in this cycle, which
  69         of the units are currently busy.
  70
  71         busy_o indicates whether it is "safe to proceed" i.e. whether
  72         there is a unit here that can *be* issued an instruction
  73
  74         fn_issue_o indicates, out of the available (non-busy) units,
  75         which one may be selected
  76     """
  77     def __init__(self, n_insns):
  78         """ Set up inputs and outputs for the Group
  79
  80             Input Parameters
  81
  82             * :n_insns:     number of instructions in this issue unit.
  83         """
  84         self.n_insns = n_insns
  85
  86         # inputs
  87         self.insn_i = Signal(reset_less=True, name="insn_i")
  88         self.busy_i = Signal(n_insns, reset_less=True, name="busy_i")
  89
  90         # outputs
  91         self.fn_issue_o = Signal(n_insns, reset_less=True, name="fn_issue_o")
  92         self.busy_o = Signal(reset_less=True)
  93
  94     def elaborate(self, platform):
  95         m = Module()
  96
  97         if self.n_insns == 0:
  98             return m
  99
 100         m.submodules.pick = pick = PriorityPicker(self.n_insns)
 101
 102         # temporaries
 103         allissue = Signal(self.n_insns, reset_less=True)
 104         all1 = Const(-1, self.n_insns)
 105
 106         m.d.comb += allissue.eq(Repl(self.insn_i, self.n_insns))
 107         # Pick one (and only one) of the units to proceed in this cycle
 108         m.d.comb += pick.i.eq(~self.busy_i & allissue)
 109
 110         # "Safe to issue" condition is basically when all units are not busy
 111         m.d.comb += self.busy_o.eq((self.busy_i == all1))
 112
 113         # Picker only raises one signal, therefore it's also the fn_issue
 114         m.d.comb += self.fn_issue_o.eq(pick.o)
 115
 116         return m
 117
 118     def __iter__(self):
 119         yield self.insn_i
 120         yield self.busy_i
 121         yield self.fn_issue_o
 122         yield self.g_issue_o
 123
 124     def ports(self):
 125         return list(self)
 126
 127
 128 class IssueUnitArray(Elaboratable):
 129     """ Convenience module that amalgamates the issue and busy signals
 130
 131         unit issue_i is to be set externally, at the same time as the
 132         ALU group oper_i
 133     """
 134     def __init__(self, units):
 135         self.units = units
 136         self.issue_o = Signal(reset_less=True)
 137         n_insns = 0
 138         for u in self.units:
 139             n_insns += len(u.fn_issue_o)
 140         self.busy_i = Signal(n_insns, reset_less=True)
 141         self.fn_issue_o = Signal(n_insns, reset_less=True)
 142         self.n_insns = n_insns
 143
 144     def elaborate(self, platform):
 145         m = Module()
 146         for i, u in enumerate(self.units):
 147             setattr(m.submodules, "issue%d" % i, u)
 148
 149         g_issue_o = []
 150         busy_i = []
 151         fn_issue_o = []
 152         for u in self.units:
 153             busy_i.append(u.busy_i)
 154             g_issue_o.append(~u.busy_o)
 155             fn_issue_o.append(u.fn_issue_o)
 156         m.d.comb += self.issue_o.eq(Cat(*g_issue_o).bool())
 157         m.d.comb += self.fn_issue_o.eq(Cat(*fn_issue_o))
 158         m.d.comb += Cat(*busy_i).eq(self.busy_i)
 159
 160         return m
 161
 162     def ports(self):
 163         yield self.busy_i
 164         yield self.issue_o
 165         yield self.fn_issue_o
 166         yield from self.units
 167
 168
 169
 170 class IssueUnit(Elaboratable):
 171     """ implements 11.4.14 issue unit, p50
 172
 173         Inputs
 174
 175         * :n_insns:     number of instructions in this issue unit.
 176     """
 177     def __init__(self, n_insns):
 178         self.n_insns = n_insns
 179
 180         # inputs
 181         self.insn_i = Signal(n_insns, reset_less=True, name="insn_i")
 182         self.busy_i = Signal(n_insns, reset_less=True, name="busy_i")
 183
 184         # outputs
 185         self.fn_issue_o = Signal(n_insns, reset_less=True, name="fn_issue_o")
 186         self.g_issue_o = Signal(reset_less=True)
 187
 188     def elaborate(self, platform):
 189         m = Module()
 190
 191         if self.n_insns == 0:
 192             return m
 193
 194         # temporaries
 195         fu_stall = Signal(reset_less=True)
 196
 197         ib_l = []
 198         for i in range(self.n_insns):
 199             ib_l.append(self.insn_i[i] & self.busy_i[i])
 200         m.d.comb += fu_stall.eq(Cat(*ib_l).bool())
 201         m.d.comb += self.g_issue_o.eq(~(fu_stall))
 202         for i in range(self.n_insns):
 203             m.d.comb += self.fn_issue_o[i].eq(self.g_issue_o & self.insn_i[i])
 204
 205         return m
 206
 207     def __iter__(self):
 208         yield self.insn_i
 209         yield self.busy_i
 210         yield self.fn_issue_o
 211         yield self.g_issue_o
 212
 213     def ports(self):
 214         return list(self)
 215
 216
 217 class IntFPIssueUnit(Elaboratable):
 218     def __init__(self, n_int_insns, n_fp_insns):
 219         self.i = IssueUnit(n_int_insns)
 220         self.f = IssueUnit(n_fp_insns)
 221         self.issue_o = Signal(reset_less=True)
 222
 223     def elaborate(self, platform):
 224         m = Module()
 225         m.submodules.intissue = self.i
 226         m.submodules.fpissue = self.f
 227
 228         m.d.comb += self.issue_o.eq(self.i.g_issue_o | self.f.g_issue_o)
 229
 230         return m
 231
 232     def ports(self):
 233         yield self.issue_o
 234         yield from self.i
 235         yield from self.f
 236
 237
 238 def issue_unit_sim(dut):
 239     yield dut.dest_i.eq(1)
 240     yield dut.issue_i.eq(1)
 241     yield
 242     yield dut.issue_i.eq(0)
 243     yield
 244     yield dut.src1_i.eq(1)
 245     yield dut.issue_i.eq(1)
 246     yield
 247     yield
 248     yield
 249     yield dut.issue_i.eq(0)
 250     yield
 251     yield dut.go_rd_i.eq(1)
 252     yield
 253     yield dut.go_rd_i.eq(0)
 254     yield
 255     yield dut.go_wr_i.eq(1)
 256     yield
 257     yield dut.go_wr_i.eq(0)
 258     yield
 259
 260 def test_issue_unit():
 261     dut = IssueUnitGroup(3)
 262     vl = rtlil.convert(dut, ports=dut.ports())
 263     with open("test_issue_unit_group.il", "w") as f:
 264         f.write(vl)
 265
 266     dut = IssueUnit(32, 3)
 267     vl = rtlil.convert(dut, ports=dut.ports())
 268     with open("test_issue_unit.il", "w") as f:
 269         f.write(vl)
 270
 271     dut = IntFPIssueUnit(32, 3, 3)
 272     vl = rtlil.convert(dut, ports=dut.ports())
 273     with open("test_intfp_issue_unit.il", "w") as f:
 274         f.write(vl)
 275
 276     run_simulation(dut, issue_unit_sim(dut), vcd_name='test_issue_unit.vcd')
 277
 278 if __name__ == '__main__':
 279     test_issue_unit()