src/scoreboard/ldst_dep_cell.py

   1 """ Mitch Alsup 6600-style LD/ST scoreboard Dependency Cell
   2
   3 Relevant comments (p45-46):
   4
   5 * If there are no WAR dependencies on a Load instruction with a computed
   6   address it can assert Bank_Addressable and Translate_Addressable.
   7
   8 * If there are no RAW dependencies on a Store instruction with both a
   9   write permission and store data present it can assert Bank_Addressable
  10
  11 Relevant bugreports:
  12
  13 * http://bugs.libre-riscv.org/show_bug.cgi?id=81
  14
  15 """
  16
  17 from nmigen.compat.sim import run_simulation
  18 from nmigen.cli import verilog, rtlil
  19 from nmigen import Module, Signal, Repl, Elaboratable
  20 from nmutil.latch import SRLatch
  21
  22
  23 class LDSTDepCell(Elaboratable):
  24     """ implements 11.4.12 mitch alsup load/store dependence cell, p45
  25     """
  26     def __init__(self, n_ls=1):
  27         self.n_ls = n_ls
  28         # inputs
  29         self.load_i = Signal(n_ls, reset_less=True)     # load pend in (top)
  30         self.stor_i = Signal(n_ls, reset_less=True)     # store pend in (top)
  31         self.issue_i = Signal(reset_less=True)    # Issue in (top)
  32         self.go_die_i = Signal(reset_less=True)    # Issue in (top)
  33
  34         # load / store hit - basically connect these to go_wr from LD/STCompUnit
  35         # LD.go_wr -> load_hit_i, ST.go_wr -> stwd_hit_i.
  36         self.load_hit_i = Signal(n_ls, reset_less=True) # ld hit in (right)
  37         self.stwd_hit_i = Signal(n_ls, reset_less=True) # st w/ hit in (right)
  38
  39         # outputs (latched rd/wr pend)
  40         self.ld_hold_st_o = Signal(reset_less=True) # ld holds st out (l)
  41         self.st_hold_ld_o = Signal(reset_less=True) # st holds ld out (l)
  42
  43     def elaborate(self, platform):
  44         m = Module()
  45         m.submodules.war_l = war_l = SRLatch(sync=False, llen=self.n_ls) # WaR
  46         m.submodules.raw_l = raw_l = SRLatch(sync=False, llen=self.n_ls) # RaW
  47
  48         # temporaries (repeat-extend)
  49         issue = Repl(self.issue_i, self.n_ls)
  50         die = Repl(self.go_die_i, self.n_ls)
  51
  52         # issue & store & load - used for both WAR and RAW Setting
  53         i_s_l = Signal(self.n_ls, reset_less=True)
  54         m.d.comb += i_s_l.eq(issue & self.stor_i & self.load_i)
  55
  56         # write after read latch: loads block stores
  57         m.d.comb += war_l.s.eq(i_s_l)
  58         m.d.comb += war_l.r.eq(die | self.load_i) # reset on LD
  59
  60         # read after write latch: stores block loads
  61         m.d.comb += raw_l.s.eq(i_s_l)
  62         m.d.comb += raw_l.r.eq(die | self.stor_i) # reset on ST
  63
  64         # Hold results (read out horizontally, accumulate in OR fashion)
  65         m.d.comb += self.ld_hold_st_o.eq((war_l.qn & self.load_hit_i).bool())
  66         m.d.comb += self.st_hold_ld_o.eq((raw_l.qn & self.stwd_hit_i).bool())
  67
  68         return m
  69
  70     def __iter__(self):
  71         yield self.load_i
  72         yield self.stor_i
  73         yield self.issue_i
  74         yield self.load_hit_i
  75         yield self.stwd_hit_i
  76         yield self.ld_hold_st_o
  77         yield self.st_hold_ld_o
  78
  79     def ports(self):
  80         return list(self)
  81
  82
  83 def dcell_sim(dut):
  84     yield dut.dest_i.eq(1)
  85     yield dut.issue_i.eq(1)
  86     yield
  87     yield dut.issue_i.eq(0)
  88     yield
  89     yield dut.src1_i.eq(1)
  90     yield dut.issue_i.eq(1)
  91     yield
  92     yield dut.issue_i.eq(0)
  93     yield
  94     yield dut.go_rd_i.eq(1)
  95     yield
  96     yield dut.go_rd_i.eq(0)
  97     yield
  98     yield dut.go_wr_i.eq(1)
  99     yield
 100     yield dut.go_wr_i.eq(0)
 101     yield
 102
 103 def test_dcell():
 104     dut = LDSTDepCell()
 105     vl = rtlil.convert(dut, ports=dut.ports())
 106     with open("test_ldst_dcell.il", "w") as f:
 107         f.write(vl)
 108
 109     run_simulation(dut, dcell_sim(dut), vcd_name='test_ldst_dcell.vcd')
 110
 111 if __name__ == '__main__':
 112     test_dcell()