src/soc/TLB/PteEntry.py

   1 from nmigen import Module, Signal, Elaboratable
   2 from nmigen.cli import main
   3
   4
   5 class PteEntry(Elaboratable):
   6     """ The purpose of this Module is to  centralize the parsing of Page
   7         Table Entries (PTE) into one module to prevent common mistakes
   8         and duplication of code. The control bits are parsed out for
   9         ease of use.
  10
  11         This module parses according to the standard PTE given by the
  12         Volume II: RISC-V Privileged Architectures V1.10 Pg 60.
  13         The Address Space IDentifier (ASID) is appended to the MSB of the input
  14         and is parsed out as such.
  15
  16         An valid input Signal would be:
  17               ASID   PTE
  18         Bits:[78-64][63-0]
  19
  20         The output PTE value will include the control bits.
  21     """
  22     def __init__(self, asid_size, pte_size):
  23         """ Arguments:
  24             * asid_size: (bit count) The size of the asid to be processed
  25             * pte_size: (bit count) The size of the pte to be processed
  26
  27             Return:
  28             * d The Dirty bit from the PTE portion of i
  29             * a The Accessed bit from the PTE portion of i
  30             * g The Global bit from the PTE portion of i
  31             * u The User Mode bit from the PTE portion of i
  32             * xwr The Execute/Write/Read bit from the PTE portion of i
  33             * v The Valid bit from the PTE portion of i
  34             * asid The asid portion of i
  35             * pte The pte portion of i
  36         """
  37         # Internal
  38         self.asid_start = pte_size
  39         self.asid_end = pte_size + asid_size
  40
  41         # Input
  42         self.i = Signal(asid_size + pte_size)
  43
  44         # Output
  45         self.d = Signal(1) # Dirty bit (From pte)
  46         self.a = Signal(1) # Accessed bit (From pte)
  47         self.g = Signal(1) # Global Access (From pte)
  48         self.u = Signal(1) # User Mode (From pte)
  49         self.xwr = Signal(3) # Execute Read Write (From pte)
  50         self.v = Signal(1) # Valid (From pte)
  51         self.asid = Signal(asid_size) # Associated Address Space IDentifier
  52         self.pte = Signal(pte_size) # Full Page Table Entry
  53
  54     def elaborate(self, platform=None):
  55         m = Module()
  56         # Pull out all control bites from PTE
  57         m.d.comb += [
  58             self.d.eq(self.i[7]),
  59             self.a.eq(self.i[6]),
  60             self.g.eq(self.i[5]),
  61             self.u.eq(self.i[4]),
  62             self.xwr.eq(self.i[1:4]),
  63             self.v.eq(self.i[0])
  64         ]
  65         m.d.comb += self.asid.eq(self.i[self.asid_start:self.asid_end])
  66         m.d.comb += self.pte.eq(self.i[0:self.asid_start])
  67         return m