src/soc/TLB/test/test_pte_entry.py

   1 from nmigen.compat.sim import run_simulation
   2
   3 from TLB.PteEntry import PteEntry
   4
   5 from TestUtil.test_helper import assert_op
   6
   7 def set_entry(dut, i):
   8     yield dut.i.eq(i)
   9     yield
  10
  11 def check_dirty(dut, d, op):
  12     out_d = yield dut.d
  13     assert_op("Dirty", out_d, d, op)
  14
  15 def check_accessed(dut, a, op):
  16     out_a = yield dut.a
  17     assert_op("Accessed", out_a, a, op)
  18
  19 def check_global(dut, o, op):
  20     out = yield dut.g
  21     assert_op("Global", out, o, op)
  22
  23 def check_user(dut, o, op):
  24     out = yield dut.u
  25     assert_op("User Mode", out, o, op)
  26
  27 def check_xwr(dut, o, op):
  28     out = yield dut.xwr
  29     assert_op("XWR", out, o, op)
  30
  31 def check_asid(dut, o, op):
  32     out = yield dut.asid
  33     assert_op("ASID", out, o, op)
  34
  35 def check_pte(dut, o, op):
  36     out = yield dut.pte
  37     assert_op("ASID", out, o, op)
  38
  39 def check_valid(dut, v, op):
  40     out_v = yield dut.v
  41     assert_op("Valid", out_v, v, op)
  42
  43 def check_all(dut, d, a, g, u, xwr, v, asid, pte):
  44     yield from check_dirty(dut, d, 0)
  45     yield from check_accessed(dut, a, 0)
  46     yield from check_global(dut, g, 0)
  47     yield from check_user(dut, u, 0)
  48     yield from check_xwr(dut, xwr, 0)
  49     yield from check_asid(dut, asid, 0)
  50     yield from check_pte(dut, pte, 0)
  51     yield from check_valid(dut, v, 0)
  52
  53 def tbench(dut):
  54     # 80 bits represented. Ignore the MSB as it will be truncated
  55     # ASID is bits first 4 hex values (bits 64 - 78)
  56
  57     i = 0x7FFF0000000000000031
  58     dirty = 0
  59     access = 0
  60     glob = 1
  61     user = 1
  62     xwr = 0
  63     valid = 1
  64     asid = 0x7FFF
  65     pte = 0x0000000000000031
  66     yield from set_entry(dut, i)
  67     yield from check_all(dut, dirty, access, glob, user, xwr, valid, asid, pte)
  68
  69     i = 0x0FFF00000000000000FF
  70     dirty = 1
  71     access = 1
  72     glob = 1
  73     user = 1
  74     xwr = 7
  75     valid = 1
  76     asid = 0x0FFF
  77     pte = 0x00000000000000FF
  78     yield from set_entry(dut, i)
  79     yield from check_all(dut, dirty, access, glob, user, xwr, valid, asid, pte)
  80
  81     i = 0x0721000000001100001F
  82     dirty = 0
  83     access = 0
  84     glob = 0
  85     user = 1
  86     xwr = 7
  87     valid = 1
  88     asid = 0x0721
  89     pte = 0x000000001100001F
  90     yield from set_entry(dut, i)
  91     yield from check_all(dut, dirty, access, glob, user, xwr, valid, asid, pte)
  92
  93     yield
  94
  95
  96 def test_pteentry():
  97     dut = PteEntry(15, 64);
  98     run_simulation(dut, tbench(dut), vcd_name="Waveforms/test_pte_entry.vcd")
  99     print("PteEntry Unit Test Success")
 100
 101 if __name__ == "__main__":
 102     test_pteentry()