src/soc/branch/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmigen.test.utils import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.branch.pipeline import BranchBasePipe
  16 from soc.alu.alu_input_record import CompALUOpSubset
  17 from soc.alu.pipe_data import ALUPipeSpec
  18 import random
  19
  20
  21 class TestCase:
  22     def __init__(self, program, regs, sprs, name):
  23         self.program = program
  24         self.regs = regs
  25         self.sprs = sprs
  26         self.name = name
  27
  28 def get_rec_width(rec):
  29     recwidth = 0
  30     # Setup random inputs for dut.op
  31     for p in rec.ports():
  32         width = p.width
  33         recwidth += width
  34     return recwidth
  35
  36
  37 # This test bench is a bit different than is usual. Initially when I
  38 # was writing it, I had all of the tests call a function to create a
  39 # device under test and simulator, initialize the dut, run the
  40 # simulation for ~2 cycles, and assert that the dut output what it
  41 # should have. However, this was really slow, since it needed to
  42 # create and tear down the dut and simulator for every test case.
  43
  44 # Now, instead of doing that, every test case in ALUTestCase puts some
  45 # data into the test_data list below, describing the instructions to
  46 # be tested and the initial state. Once all the tests have been run,
  47 # test_data gets passed to TestRunner which then sets up the DUT and
  48 # simulator once, runs all the data through it, and asserts that the
  49 # results match the pseudocode sim at every cycle.
  50
  51 # By doing this, I've reduced the time it takes to run the test suite
  52 # massively. Before, it took around 1 minute on my computer, now it
  53 # takes around 3 seconds
  54
  55 test_data = []
  56
  57
  58 class LogicalTestCase(FHDLTestCase):
  59     def __init__(self, name):
  60         super().__init__(name)
  61         self.test_name = name
  62     def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}):
  63         tc = TestCase(prog, initial_regs, initial_sprs, self.test_name)
  64         test_data.append(tc)
  65
  66     def test_cmpb(self):
  67         lst = ["b 0x1234"]
  68         initial_regs = [0] * 32
  69         self.run_tst_program(Program(lst), initial_regs)
  70
  71     def test_ilang(self):
  72         rec = CompALUOpSubset()
  73
  74         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
  75         alu = BranchBasePipe(pspec)
  76         vl = rtlil.convert(alu, ports=[])
  77         with open("logical_pipeline.il", "w") as f:
  78             f.write(vl)
  79
  80
  81 class TestRunner(FHDLTestCase):
  82     def __init__(self, test_data):
  83         super().__init__("run_all")
  84         self.test_data = test_data
  85
  86     def run_all(self):
  87         m = Module()
  88         comb = m.d.comb
  89         instruction = Signal(32)
  90
  91         pdecode = create_pdecode()
  92
  93         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
  94
  95         rec = CompALUOpSubset()
  96
  97         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
  98         m.submodules.alu = alu = BranchBasePipe(pspec)
  99
 100         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 101         comb += alu.p.valid_i.eq(1)
 102         comb += alu.n.ready_i.eq(1)
 103         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 104         sim = Simulator(m)
 105
 106         sim.add_clock(1e-6)
 107         def process():
 108             for test in self.test_data:
 109                 print(test.name)
 110                 program = test.program
 111                 self.subTest(test.name)
 112                 simulator = ISA(pdecode2, test.regs, test.sprs)
 113                 gen = program.generate_instructions()
 114                 instructions = list(zip(gen, program.assembly.splitlines()))
 115
 116                 index = simulator.pc.CIA.value//4
 117                 while index < len(instructions):
 118                     ins, code = instructions[index]
 119
 120                     print("0x{:X}".format(ins & 0xffffffff))
 121                     print(code)
 122
 123                     # ask the decoder to decode this binary data (endian'd)
 124                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 125                     yield instruction.eq(ins)          # raw binary instr.
 126                     yield Settle()
 127                     fn_unit = yield pdecode2.e.fn_unit
 128                     self.assertEqual(fn_unit, Function.BRANCH.value, code)
 129                     yield
 130                     opname = code.split(' ')[0]
 131                     yield from simulator.call(opname)
 132                     index = simulator.pc.CIA.value//4
 133
 134
 135         sim.add_sync_process(process)
 136         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 137                             traces=[]):
 138             sim.run()
 139     def check_extra_alu_outputs(self, alu, dec2, sim):
 140         rc = yield dec2.e.rc.data
 141         if rc:
 142             cr_expected = sim.crl[0].get_range().value
 143             cr_actual = yield alu.n.data_o.cr0
 144             self.assertEqual(cr_expected, cr_actual)
 145
 146
 147 if __name__ == "__main__":
 148     unittest.main(exit=False)
 149     suite = unittest.TestSuite()
 150     suite.addTest(TestRunner(test_data))
 151
 152     runner = unittest.TextTestRunner()
 153     runner.run(suite)