src/soc/bus/opencores_ethmac.py

   1 #!/usr/bin/env python3
   2 #
   3 # SPDX-License-Identifier: LGPLv3+
   4 # Copyright (C) 2020-2022 Raptor Engineering LLC <support@raptorengineering.com>
   5 # Copyright (C) 2022 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   6 # Sponsored by NLnet and NGI POINTER under EU Grants 871528 and 957073
   7 # Part of the Libre-SOC Project.
   8 #
   9 # this is a wrapper around the opencores verilog 10/100 MAC
  10
  11 from nmigen import (Elaboratable, Cat, Module, Signal, ClockSignal, Instance,
  12                     ResetSignal)
  13
  14 from nmigen_soc.wishbone.bus import Interface
  15 from nmigen_soc.memory import MemoryMap
  16 from nmigen.utils import log2_int
  17 from nmigen.cli import rtlil, verilog
  18 import os
  19
  20 __all__ = ["EthMAC"]
  21
  22
  23 class EthMAC(Elaboratable):
  24     """Ethernet MAC from opencores, nmigen wrapper.
  25     remember to call EthMAC.add_verilog_source
  26     """
  27
  28     def __init__(self, master_bus=None, slave_bus=None, name=None,
  29                        irq=None, pins=None):
  30         if name is not None:
  31             # convention: give the name in the format "name_number"
  32             self.idx = int(name.split("_")[-1])
  33         else:
  34             self.idx = 0
  35             name = "eth_0"
  36         self.granularity = 8
  37         self.data_width = 32
  38         self.dsize = log2_int(self.data_width//self.granularity)
  39
  40         # set up the wishbone busses
  41         features = frozenset()
  42         if master_bus is None:
  43             master_bus = Interface(addr_width=30,
  44                             data_width=32,
  45                             features=features,
  46                             granularity=8,
  47                             name=name+"_wb_%d_0" % self.idx)
  48         if slave_bus is None:
  49             slave_bus = Interface(addr_width=12,
  50                             data_width=32,
  51                             features=features,
  52                             granularity=8,
  53                             name=name+"_wb_%d_1" % self.idx)
  54         self.master_bus = master_bus
  55         self.slave_bus = slave_bus
  56         if irq is None:
  57             irq = Signal()
  58         self.irq = irq
  59
  60         slave_mmap = MemoryMap(addr_width=12+self.dsize,
  61                         data_width=self.granularity)
  62
  63         self.slave_bus.memory_map = slave_mmap
  64
  65         # RMII TX signals
  66         self.mtx_clk = Signal()
  67         self.mtxd = Signal(4)
  68         self.mtxen = Signal()
  69         self.mtxerr = Signal()
  70
  71         # RMII RX signals
  72         self.mrx_clk = Signal()
  73         self.mrxd = Signal(4)
  74         self.mrxdv = Signal()
  75         self.mrxerr = Signal()
  76
  77         # RMII common signals
  78         self.mcoll = Signal()
  79         self.mcrs = Signal()
  80
  81         # RMII management interface signals
  82         self.mdc = Signal()
  83         self.md_in = Signal()
  84         self.md_out = Signal()
  85         self.md_direction = Signal()
  86
  87         # pins resource
  88         self.pins = pins
  89
  90     @classmethod
  91     def add_verilog_source(cls, verilog_src_dir, platform):
  92         # add each of the verilog sources, needed for when doing platform.build
  93         for fname in ['eth_clockgen.v', 'eth_cop.v', 'eth_crc.v',
  94                     'eth_fifo.v', 'eth_maccontrol.v', 'ethmac_defines.v',
  95                     'eth_macstatus.v', 'ethmac.v', 'eth_miim.v',
  96                     'eth_outputcontrol.v', 'eth_random.v',
  97                     'eth_receivecontrol.v', 'eth_registers.v',
  98                     'eth_register.v', 'eth_rxaddrcheck.v',
  99                     'eth_rxcounters.v', 'eth_rxethmac.v',
 100                     'eth_rxstatem.v', 'eth_shiftreg.v',
 101                     'eth_spram_256x32.v', 'eth_top.v',
 102                     'eth_transmitcontrol.v', 'eth_txcounters.v',
 103                     'eth_txethmac.v', 'eth_txstatem.v', 'eth_wishbone.v',
 104                     'timescale.v']:
 105             # prepend the src directory to each filename, add its contents
 106             fullname = os.path.join(verilog_src_dir, fname)
 107             with open(fullname) as f:
 108                 platform.add_file(fullname, f)
 109
 110     def elaborate(self, platform):
 111         m = Module()
 112         comb = m.d.comb
 113         idx = self.idx
 114
 115         # Calculate arbiter bus address
 116         wb_master_bus_adr = Signal(32)
 117         # arbiter address is in words, ethernet master address is in bytes
 118         comb += self.master_bus.adr.eq(wb_master_bus_adr >> 2)
 119
 120         # create definition of external verilog EthMAC code here, so that
 121         # nmigen understands I/O directions (defined by i_ and o_ prefixes)
 122         ethmac = Instance("eth_top",
 123                             # Clock/reset (use DomainRenamer if needed)
 124                             i_wb_clk_i=ClockSignal(),
 125                             i_wb_rst_i=ResetSignal(),
 126
 127                             # Master Wishbone bus signals
 128                             o_m_wb_adr_o=wb_master_bus_adr,
 129                             i_m_wb_dat_i=self.master_bus.dat_r,
 130                             o_m_wb_sel_o=self.master_bus.sel,
 131                             o_m_wb_dat_o=self.master_bus.dat_w,
 132                             o_m_wb_we_o=self.master_bus.we,
 133                             o_m_wb_stb_o=self.master_bus.stb,
 134                             o_m_wb_cyc_o=self.master_bus.cyc,
 135                             i_m_wb_ack_i=self.master_bus.ack,
 136
 137                             # Slave Wishbone bus signals
 138                             i_wb_adr_i=self.slave_bus.adr,
 139                             i_wb_dat_i=self.slave_bus.dat_w,
 140                             i_wb_sel_i=self.slave_bus.sel,
 141                             o_wb_dat_o=self.slave_bus.dat_r,
 142                             i_wb_we_i=self.slave_bus.we,
 143                             i_wb_stb_i=self.slave_bus.stb,
 144                             i_wb_cyc_i=self.slave_bus.cyc,
 145                             o_wb_ack_o=self.slave_bus.ack,
 146
 147                             o_int_o=self.irq,
 148
 149                             # RMII TX
 150                             i_mtx_clk_pad_i=self.mtx_clk,
 151                             o_mtxd_pad_o=self.mtxd,
 152                             o_mtxen_pad_o=self.mtxen,
 153                             o_mtxerr_pad_o=self.mtxerr,
 154
 155                             # RMII RX
 156                             i_mrx_clk_pad_i=self.mrx_clk,
 157                             i_mrxd_pad_i=self.mrxd,
 158                             i_mrxdv_pad_i=self.mrxdv,
 159                             i_mrxerr_pad_i=self.mrxerr,
 160
 161                             # RMII common
 162                             i_mcoll_pad_i=self.mcoll,
 163                             i_mcrs_pad_i=self.mcrs,
 164
 165                             # Management Interface
 166                             o_mdc_pad_o=self.mdc,
 167                             i_md_pad_i=self.md_in,
 168                             o_md_pad_o=self.md_out,
 169                             o_md_padoe_o=self.md_direction
 170                             );
 171
 172         m.submodules['ethmac_%d' % self.idx] = ethmac
 173
 174         if self.pins is not None:
 175             comb += self.mtx_clk.eq(self.pins.mtx_clk.i)
 176             comb += self.pins.mtxd.o.eq(self.mtxd)
 177             comb += self.pins.mtxen.o.eq(self.mtxen)
 178             comb += self.pins.mtxerr.o.eq(self.mtxerr)
 179
 180             comb += self.mrx_clk.eq(self.pins.mrx_clk.i)
 181             comb += self.mrxd.eq(self.pins.mrxd.i)
 182             comb += self.mrxdv.eq(self.pins.mrxdv.i)
 183             comb += self.mrxerr.eq(self.pins.mrxerr.i)
 184             comb += self.mcoll.eq(self.pins.mcoll.i)
 185             comb += self.mcrs.eq(self.pins.mcrs.i)
 186
 187             comb += self.pins.mdc.o.eq(self.mdc)
 188
 189             comb += self.pins.md.o.eq(self.md_out)
 190             comb += self.pins.md.oe.eq(self.md_direction)
 191             comb += self.md_in.eq(self.pins.md.i)
 192         return m
 193
 194
 195 def create_ilang(dut, ports, test_name):
 196     vl = rtlil.convert(dut, name=test_name, ports=ports)
 197     with open("%s.il" % test_name, "w") as f:
 198         f.write(vl)
 199
 200 def create_verilog(dut, ports, test_name):
 201     vl = verilog.convert(dut, name=test_name, ports=ports)
 202     with open("%s.v" % test_name, "w") as f:
 203         f.write(vl)
 204
 205 if __name__ == "__main__":
 206     ethmac = EthMAC(name="eth_0")
 207     create_ilang(ethmac, [ethmac.master_bus.cyc, ethmac.master_bus.stb,
 208                         ethmac.master_bus.ack, ethmac.master_bus.dat_r,
 209                         ethmac.master_bus.dat_w, ethmac.master_bus.adr,
 210                         ethmac.master_bus.we, ethmac.master_bus.sel,
 211                         ethmac.slave_bus.cyc, ethmac.slave_bus.stb,
 212                         ethmac.slave_bus.ack,
 213                         ethmac.slave_bus.dat_r, ethmac.slave_bus.dat_w,
 214                         ethmac.slave_bus.adr,
 215                         ethmac.slave_bus.we, ethmac.slave_bus.sel,
 216                         ethmac.mtx_clk, ethmac.mtxd, ethmac.mtxen,
 217                         ethmac.mtxerr, ethmac.mrx_clk, ethmac.mrxd,
 218                         ethmac.mrxdv, ethmac.mrxerr, ethmac.mcoll,
 219                         ethmac.mcrs, ethmac.mdc, ethmac.md_in,
 220                         ethmac.md_out, ethmac.md_direction
 221                        ], "eth_0")
 222