src/soc/bus/test/test_sram_wishbone.py

   1 """demonstration of nmigen-soc SRAM behind a wishbone bus
   2 Bugs:
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=382
   4 """
   5 from nmigen_soc.wishbone.sram import SRAM
   6 from nmigen import Memory, Signal, Module
   7
   8 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
   9 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  10 from nmutil.sim_tmp_alternative import Simulator, Settle
  11
  12 memory = Memory(width=64, depth=16)
  13 sram = SRAM(memory=memory, granularity=16)
  14
  15 # valid wishbone signals include
  16 # sram.bus.adr
  17 # sram.bus.dat_w
  18 # sram.bus.dat_r
  19 # sram.bus.sel
  20 # sram.bus.cyc
  21 # sram.bus.stb
  22 # sram.bus.we
  23 # sram.bus.ack
  24
  25 # setup simulation
  26 m = Module()
  27 m.submodules.sram = sram
  28 sim = Simulator(m)
  29 sim.add_clock(1e-6)
  30
  31 def print_sig(sig, format=None):
  32     if format == None:
  33         print(f"{sig.__repr__()} = {(yield sig)}")
  34     if format == "h":
  35         print(f"{sig.__repr__()} = {hex((yield sig))}")
  36
  37 def process():
  38     # enable necessary signals for write
  39     for en in range(4):
  40         yield sram.bus.sel[en].eq(1)
  41     yield sram.bus.we.eq(1)
  42     yield sram.bus.cyc.eq(1)
  43     yield sram.bus.stb.eq(1)
  44
  45     # put data and address on bus
  46     yield sram.bus.adr.eq(0x4)
  47     yield sram.bus.dat_w.eq(0xdeadbeef)
  48     yield
  49
  50     # set necessary signal to read bus
  51     # at address 0
  52     yield sram.bus.we.eq(0)
  53     yield sram.bus.adr.eq(0)
  54     yield sram.bus.cyc.eq(1)
  55     yield sram.bus.stb.eq(1)
  56     yield
  57
  58     # see sync_behaviors.py
  59     # for why we need Settle()
  60     # debug print the bus address/data
  61     yield Settle()
  62     yield from print_sig(sram.bus.adr)
  63     yield from print_sig(sram.bus.dat_r, "h")
  64
  65     # check the result
  66     data = yield sram.bus.dat_r
  67     assert data == 0
  68
  69     # set necessary signal to read bus
  70     # at address 4
  71     yield sram.bus.we.eq(0)
  72     yield sram.bus.adr.eq(0x4)
  73     yield sram.bus.cyc.eq(1)
  74     yield sram.bus.stb.eq(1)
  75     yield
  76
  77     # see sync_behaviors.py
  78     # for why we need Settle()
  79     # debug print the bus address/data
  80     yield Settle()
  81     yield from print_sig(sram.bus.adr)
  82     yield from print_sig(sram.bus.dat_r, "h")
  83
  84     # check the result
  85     data = yield sram.bus.dat_r
  86     assert data == 0xdeadbeef
  87
  88     # disable signals
  89     yield sram.bus.cyc.eq(0)
  90     yield sram.bus.stb.eq(0)
  91     yield
  92
  93 sim_writer = sim.write_vcd(f"{__file__[:-3]}.vcd")
  94
  95 with sim_writer:
  96     sim.add_sync_process(process)
  97     sim.run()