1 from nmigen
import Signal
, Module
, Record
2 from nmigen
.back
.pysim
import Simulator
, Delay
3 from nmigen
.compat
.sim
import run_simulation
, Settle
4 from nmutil
.formaltest
import FHDLTestCase
5 from nmigen
.cli
import rtlil
7 from soc
.config
.test
.test_loadstore
import TestMemPspec
8 from soc
.config
.loadstore
import ConfigMemoryPortInterface
11 def wait_busy(port
, no
=False):
13 busy
= yield port
.pi
.busy_o
14 print("busy", no
, busy
)
22 addr_ok
= yield port
.pi
.addr_ok_o
23 print("addrok", addr_ok
)
31 ldok
= yield port
.pi
.ld
.ok
38 def l0_cache_st(dut
, addr
, data
, datalen
):
39 if isinstance(dut
.pi
, Record
):
44 # have to wait until not busy
45 yield from wait_busy(port1
, no
=False) # wait until not busy
47 # set up a ST on the port. address first:
48 yield port1
.pi
.is_st_i
.eq(1) # indicate ST
49 yield port1
.pi
.data_len
.eq(datalen
) # ST length (1/2/4/8)
51 yield port1
.pi
.addr
.data
.eq(addr
) # set address
52 yield port1
.pi
.addr
.ok
.eq(1) # set ok
54 yield from wait_addr(port1
) # wait until addr ok
55 # yield # not needed, just for checking
56 # yield # not needed, just for checking
57 # assert "ST" for one cycle (required by the API)
58 yield port1
.pi
.st
.data
.eq(data
)
59 yield port1
.pi
.st
.ok
.eq(1)
61 yield port1
.pi
.st
.ok
.eq(0)
63 # can go straight to reset.
64 yield port1
.pi
.is_st_i
.eq(0) # end
65 yield port1
.pi
.addr
.ok
.eq(0) # set !ok
66 # yield from wait_busy(port1, False) # wait until not busy
69 def l0_cache_ld(dut
, addr
, datalen
):
71 if isinstance(dut
.pi
, Record
):
76 # have to wait until not busy
77 yield from wait_busy(port1
, no
=False) # wait until not busy
79 # set up a LD on the port. address first:
80 yield port1
.pi
.is_ld_i
.eq(1) # indicate LD
81 yield port1
.pi
.data_len
.eq(datalen
) # LD length (1/2/4/8)
83 yield port1
.pi
.addr
.data
.eq(addr
) # set address
84 yield port1
.pi
.addr
.ok
.eq(1) # set ok
86 yield from wait_addr(port1
) # wait until addr ok
88 yield from wait_ldok(port1
) # wait until ld ok
89 data
= yield port1
.pi
.ld
.data
92 yield port1
.pi
.is_ld_i
.eq(0) # end
93 yield port1
.pi
.addr
.ok
.eq(0) # set !ok
94 # yield from wait_busy(port1, no=False) # wait until not busy
99 def l0_cache_ldst(arg
, dut
):
101 # do two half-word stores at consecutive addresses, then two loads
107 yield from l0_cache_st(dut
, addr1
, data
, 2)
108 yield from l0_cache_st(dut
, addr2
, data2
, 2)
109 result
= yield from l0_cache_ld(dut
, addr1
, 2)
110 result2
= yield from l0_cache_ld(dut
, addr2
, 2)
111 arg
.assertEqual(data
, result
, "data %x != %x" % (result
, data
))
112 arg
.assertEqual(data2
, result2
, "data2 %x != %x" % (result2
, data2
))
114 # now load both in a 32-bit load to make sure they're really consecutive
115 data3
= data |
(data2
<< 16)
116 result3
= yield from l0_cache_ld(dut
, addr1
, 4)
117 arg
.assertEqual(data3
, result3
, "data3 %x != %x" % (result3
, data3
))
120 def tst_config_pi(testcls
, ifacetype
):
121 """set up a configureable memory test of type ifacetype
124 pspec
= TestMemPspec(ldst_ifacetype
=ifacetype
,
128 cmpi
= ConfigMemoryPortInterface(pspec
)
129 dut
.submodules
.pi
= cmpi
.pi
130 if hasattr(cmpi
, 'lsmem'): # hmmm not happy about this
131 dut
.submodules
.lsmem
= cmpi
.lsmem
.lsi
132 vl
= rtlil
.convert(dut
, ports
=[])#dut.ports())
133 with
open("test_pi_%s.il" % ifacetype
, "w") as f
:
136 run_simulation(dut
, {"sync": l0_cache_ldst(testcls
, cmpi
.pi
)},
137 vcd_name
='test_pi_%s.vcd' % ifacetype
)
140 class TestPIMem(unittest
.TestCase
):
142 def test_pi_mem(self
):
143 tst_config_pi(self
, 'testpi')
145 def test_pi2ls(self
):
146 tst_config_pi(self
, 'testmem')
148 def test_pi2ls_bare_wb(self
):
149 tst_config_pi(self
, 'test_bare_wb')
152 if __name__
== '__main__':
153 unittest
.main(exit
=False)