src/soc/config/test/test_pi2ls.py

   1 from nmigen import Signal, Module, Record
   2 from nmigen.back.pysim import Simulator, Delay
   3 from nmigen.compat.sim import run_simulation, Settle
   4 from nmutil.formaltest import FHDLTestCase
   5 from nmigen.cli import rtlil
   6 import unittest
   7 from soc.config.test.test_loadstore import TestMemPspec
   8 from soc.config.loadstore import ConfigMemoryPortInterface
   9 from openpower.exceptions import LDSTExceptionTuple
  10
  11
  12 def wait_busy(port, no=False, debug=None):
  13     cnt = 0
  14     while True:
  15         busy = yield port.busy_o
  16         print("busy", no, busy, cnt, debug)
  17         if bool(busy) == no:
  18             break
  19         yield
  20         cnt += 1
  21
  22
  23 def wait_addr(port,debug=None):
  24     cnt = 0
  25     while True:
  26         addr_ok = yield port.addr_ok_o
  27         print("addrok", addr_ok,cnt,debug)
  28         if addr_ok:
  29             break
  30         yield
  31         cnt += 1
  32
  33
  34 def wait_ldok(port):
  35     cnt = 0
  36     while True:
  37         ldok = yield port.ld.ok
  38         exc_happened = yield port.exc_o.happened
  39         print("ldok", ldok, "exception", exc_happened, "count", cnt)
  40         cnt += 1
  41         if ldok or exc_happened:
  42             break
  43         yield
  44
  45
  46 def pi_st(port1, addr, data, datalen, msr_pr=0, is_dcbz=0):
  47
  48     # have to wait until not busy
  49     yield from wait_busy(port1,debug="pi_st_A") # wait while busy
  50
  51     # set up a ST on the port.  address first:
  52     yield port1.is_dcbz_i.eq(is_dcbz)  # reset dcbz too
  53     yield port1.is_st_i.eq(1)  # indicate ST
  54     yield port1.data_len.eq(datalen)  # ST length (1/2/4/8)
  55     yield port1.msr_pr.eq(msr_pr)  # MSR PR bit (1==>virt, 0==>real)
  56
  57     yield port1.addr.data.eq(addr)  # set address
  58     yield port1.addr.ok.eq(1)  # set ok
  59     yield Settle()
  60
  61     # must check exception even before waiting for address.
  62     # XXX TODO: wait_addr should check for exception
  63     exc_info = yield from get_exception_info(port1.exc_o)
  64     exc_happened = exc_info.happened
  65     dar_o = yield port1.dar_o
  66     if exc_happened:
  67         print("print fast ST exception happened")
  68         yield # MUST wait for one clock cycle before de-asserting these
  69         yield port1.is_st_i.eq(0)  # end
  70         yield port1.addr.ok.eq(0)  # set !ok
  71         yield port1.is_dcbz_i.eq(0)  # reset dcbz too
  72         return "fast", exc_info, dar_o
  73
  74     yield from wait_addr(port1)             # wait until addr ok
  75
  76     exc_info = yield from get_exception_info(port1.exc_o)
  77     exc_happened = exc_info.happened
  78     dar_o = yield port1.dar_o
  79     if exc_happened:
  80         print("print fast ST exception happened")
  81         yield # MUST wait for one clock cycle before de-asserting these
  82         yield port1.is_st_i.eq(0)  # end
  83         yield port1.addr.ok.eq(0)  # set !ok
  84         yield port1.is_dcbz_i.eq(0)  # reset dcbz too
  85         return "fast", exc_info, dar_o
  86
  87
  88     # yield # not needed, just for checking
  89     # yield # not needed, just for checking
  90     # assert "ST" for one cycle (required by the API)
  91     yield port1.st.data.eq(data)
  92     yield port1.st.ok.eq(1)
  93     yield
  94     yield port1.st.ok.eq(0)
  95     exc_info = yield from get_exception_info(port1.exc_o)
  96     dar_o = yield port1.dar_o
  97     exc_happened = exc_info.happened
  98     if exc_happened:
  99         print("print fast ST exception happened")
 100         yield # MUST wait for one clock cycle before de-asserting these
 101         yield port1.is_st_i.eq(0)  # end
 102         yield port1.addr.ok.eq(0)  # set !ok
 103         yield port1.is_dcbz_i.eq(0)  # reset dcbz too
 104         return "fast", exc_info, dar_o
 105
 106     yield from wait_busy(port1,debug="pi_st_E") # wait while busy
 107     exc_info = yield from get_exception_info(port1.exc_o)
 108     dar_o = yield port1.dar_o
 109     exc_happened = exc_info.happened
 110     if exc_happened:
 111         yield  # needed if mmu/dache is used
 112         yield port1.is_st_i.eq(0)  # end
 113         yield port1.addr.ok.eq(0)  # set !ok
 114         yield port1.is_dcbz_i.eq(0)  # reset dcbz too
 115         yield  # needed if mmu/dache is used
 116         return "slow", exc_info, dar_o
 117
 118     # can go straight to reset.
 119     yield port1.is_st_i.eq(0)  # end
 120     yield port1.addr.ok.eq(0)  # set !ok
 121     yield port1.is_dcbz_i.eq(0)  # reset dcbz too
 122     yield  # needed if mmu/dache is used
 123
 124     return None, None, None
 125
 126 def get_exception_info(exc_o):
 127     attrs = []
 128     for fname in LDSTExceptionTuple._fields:
 129         attr = getattr(exc_o, fname)
 130         val = yield attr
 131         attrs.append(val)
 132     return LDSTExceptionTuple(*attrs)
 133
 134
 135 # copy of pi_st removed
 136
 137 def pi_ld(port1, addr, datalen, msr_pr=0):
 138
 139     # have to wait until not busy
 140     yield from wait_busy(port1,debug="pi_ld_A") # wait while busy
 141
 142     # set up a LD on the port.  address first:
 143     yield port1.is_ld_i.eq(1)  # indicate LD
 144     yield port1.data_len.eq(datalen)  # LD length (1/2/4/8)
 145     yield port1.msr_pr.eq(msr_pr)  # MSR PR bit (1==>virt, 0==>real)
 146
 147     yield port1.addr.data.eq(addr)  # set address
 148     yield port1.addr.ok.eq(1)  # set ok
 149     yield Settle()
 150     yield from wait_addr(port1)             # wait until addr ok
 151     exc_info = yield from get_exception_info(port1.exc_o)
 152     dar_o = yield port1.dar_o
 153     exc_happened = exc_info.happened
 154     if exc_happened:
 155         print("print fast LD exception happened")
 156         yield # MUST wait for one clock cycle before de-asserting these
 157         yield port1.is_ld_i.eq(0)  # end
 158         yield port1.addr.ok.eq(0)  # set !ok
 159         return None, "fast", exc_info, dar_o
 160
 161     yield
 162     yield from wait_ldok(port1)             # wait until ld ok
 163     data = yield port1.ld.data
 164     exc_info = yield from get_exception_info(port1.exc_o)
 165     dar_o = yield port1.dar_o
 166     exc_happened = yield port1.exc_o.happened
 167     exc_happened = exc_info.happened
 168
 169     # cleanup
 170     yield port1.is_ld_i.eq(0)  # end
 171     yield port1.addr.ok.eq(0)  # set !ok
 172     if exc_happened:
 173         return None, "slow", exc_info, dar_o
 174
 175     yield from wait_busy(port1, debug="pi_ld_E") # wait while busy
 176
 177     exc_info = yield from get_exception_info(port1.exc_o)
 178     dar_o = yield port1.dar_o
 179     exc_happened = exc_info.happened
 180     if exc_happened:
 181         return None, "slow", exc_info, dar_o
 182
 183     return data, None, None, None
 184
 185
 186 def pi_ldst(arg, dut, msr_pr=0):
 187
 188     # do two half-word stores at consecutive addresses, then two loads
 189     addr1 = 0x04
 190     addr2 = addr1 + 0x2
 191     data = 0xbeef
 192     data2 = 0xf00f
 193     #data = 0x4
 194     assert(yield from pi_st(dut, addr1, data, 2, msr_pr) is None)
 195     assert(yield from pi_st(dut, addr2, data2, 2, msr_pr) is None)
 196     result, exc = yield from pi_ld(dut, addr1, 2, msr_pr)
 197     result2, exc2 = yield from pi_ld(dut, addr2, 2, msr_pr)
 198     assert(exc is None)
 199     assert(exc2 is None)
 200     arg.assertEqual(data, result, "data %x != %x" % (result, data))
 201     arg.assertEqual(data2, result2, "data2 %x != %x" % (result2, data2))
 202
 203     # now load both in a 32-bit load to make sure they're really consecutive
 204     data3 = data | (data2 << 16)
 205     result3, exc3 = yield from pi_ld(dut, addr1, 4, msr_pr)
 206     assert(exc3 is None)
 207     arg.assertEqual(data3, result3, "data3 %x != %x" % (result3, data3))
 208
 209
 210 def tst_config_pi(testcls, ifacetype):
 211     """set up a configureable memory test of type ifacetype
 212     """
 213     dut = Module()
 214     pspec = TestMemPspec(ldst_ifacetype=ifacetype,
 215                          imem_ifacetype='',
 216                          addr_wid=48,
 217                          mask_wid=8,
 218                          reg_wid=64)
 219     cmpi = ConfigMemoryPortInterface(pspec)
 220     dut.submodules.pi = cmpi.pi
 221     if hasattr(cmpi, 'lsmem'):  # hmmm not happy about this
 222         dut.submodules.lsmem = cmpi.lsmem.lsi
 223     vl = rtlil.convert(dut, ports=[])  # dut.ports())
 224     with open("test_pi_%s.il" % ifacetype, "w") as f:
 225         f.write(vl)
 226
 227     run_simulation(dut, {"sync": pi_ldst(testcls, cmpi.pi.pi)},
 228                    vcd_name='test_pi_%s.vcd' % ifacetype)
 229
 230
 231 class TestPIMem(unittest.TestCase):
 232
 233     def test_pi_mem(self):
 234         tst_config_pi(self, 'testpi')
 235
 236     def test_pi2ls(self):
 237         tst_config_pi(self, 'testmem')
 238
 239     def test_pi2ls_bare_wb(self):
 240         tst_config_pi(self, 'test_bare_wb')
 241
 242
 243 if __name__ == '__main__':
 244     unittest.main()