src/soc/config/test/test_pi2ls.py

   1 from nmigen import Signal, Module, Record
   2 from nmigen.back.pysim import Simulator, Delay
   3 from nmigen.compat.sim import run_simulation, Settle
   4 from nmutil.formaltest import FHDLTestCase
   5 from nmigen.cli import rtlil
   6 import unittest
   7 from soc.config.test.test_loadstore import TestMemPspec
   8 from soc.config.loadstore import ConfigMemoryPortInterface
   9
  10
  11 def wait_busy(port, no=False):
  12     while True:
  13         busy = yield port.busy_o
  14         print("busy", no, busy)
  15         if bool(busy) == no:
  16             break
  17         yield
  18
  19
  20 def wait_addr(port):
  21     while True:
  22         addr_ok = yield port.addr_ok_o
  23         print("addrok", addr_ok)
  24         if addr_ok:
  25             break
  26         yield
  27
  28
  29 def wait_ldok(port):
  30     while True:
  31         ldok = yield port.ld.ok
  32         print("ldok", ldok)
  33         if ldok:
  34             break
  35         yield
  36
  37
  38 def pi_st(port1, addr, data, datalen, msr_pr=0):
  39
  40     # have to wait until not busy
  41     yield from wait_busy(port1, no=False)    # wait until not busy
  42
  43     # set up a ST on the port.  address first:
  44     yield port1.is_st_i.eq(1)  # indicate ST
  45     yield port1.data_len.eq(datalen)  # ST length (1/2/4/8)
  46     yield port1.msr_pr.eq(msr_pr)  # MSR PR bit (1==>virt, 0==>real)
  47
  48     yield port1.addr.data.eq(addr)  # set address
  49     yield port1.addr.ok.eq(1)  # set ok
  50     yield Settle()
  51     yield from wait_addr(port1)             # wait until addr ok
  52     # yield # not needed, just for checking
  53     # yield # not needed, just for checking
  54     # assert "ST" for one cycle (required by the API)
  55     yield port1.st.data.eq(data)
  56     yield port1.st.ok.eq(1)
  57     yield
  58     yield port1.st.ok.eq(0)
  59     yield from wait_busy(port1, True)    # wait while busy
  60
  61     # can go straight to reset.
  62     yield port1.is_st_i.eq(0)  # end
  63     yield port1.addr.ok.eq(0)  # set !ok
  64
  65
  66 def pi_ld(port1, addr, datalen, msr_pr=0):
  67
  68     # have to wait until not busy
  69     yield from wait_busy(port1, no=False)    # wait until not busy
  70
  71     # set up a LD on the port.  address first:
  72     yield port1.is_ld_i.eq(1)  # indicate LD
  73     yield port1.data_len.eq(datalen)  # LD length (1/2/4/8)
  74     yield port1.msr_pr.eq(msr_pr)  # MSR PR bit (1==>virt, 0==>real)
  75
  76     yield port1.addr.data.eq(addr)  # set address
  77     yield port1.addr.ok.eq(1)  # set ok
  78     yield Settle()
  79     yield from wait_addr(port1)             # wait until addr ok
  80     yield
  81     yield from wait_ldok(port1)             # wait until ld ok
  82     data = yield port1.ld.data
  83
  84     # cleanup
  85     yield port1.is_ld_i.eq(0)  # end
  86     yield port1.addr.ok.eq(0)  # set !ok
  87     yield from wait_busy(port1, no=False)    # wait while not busy
  88
  89     return data
  90
  91
  92 def pi_ldst(arg, dut, msr_pr=0):
  93
  94     # do two half-word stores at consecutive addresses, then two loads
  95     addr1 = 0x04
  96     addr2 = addr1 + 0x2
  97     data = 0xbeef
  98     data2 = 0xf00f
  99     #data = 0x4
 100     yield from pi_st(dut, addr1, data, 2, msr_pr)
 101     yield from pi_st(dut, addr2, data2, 2, msr_pr)
 102     result = yield from pi_ld(dut, addr1, 2, msr_pr)
 103     result2 = yield from pi_ld(dut, addr2, 2, msr_pr)
 104     arg.assertEqual(data, result, "data %x != %x" % (result, data))
 105     arg.assertEqual(data2, result2, "data2 %x != %x" % (result2, data2))
 106
 107     # now load both in a 32-bit load to make sure they're really consecutive
 108     data3 = data | (data2 << 16)
 109     result3 = yield from pi_ld(dut, addr1, 4, msr_pr)
 110     arg.assertEqual(data3, result3, "data3 %x != %x" % (result3, data3))
 111
 112
 113 def tst_config_pi(testcls, ifacetype):
 114     """set up a configureable memory test of type ifacetype
 115     """
 116     dut = Module()
 117     pspec = TestMemPspec(ldst_ifacetype=ifacetype,
 118                          imem_ifacetype='',
 119                          addr_wid=48,
 120                          mask_wid=8,
 121                          reg_wid=64)
 122     cmpi = ConfigMemoryPortInterface(pspec)
 123     dut.submodules.pi = cmpi.pi
 124     if hasattr(cmpi, 'lsmem'):  # hmmm not happy about this
 125         dut.submodules.lsmem = cmpi.lsmem.lsi
 126     vl = rtlil.convert(dut, ports=[])  # dut.ports())
 127     with open("test_pi_%s.il" % ifacetype, "w") as f:
 128         f.write(vl)
 129
 130     run_simulation(dut, {"sync": pi_ldst(testcls, cmpi.pi.pi)},
 131                    vcd_name='test_pi_%s.vcd' % ifacetype)
 132
 133
 134 class TestPIMem(unittest.TestCase):
 135
 136     def test_pi_mem(self):
 137         tst_config_pi(self, 'testpi')
 138
 139     def test_pi2ls(self):
 140         tst_config_pi(self, 'testmem')
 141
 142     def test_pi2ls_bare_wb(self):
 143         tst_config_pi(self, 'test_bare_wb')
 144
 145
 146 if __name__ == '__main__':
 147     unittest.main()