src/soc/config/test/test_pi2ls.py

   1 from nmigen import Signal, Module, Record
   2 from nmigen.back.pysim import Simulator, Delay
   3 from nmigen.compat.sim import run_simulation, Settle
   4 from nmutil.formaltest import FHDLTestCase
   5 from nmigen.cli import rtlil
   6 import unittest
   7 from soc.config.test.test_loadstore import TestMemPspec
   8 from soc.config.loadstore import ConfigMemoryPortInterface
   9
  10
  11 def wait_busy(port, no=False):
  12     while True:
  13         busy = yield port.busy_o
  14         print("busy", no, busy)
  15         if bool(busy) == no:
  16             break
  17         yield
  18
  19
  20 def wait_addr(port):
  21     while True:
  22         addr_ok = yield port.addr_ok_o
  23         print("addrok", addr_ok)
  24         if addr_ok:
  25             break
  26         yield
  27
  28
  29 def wait_ldok(port):
  30     while True:
  31         ldok = yield port.ld.ok
  32         exc_happened = yield port.exc_o.happened
  33         print("ldok", ldok, "exception", exc_happened)
  34         if ldok or exc_happened:
  35             break
  36         yield
  37
  38
  39 def pi_st(port1, addr, data, datalen, msr_pr=0):
  40
  41     # have to wait until not busy
  42     yield from wait_busy(port1, no=False)    # wait until not busy
  43
  44     # set up a ST on the port.  address first:
  45     yield port1.is_st_i.eq(1)  # indicate ST
  46     yield port1.data_len.eq(datalen)  # ST length (1/2/4/8)
  47     yield port1.msr_pr.eq(msr_pr)  # MSR PR bit (1==>virt, 0==>real)
  48
  49     yield port1.addr.data.eq(addr)  # set address
  50     yield port1.addr.ok.eq(1)  # set ok
  51     yield Settle()
  52     yield from wait_addr(port1)             # wait until addr ok
  53     # yield # not needed, just for checking
  54     # yield # not needed, just for checking
  55     # assert "ST" for one cycle (required by the API)
  56     yield port1.st.data.eq(data)
  57     yield port1.st.ok.eq(1)
  58     yield
  59     yield port1.st.ok.eq(0)
  60     yield from wait_busy(port1, True)    # wait while busy
  61
  62     # can go straight to reset.
  63     yield port1.is_st_i.eq(0)  # end
  64     yield port1.addr.ok.eq(0)  # set !ok
  65
  66
  67 def pi_ld(port1, addr, datalen, msr_pr=0):
  68
  69     # have to wait until not busy
  70     yield from wait_busy(port1, no=False)    # wait until not busy
  71
  72     # set up a LD on the port.  address first:
  73     yield port1.is_ld_i.eq(1)  # indicate LD
  74     yield port1.data_len.eq(datalen)  # LD length (1/2/4/8)
  75     yield port1.msr_pr.eq(msr_pr)  # MSR PR bit (1==>virt, 0==>real)
  76
  77     yield port1.addr.data.eq(addr)  # set address
  78     yield port1.addr.ok.eq(1)  # set ok
  79     yield Settle()
  80     yield from wait_addr(port1)             # wait until addr ok
  81     yield
  82     yield from wait_ldok(port1)             # wait until ld ok
  83     data = yield port1.ld.data
  84     exc_happened = yield port1.exc_o.happened
  85
  86     # cleanup
  87     yield port1.is_ld_i.eq(0)  # end
  88     yield port1.addr.ok.eq(0)  # set !ok
  89     if exc_happened:
  90         return 0
  91
  92     yield from wait_busy(port1, no=False)    # wait while not busy
  93
  94     return data
  95
  96
  97 def pi_ldst(arg, dut, msr_pr=0):
  98
  99     # do two half-word stores at consecutive addresses, then two loads
 100     addr1 = 0x04
 101     addr2 = addr1 + 0x2
 102     data = 0xbeef
 103     data2 = 0xf00f
 104     #data = 0x4
 105     yield from pi_st(dut, addr1, data, 2, msr_pr)
 106     yield from pi_st(dut, addr2, data2, 2, msr_pr)
 107     result = yield from pi_ld(dut, addr1, 2, msr_pr)
 108     result2 = yield from pi_ld(dut, addr2, 2, msr_pr)
 109     arg.assertEqual(data, result, "data %x != %x" % (result, data))
 110     arg.assertEqual(data2, result2, "data2 %x != %x" % (result2, data2))
 111
 112     # now load both in a 32-bit load to make sure they're really consecutive
 113     data3 = data | (data2 << 16)
 114     result3 = yield from pi_ld(dut, addr1, 4, msr_pr)
 115     arg.assertEqual(data3, result3, "data3 %x != %x" % (result3, data3))
 116
 117
 118 def tst_config_pi(testcls, ifacetype):
 119     """set up a configureable memory test of type ifacetype
 120     """
 121     dut = Module()
 122     pspec = TestMemPspec(ldst_ifacetype=ifacetype,
 123                          imem_ifacetype='',
 124                          addr_wid=48,
 125                          mask_wid=8,
 126                          reg_wid=64)
 127     cmpi = ConfigMemoryPortInterface(pspec)
 128     dut.submodules.pi = cmpi.pi
 129     if hasattr(cmpi, 'lsmem'):  # hmmm not happy about this
 130         dut.submodules.lsmem = cmpi.lsmem.lsi
 131     vl = rtlil.convert(dut, ports=[])  # dut.ports())
 132     with open("test_pi_%s.il" % ifacetype, "w") as f:
 133         f.write(vl)
 134
 135     run_simulation(dut, {"sync": pi_ldst(testcls, cmpi.pi.pi)},
 136                    vcd_name='test_pi_%s.vcd' % ifacetype)
 137
 138
 139 class TestPIMem(unittest.TestCase):
 140
 141     def test_pi_mem(self):
 142         tst_config_pi(self, 'testpi')
 143
 144     def test_pi2ls(self):
 145         tst_config_pi(self, 'testmem')
 146
 147     def test_pi2ls_bare_wb(self):
 148         tst_config_pi(self, 'test_bare_wb')
 149
 150
 151 if __name__ == '__main__':
 152     unittest.main()