1 from nmigen
import Signal
, Module
, Record
2 from nmigen
.back
.pysim
import Simulator
, Delay
3 from nmigen
.compat
.sim
import run_simulation
, Settle
4 from nmutil
.formaltest
import FHDLTestCase
5 from nmigen
.cli
import rtlil
7 from soc
.config
.test
.test_loadstore
import TestMemPspec
8 from soc
.config
.loadstore
import ConfigMemoryPortInterface
11 def wait_busy(port
, no
=False, debug
=None):
14 busy
= yield port
.busy_o
15 print("busy", no
, busy
, cnt
, debug
)
22 def wait_addr(port
,debug
=None):
25 addr_ok
= yield port
.addr_ok_o
26 print("addrok", addr_ok
,cnt
,debug
)
36 ldok
= yield port
.ld
.ok
37 exc_happened
= yield port
.exc_o
.happened
38 print("ldok", ldok
, "exception", exc_happened
, "count", cnt
)
40 if ldok
or exc_happened
:
45 def pi_st(port1
, addr
, data
, datalen
, msr_pr
=0, is_dcbz
=0):
47 # have to wait until not busy
48 yield from wait_busy(port1
,debug
="pi_st_A") # wait while busy
50 # set up a ST on the port. address first:
51 yield port1
.is_dcbz_i
.eq(is_dcbz
) # reset dcbz too
52 yield port1
.is_st_i
.eq(1) # indicate ST
53 yield port1
.data_len
.eq(datalen
) # ST length (1/2/4/8)
54 yield port1
.msr_pr
.eq(msr_pr
) # MSR PR bit (1==>virt, 0==>real)
56 yield port1
.addr
.data
.eq(addr
) # set address
57 yield port1
.addr
.ok
.eq(1) # set ok
59 yield from wait_addr(port1
) # wait until addr ok
60 yield from wait_addr(port1
) # wait until addr ok
62 # yield # not needed, just for checking
63 # yield # not needed, just for checking
64 # assert "ST" for one cycle (required by the API)
65 yield port1
.st
.data
.eq(data
)
66 yield port1
.st
.ok
.eq(1)
68 yield port1
.st
.ok
.eq(0)
69 exc_happened
= yield port1
.exc_o
.happened
71 print("print fast exception happened")
72 yield port1
.is_st_i
.eq(0) # end
73 yield port1
.addr
.ok
.eq(0) # set !ok
74 yield port1
.is_dcbz_i
.eq(0) # reset dcbz too
76 yield from wait_busy(port1
,debug
="pi_st_E") # wait while busy
78 # can go straight to reset.
79 yield port1
.is_st_i
.eq(0) # end
80 yield port1
.addr
.ok
.eq(0) # set !ok
81 yield port1
.is_dcbz_i
.eq(0) # reset dcbz too
86 # copy of pi_st removed
88 def pi_ld(port1
, addr
, datalen
, msr_pr
=0):
90 # have to wait until not busy
91 yield from wait_busy(port1
,debug
="pi_ld_A") # wait while busy
93 # set up a LD on the port. address first:
94 yield port1
.is_ld_i
.eq(1) # indicate LD
95 yield port1
.data_len
.eq(datalen
) # LD length (1/2/4/8)
96 yield port1
.msr_pr
.eq(msr_pr
) # MSR PR bit (1==>virt, 0==>real)
98 yield port1
.addr
.data
.eq(addr
) # set address
99 yield port1
.addr
.ok
.eq(1) # set ok
101 yield from wait_addr(port1
) # wait until addr ok
102 exc_happened
= yield port1
.exc_o
.happened
104 print("print fast exception happened")
105 yield port1
.is_ld_i
.eq(0) # end
106 yield port1
.addr
.ok
.eq(0) # set !ok
110 yield from wait_ldok(port1
) # wait until ld ok
111 data
= yield port1
.ld
.data
112 exc_happened
= yield port1
.exc_o
.happened
115 yield port1
.is_ld_i
.eq(0) # end
116 yield port1
.addr
.ok
.eq(0) # set !ok
120 yield from wait_busy(port1
,debug
="pi_ld_E") # wait while busy
122 exc_happened
= yield port1
.exc_o
.happened
129 def pi_ldst(arg
, dut
, msr_pr
=0):
131 # do two half-word stores at consecutive addresses, then two loads
137 assert(yield from pi_st(dut
, addr1
, data
, 2, msr_pr
) is None)
138 assert(yield from pi_st(dut
, addr2
, data2
, 2, msr_pr
) is None)
139 result
, exc
= yield from pi_ld(dut
, addr1
, 2, msr_pr
)
140 result2
, exc2
= yield from pi_ld(dut
, addr2
, 2, msr_pr
)
143 arg
.assertEqual(data
, result
, "data %x != %x" % (result
, data
))
144 arg
.assertEqual(data2
, result2
, "data2 %x != %x" % (result2
, data2
))
146 # now load both in a 32-bit load to make sure they're really consecutive
147 data3
= data |
(data2
<< 16)
148 result3
, exc3
= yield from pi_ld(dut
, addr1
, 4, msr_pr
)
150 arg
.assertEqual(data3
, result3
, "data3 %x != %x" % (result3
, data3
))
153 def tst_config_pi(testcls
, ifacetype
):
154 """set up a configureable memory test of type ifacetype
157 pspec
= TestMemPspec(ldst_ifacetype
=ifacetype
,
162 cmpi
= ConfigMemoryPortInterface(pspec
)
163 dut
.submodules
.pi
= cmpi
.pi
164 if hasattr(cmpi
, 'lsmem'): # hmmm not happy about this
165 dut
.submodules
.lsmem
= cmpi
.lsmem
.lsi
166 vl
= rtlil
.convert(dut
, ports
=[]) # dut.ports())
167 with
open("test_pi_%s.il" % ifacetype
, "w") as f
:
170 run_simulation(dut
, {"sync": pi_ldst(testcls
, cmpi
.pi
.pi
)},
171 vcd_name
='test_pi_%s.vcd' % ifacetype
)
174 class TestPIMem(unittest
.TestCase
):
176 def test_pi_mem(self
):
177 tst_config_pi(self
, 'testpi')
179 def test_pi2ls(self
):
180 tst_config_pi(self
, 'testmem')
182 def test_pi2ls_bare_wb(self
):
183 tst_config_pi(self
, 'test_bare_wb')
186 if __name__
== '__main__':