1 from nmigen
import Signal
, Module
, Record
2 from nmigen
.back
.pysim
import Simulator
, Delay
3 from nmigen
.compat
.sim
import run_simulation
, Settle
4 from nmutil
.formaltest
import FHDLTestCase
5 from nmigen
.cli
import rtlil
7 from soc
.config
.test
.test_loadstore
import TestMemPspec
8 from soc
.config
.loadstore
import ConfigMemoryPortInterface
9 from openpower
.exceptions
import LDSTExceptionTuple
12 def wait_busy(port
, no
=False, debug
=None):
15 busy
= yield port
.busy_o
16 print("busy", no
, busy
, cnt
, debug
)
23 def wait_addr(port
,debug
=None):
26 addr_ok
= yield port
.addr_ok_o
27 exc_happened
= yield port
.exc_o
.happened
28 print("addrok", addr_ok
,cnt
,debug
,exc_happened
)
29 if addr_ok
or exc_happened
:
38 ldok
= yield port
.ld
.ok
39 exc_happened
= yield port
.exc_o
.happened
40 print("ldok", ldok
, "exception", exc_happened
, "count", cnt
)
42 if ldok
or exc_happened
:
47 def pi_st(port1
, addr
, data
, datalen
, msr_pr
=0, is_dcbz
=0):
49 # have to wait until not busy
50 yield from wait_busy(port1
,debug
="pi_st_A") # wait while busy
52 # set up a ST on the port. address first:
53 yield port1
.is_dcbz_i
.eq(is_dcbz
) # reset dcbz too
54 yield port1
.is_st_i
.eq(1) # indicate ST
55 yield port1
.data_len
.eq(datalen
) # ST length (1/2/4/8)
56 yield port1
.msr_pr
.eq(msr_pr
) # MSR PR bit (1==>virt, 0==>real)
58 yield port1
.addr
.data
.eq(addr
) # set address
59 yield port1
.addr
.ok
.eq(1) # set ok
62 # must check exception even before waiting for address.
63 # XXX TODO: wait_addr should check for exception
64 exc_info
= yield from get_exception_info(port1
.exc_o
)
65 exc_happened
= exc_info
.happened
67 print("print fast ST exception happened")
68 yield # MUST wait for one clock cycle before de-asserting these
69 yield port1
.is_st_i
.eq(0) # end
70 yield port1
.addr
.ok
.eq(0) # set !ok
71 yield port1
.is_dcbz_i
.eq(0) # reset dcbz too
72 return "fast", exc_info
74 yield from wait_addr(port1
) # wait until addr ok
76 exc_info
= yield from get_exception_info(port1
.exc_o
)
77 exc_happened
= exc_info
.happened
79 print("print fast ST exception happened")
80 yield # MUST wait for one clock cycle before de-asserting these
81 yield port1
.is_st_i
.eq(0) # end
82 yield port1
.addr
.ok
.eq(0) # set !ok
83 yield port1
.is_dcbz_i
.eq(0) # reset dcbz too
84 return "fast", exc_info
87 # yield # not needed, just for checking
88 # yield # not needed, just for checking
89 # assert "ST" for one cycle (required by the API)
90 yield port1
.st
.data
.eq(data
)
91 yield port1
.st
.ok
.eq(1)
93 yield port1
.st
.ok
.eq(0)
94 exc_info
= yield from get_exception_info(port1
.exc_o
)
95 exc_happened
= exc_info
.happened
97 print("print fast ST exception happened")
98 yield # MUST wait for one clock cycle before de-asserting these
99 yield port1
.is_st_i
.eq(0) # end
100 yield port1
.addr
.ok
.eq(0) # set !ok
101 yield port1
.is_dcbz_i
.eq(0) # reset dcbz too
102 return "fast", exc_info
104 yield from wait_busy(port1
,debug
="pi_st_E") # wait while busy
105 exc_info
= yield from get_exception_info(port1
.exc_o
)
106 exc_happened
= exc_info
.happened
108 yield # needed if mmu/dache is used
109 yield port1
.is_st_i
.eq(0) # end
110 yield port1
.addr
.ok
.eq(0) # set !ok
111 yield port1
.is_dcbz_i
.eq(0) # reset dcbz too
112 yield # needed if mmu/dache is used
113 return "slow", exc_info
115 # can go straight to reset.
116 yield port1
.is_st_i
.eq(0) # end
117 yield port1
.addr
.ok
.eq(0) # set !ok
118 yield port1
.is_dcbz_i
.eq(0) # reset dcbz too
119 yield # needed if mmu/dache is used
123 def get_exception_info(exc_o
):
125 for fname
in LDSTExceptionTuple
._fields
:
126 attr
= getattr(exc_o
, fname
)
129 return LDSTExceptionTuple(*attrs
)
132 # copy of pi_st removed
134 def pi_ld(port1
, addr
, datalen
, msr_pr
=0):
136 # have to wait until not busy
137 yield from wait_busy(port1
,debug
="pi_ld_A") # wait while busy
139 # set up a LD on the port. address first:
140 yield port1
.is_ld_i
.eq(1) # indicate LD
141 yield port1
.data_len
.eq(datalen
) # LD length (1/2/4/8)
142 yield port1
.msr_pr
.eq(msr_pr
) # MSR PR bit (1==>virt, 0==>real)
144 yield port1
.addr
.data
.eq(addr
) # set address
145 yield port1
.addr
.ok
.eq(1) # set ok
147 yield from wait_addr(port1
) # wait until addr ok
148 exc_info
= yield from get_exception_info(port1
.exc_o
)
149 exc_happened
= exc_info
.happened
151 print("print fast LD exception happened")
152 yield # MUST wait for one clock cycle before de-asserting these
153 yield port1
.is_ld_i
.eq(0) # end
154 yield port1
.addr
.ok
.eq(0) # set !ok
155 return None, "fast", exc_info
158 yield from wait_ldok(port1
) # wait until ld ok
159 data
= yield port1
.ld
.data
160 exc_info
= yield from get_exception_info(port1
.exc_o
)
161 exc_happened
= yield port1
.exc_o
.happened
162 exc_happened
= exc_info
.happened
165 yield port1
.is_ld_i
.eq(0) # end
166 yield port1
.addr
.ok
.eq(0) # set !ok
168 return None, "slow", exc_info
170 yield from wait_busy(port1
, debug
="pi_ld_E") # wait while busy
172 exc_info
= yield from get_exception_info(port1
.exc_o
)
173 exc_happened
= exc_info
.happened
175 return None, "slow", exc_info
177 return data
, None, None
180 def pi_ldst(arg
, dut
, msr_pr
=0):
182 # do two half-word stores at consecutive addresses, then two loads
188 assert(yield from pi_st(dut
, addr1
, data
, 2, msr_pr
) is None)
189 assert(yield from pi_st(dut
, addr2
, data2
, 2, msr_pr
) is None)
190 result
, exc
= yield from pi_ld(dut
, addr1
, 2, msr_pr
)
191 result2
, exc2
= yield from pi_ld(dut
, addr2
, 2, msr_pr
)
194 arg
.assertEqual(data
, result
, "data %x != %x" % (result
, data
))
195 arg
.assertEqual(data2
, result2
, "data2 %x != %x" % (result2
, data2
))
197 # now load both in a 32-bit load to make sure they're really consecutive
198 data3
= data |
(data2
<< 16)
199 result3
, exc3
= yield from pi_ld(dut
, addr1
, 4, msr_pr
)
201 arg
.assertEqual(data3
, result3
, "data3 %x != %x" % (result3
, data3
))
204 def tst_config_pi(testcls
, ifacetype
):
205 """set up a configureable memory test of type ifacetype
208 pspec
= TestMemPspec(ldst_ifacetype
=ifacetype
,
213 cmpi
= ConfigMemoryPortInterface(pspec
)
214 dut
.submodules
.pi
= cmpi
.pi
215 if hasattr(cmpi
, 'lsmem'): # hmmm not happy about this
216 dut
.submodules
.lsmem
= cmpi
.lsmem
.lsi
217 vl
= rtlil
.convert(dut
, ports
=[]) # dut.ports())
218 with
open("test_pi_%s.il" % ifacetype
, "w") as f
:
221 run_simulation(dut
, {"sync": pi_ldst(testcls
, cmpi
.pi
.pi
)},
222 vcd_name
='test_pi_%s.vcd' % ifacetype
)
225 class TestPIMem(unittest
.TestCase
):
227 def test_pi_mem(self
):
228 tst_config_pi(self
, 'testpi')
230 def test_pi2ls(self
):
231 tst_config_pi(self
, 'testmem')
233 def test_pi2ls_bare_wb(self
):
234 tst_config_pi(self
, 'test_bare_wb')
237 if __name__
== '__main__':