src/soc/debug/dmi.py

   1 """Converted from microwatt core_debug.vhdl to nmigen
   2
   3 Provides a DMI (Debug Module Interface) for accessing a Libre-SOC core,
   4 compatible with microwatt's same interface.
   5
   6 See constants below for addresses and register formats
   7 """
   8
   9 from nmigen import Elaboratable, Module, Signal, Cat, Const, Record, Array, Mux
  10 from nmutil.iocontrol import RecordObject
  11 from nmigen.utils import log2_int
  12 from nmigen.cli import rtlil
  13
  14
  15 # DMI register addresses
  16 class DBGCore:
  17     CTRL           = 0b0000
  18     STAT           = 0b0001
  19     NIA            = 0b0010 # NIA register (read only for now)
  20     MSR            = 0b0011 # MSR (read only)
  21     GSPR_INDEX     = 0b0100 # GSPR register index
  22     GSPR_DATA      = 0b0101 # GSPR register data
  23     LOG_ADDR       = 0b0110 # Log buffer address register
  24     LOG_DATA       = 0b0111 # Log buffer data register
  25
  26
  27 # CTRL register (direct actions, write 1 to act, read back 0)
  28 # bit     0 : Core stop
  29 # bit     1 : Core reset (doesn't clear stop)
  30 # bit     2 : Icache reset
  31 # bit     3 : Single step
  32 # bit     4 : Core start
  33 class DBGCtrl:
  34     STOP    = 0
  35     RESET   = 1
  36     ICRESET = 2
  37     STEP    = 3
  38     START   = 4
  39
  40
  41 # STAT register (read only)
  42 # bit    0 : Core stopping (wait til bit 1 set)
  43 # bit    1 : Core stopped
  44 # bit    2 : Core terminated (clears with start or reset)
  45 class DBGStat:
  46     STOPPING  = 0
  47     STOPPED   = 1
  48     TERM      = 2
  49
  50
  51 class DMIInterface(RecordObject):
  52     def __init__(self, name):
  53         super().__init__(name=name)
  54         self.addr_i = Signal(4)   # DMI register address
  55         self.din    = Signal(64)  # DMI data in (if we=1)
  56         self.dout   = Signal(64)  # DMI data out (if we=0)
  57         self.req_i  = Signal()    # DMI request valid (stb)
  58         self.we_i   = Signal()    # DMI write-enable
  59         self.ack_o  = Signal()    # DMI ack request
  60
  61
  62 class DbgReg(RecordObject):
  63     def __init__(self, name):
  64         super().__init__(name=name)
  65         self.req_o     = Signal()
  66         self.ack_i     = Signal()
  67         self.addr_o    = Signal(7) #  includes fast SPRs, others?
  68         self.data_i    = Signal(64)
  69
  70
  71 class CoreDebug(Elaboratable):
  72     def __init__(self, LOG_LENGTH=0): # TODO - debug log 512):
  73         # Length of log buffer
  74         self.LOG_LENGTH = LOG_LENGTH
  75         self.dmi = DMIInterface("dmi")
  76
  77         # Debug actions
  78         self.core_stop_o       = Signal()
  79         self.core_rst_o        = Signal()
  80         self.icache_rst_o      = Signal()
  81
  82         # Core status inputs
  83         self.terminate_i    = Signal()
  84         self.core_stopped_i = Signal()
  85         self.nia            = Signal(64)
  86         self.msr            = Signal(64)
  87
  88         # GSPR register read port
  89         self.dbg_gpr = DbgReg("dbg_gpr")
  90
  91         # Core logging data
  92         self.log_data_i        = Signal(256)
  93         self.log_read_addr_i   = Signal(32)
  94         self.log_read_data_o   = Signal(64)
  95         self.log_write_addr_o  = Signal(32)
  96
  97         # Misc
  98         self.terminated_o  = Signal()
  99
 100     def elaborate(self, platform):
 101
 102         m = Module()
 103         comb, sync = m.d.comb, m.d.sync
 104
 105         # DMI needs fixing... make a one clock pulse
 106         dmi_req_i_1 = Signal()
 107
 108         # Some internal wires
 109         stat_reg = Signal(64)
 110
 111         # Some internal latches
 112         stopping     = Signal()
 113         do_step      = Signal()
 114         do_reset     = Signal()
 115         do_icreset   = Signal()
 116         terminated   = Signal()
 117         do_gspr_rd   = Signal()
 118         gspr_index   = Signal.like(self.dbg_gpr.addr_o)
 119
 120         log_dmi_addr = Signal(32)
 121         log_dmi_data = Signal(64)
 122         do_dmi_log_rd = Signal()
 123         dmi_read_log_data = Signal()
 124         dmi_read_log_data_1 = Signal()
 125
 126         LOG_INDEX_BITS = log2_int(self.LOG_LENGTH)
 127
 128         # Single cycle register accesses on DMI except for GSPR data
 129         comb += self.dmi.ack_o.eq(Mux(self.dmi.addr_i == DBGCore.GSPR_DATA,
 130                                       self.dbg_gpr.ack_i, self.dmi.req_i))
 131         comb += self.dbg_gpr.req_o.eq(Mux(self.dmi.addr_i == DBGCore.GSPR_DATA,
 132                                       self.dmi.req_i, 0))
 133
 134         # Status register read composition (DBUG_CORE_STAT_xxx)
 135         comb += stat_reg.eq(Cat(stopping,            # bit 0
 136                                 self.core_stopped_i, # bit 1
 137                                 terminated))         # bit 2
 138
 139         # DMI read data mux
 140         with m.Switch(self.dmi.addr_i):
 141             with m.Case( DBGCore.STAT):
 142                 comb += self.dmi.dout.eq(stat_reg)
 143             with m.Case( DBGCore.NIA):
 144                 comb += self.dmi.dout.eq(self.nia)
 145             with m.Case( DBGCore.MSR):
 146                 comb += self.dmi.dout.eq(self.msr)
 147             with m.Case( DBGCore.GSPR_DATA):
 148                 comb += self.dmi.dout.eq(self.dbg_gpr.data_i)
 149             with m.Case( DBGCore.LOG_ADDR):
 150                 comb += self.dmi.dout.eq(Cat(log_dmi_addr,
 151                                              self.log_write_addr_o))
 152             with m.Case( DBGCore.LOG_DATA):
 153                 comb += self.dmi.dout.eq(log_dmi_data)
 154
 155         # DMI writes
 156         # Reset the 1-cycle "do" signals
 157         sync += do_step.eq(0)
 158         sync += do_reset.eq(0)
 159         sync += do_icreset.eq(0)
 160         sync += do_dmi_log_rd.eq(0)
 161
 162         # Edge detect on dmi_req_i for 1-shot pulses
 163         sync += dmi_req_i_1.eq(self.dmi.req_i)
 164         with m.If(self.dmi.req_i & ~dmi_req_i_1):
 165             with m.If(self.dmi.we_i):
 166                 #sync += Display("DMI write to " & to_hstring(dmi_addr))
 167
 168                 # Control register actions
 169
 170                 # Core control
 171                 with m.If(self.dmi.addr_i == DBGCore.CTRL):
 172                     with m.If(self.dmi.din[DBGCtrl.RESET]):
 173                         sync += do_reset.eq(1)
 174                         sync += terminated.eq(0)
 175                     with m.If(self.dmi.din[DBGCtrl.STOP]):
 176                         sync += stopping.eq(1)
 177                     with m.If(self.dmi.din[DBGCtrl.STEP]):
 178                         sync += do_step.eq(1)
 179                         sync += terminated.eq(0)
 180                     with m.If(self.dmi.din[DBGCtrl.ICRESET]):
 181                         sync += do_icreset.eq(1)
 182                     with m.If(self.dmi.din[DBGCtrl.START]):
 183                         sync += stopping.eq(0)
 184                         sync += terminated.eq(0)
 185
 186                 # GSPR address
 187                 with m.Elif(self.dmi.addr_i == DBGCore.GSPR_INDEX):
 188                     sync += gspr_index.eq(self.dmi.din)
 189
 190                 # Log address
 191                 with m.Elif(self.dmi.addr_i == DBGCore.LOG_ADDR):
 192                     sync += log_dmi_addr.eq(self.dmi.din)
 193                     sync += do_dmi_log_rd.eq(1)
 194             with m.Else():
 195                 # sync += Display("DMI read from " & to_string(dmi_addr))
 196                 pass
 197
 198         with m.Elif(dmi_read_log_data_1 & ~dmi_read_log_data):
 199             # Increment log_dmi_addr after end of read from DBGCore.LOG_DATA
 200             lds = log_dmi_addr[:LOG_INDEX_BITS+2]
 201             sync += lds.eq(lds + 1)
 202             sync += do_dmi_log_rd.eq(1)
 203
 204         sync += dmi_read_log_data_1.eq(dmi_read_log_data)
 205         sync += dmi_read_log_data.eq(self.dmi.req_i &
 206                                      (self.dmi.addr_i == DBGCore.LOG_DATA))
 207
 208         # Set core stop on terminate. We'll be stopping some time *after*
 209         # the offending instruction, at least until we can do back flushes
 210         # that preserve NIA which we can't just yet.
 211         with m.If(self.terminate_i):
 212             sync += stopping.eq(1)
 213             sync += terminated.eq(1)
 214
 215         comb += self.dbg_gpr.addr_o.eq(gspr_index)
 216
 217         # Core control signals generated by the debug module
 218         comb += self.core_stop_o.eq(stopping & ~do_step)
 219         comb += self.core_rst_o.eq(do_reset)
 220         comb += self.icache_rst_o.eq(do_icreset)
 221         comb += self.terminated_o.eq(terminated)
 222
 223         # Logging RAM (none)
 224
 225         if self.LOG_LENGTH == 0:
 226             self.log_read_data_o.eq(0)
 227             self.log_write_addr_o.eq(0x00000001)
 228
 229         return m
 230
 231         # TODO: debug logging
 232         """
 233         maybe_log: with m.If(LOG_LENGTH > 0 generate
 234             subtype log_ptr_t is unsigned(LOG_INDEX_BITS - 1 downto 0)
 235             type log_array_t is array(0 to LOG_LENGTH - 1) of std_ulogic_vector(255 downto 0)
 236             signal log_array    : log_array_t
 237             signal log_rd_ptr   : log_ptr_t
 238             signal log_wr_ptr   : log_ptr_t
 239             signal log_toggle   = Signal()
 240             signal log_wr_enable = Signal()
 241             signal log_rd_ptr_latched : log_ptr_t
 242             signal log_rd       = Signal()_vector(255 downto 0)
 243             signal log_dmi_reading = Signal()
 244             signal log_dmi_read_done = Signal()
 245
 246             function select_dword(data = Signal()_vector(255 downto 0)
 247                                   addr = Signal()_vector(31 downto 0)) return std_ulogic_vector is
 248                 variable firstbit : integer
 249             begin
 250                 firstbit := to_integer(unsigned(addr(1 downto 0))) * 64
 251                 return data(firstbit + 63 downto firstbit)
 252             end
 253
 254             attribute ram_style : string
 255             attribute ram_style of log_array : signal is "block"
 256             attribute ram_decomp : string
 257             attribute ram_decomp of log_array : signal is "power"
 258
 259         begin
 260             # Use MSB of read addresses to stop the logging
 261             log_wr_enable.eq(not (self.log_read_addr(31) or log_dmi_addr(31))
 262
 263             log_ram: process(clk)
 264             begin
 265                 with m.If(rising_edge(clk)):
 266                     with m.If(log_wr_enable = '1'):
 267                         log_array(to_integer(log_wr_ptr)).eq(self.log_data
 268                     end if
 269                     log_rd.eq(log_array(to_integer(log_rd_ptr_latched))
 270                 end if
 271             end process
 272
 273
 274             log_buffer: process(clk)
 275                 variable b : integer
 276                 variable data = Signal()_vector(255 downto 0)
 277             begin
 278                 with m.If(rising_edge(clk)):
 279                     with m.If(rst = '1'):
 280                         log_wr_ptr.eq((others => '0')
 281                         log_toggle.eq('0'
 282                     with m.Elif(log_wr_enable = '1'):
 283                         with m.If(log_wr_ptr = to_unsigned(LOG_LENGTH - 1, LOG_INDEX_BITS)):
 284                             log_toggle.eq(not log_toggle
 285                         end if
 286                         log_wr_ptr.eq(log_wr_ptr + 1
 287                     end if
 288                     with m.If(do_dmi_log_rd = '1'):
 289                         log_rd_ptr_latched.eq(unsigned(log_dmi_addr(LOG_INDEX_BITS + 1 downto 2))
 290                     else
 291                         log_rd_ptr_latched.eq(unsigned(self.log_read_addr(LOG_INDEX_BITS + 1 downto 2))
 292                     end if
 293                     with m.If(log_dmi_read_done = '1'):
 294                         log_dmi_data.eq(select_dword(log_rd, log_dmi_addr)
 295                     else
 296                         self.log_read_data.eq(select_dword(log_rd, self.log_read_addr)
 297                     end if
 298                     log_dmi_read_done.eq(log_dmi_reading
 299                     log_dmi_reading.eq(do_dmi_log_rd
 300                 end if
 301             end process
 302             self.log_write_addr(LOG_INDEX_BITS - 1 downto 0).eq(std_ulogic_vector(log_wr_ptr)
 303             self.log_write_addr(LOG_INDEX_BITS).eq('1'
 304             self.log_write_addr(31 downto LOG_INDEX_BITS + 1).eq((others => '0')
 305         end generate
 306
 307         """
 308
 309     def __iter__(self):
 310         yield from self.dmi
 311         yield self.core_stop_o
 312         yield self.core_rst_o
 313         yield self.icache_rst_o
 314         yield self.terminate_i
 315         yield self.core_stopped_i
 316         yield self.nia
 317         yield self.msr
 318         yield from self.dbg_gpr
 319         yield self.log_data_i
 320         yield self.log_read_addr_i
 321         yield self.log_read_data_o
 322         yield self.log_write_addr_o
 323         yield self.terminated_o
 324
 325     def ports(self):
 326         return list(self)
 327
 328
 329 def test_debug():
 330
 331     dut = CoreDebug()
 332     vl = rtlil.convert(dut, ports=dut.ports())
 333     with open("test_core_debug.il", "w") as f:
 334         f.write(vl)
 335
 336 if __name__ == '__main__':
 337     test_debug()
 338