1 """Converted from microwatt core_debug.vhdl to nmigen
3 Provides a DMI (Debug Module Interface) for accessing a Libre-SOC core,
4 compatible with microwatt's same interface.
6 See constants below for addresses and register formats
9 from nmigen
import Elaboratable
, Module
, Signal
, Cat
, Const
, Record
, Array
, Mux
10 from nmutil
.iocontrol
import RecordObject
11 from nmigen
.utils
import log2_int
12 from nmigen
.cli
import rtlil
13 from soc
.config
.state
import CoreState
16 # DMI register addresses
20 NIA
= 0b0010 # NIA register (read only for now)
21 MSR
= 0b0011 # MSR (read only)
22 GSPR_IDX
= 0b0100 # GSPR register index
23 GSPR_DATA
= 0b0101 # GSPR register data
24 LOG_ADDR
= 0b0110 # Log buffer address register
25 LOG_DATA
= 0b0111 # Log buffer data register
28 # CTRL register (direct actions, write 1 to act, read back 0)
30 # bit 1 : Core reset (doesn't clear stop)
31 # bit 2 : Icache reset
42 # STAT register (read only)
43 # bit 0 : Core stopping (wait til bit 1 set)
44 # bit 1 : Core stopped
45 # bit 2 : Core terminated (clears with start or reset)
52 class DMIInterface(RecordObject
):
53 def __init__(self
, name
):
54 super().__init
__(name
=name
)
55 self
.addr_i
= Signal(4) # DMI register address
56 self
.din
= Signal(64) # DMI data in (if we=1)
57 self
.dout
= Signal(64) # DMI data out (if we=0)
58 self
.req_i
= Signal() # DMI request valid (stb)
59 self
.we_i
= Signal() # DMI write-enable
60 self
.ack_o
= Signal() # DMI ack request
63 class DbgReg(RecordObject
):
64 def __init__(self
, name
):
65 super().__init
__(name
=name
)
68 self
.addr
= Signal(7) # includes fast SPRs, others?
69 self
.data
= Signal(64)
72 class CoreDebug(Elaboratable
):
73 def __init__(self
, LOG_LENGTH
=0): # TODO - debug log 512):
74 # Length of log buffer
75 self
.LOG_LENGTH
= LOG_LENGTH
76 self
.dmi
= DMIInterface("dmi")
79 self
.core_stop_o
= Signal()
80 self
.core_rst_o
= Signal()
81 self
.icache_rst_o
= Signal()
84 self
.terminate_i
= Signal()
85 self
.core_stopped_i
= Signal()
86 self
.state
= CoreState("core_dbg")
88 # GSPR register read port
89 self
.dbg_gpr
= DbgReg("dbg_gpr")
92 self
.log_data_i
= Signal(256)
93 self
.log_read_addr_i
= Signal(32)
94 self
.log_read_data_o
= Signal(64)
95 self
.log_write_addr_o
= Signal(32)
98 self
.terminated_o
= Signal()
100 def elaborate(self
, platform
):
103 comb
, sync
= m
.d
.comb
, m
.d
.sync
105 # DMI needs fixing... make a one clock pulse
106 dmi_req_i_1
= Signal()
108 # Some internal wires
109 stat_reg
= Signal(64)
111 # Some internal latches
115 do_icreset
= Signal()
116 terminated
= Signal()
117 do_gspr_rd
= Signal()
118 gspr_index
= Signal
.like(self
.dbg_gpr
.addr
)
120 log_dmi_addr
= Signal(32)
121 log_dmi_data
= Signal(64)
122 do_dmi_log_rd
= Signal()
123 dmi_read_log_data
= Signal()
124 dmi_read_log_data_1
= Signal()
126 LOG_INDEX_BITS
= log2_int(self
.LOG_LENGTH
)
128 # Single cycle register accesses on DMI except for GSPR data
129 comb
+= self
.dmi
.ack_o
.eq(Mux(self
.dmi
.addr_i
== DBGCore
.GSPR_DATA
,
130 self
.dbg_gpr
.ack
, self
.dmi
.req_i
))
131 comb
+= self
.dbg_gpr
.req
.eq(Mux(self
.dmi
.addr_i
== DBGCore
.GSPR_DATA
,
134 # Status register read composition (DBUG_CORE_STAT_xxx)
135 comb
+= stat_reg
.eq(Cat(stopping
, # bit 0
136 self
.core_stopped_i
, # bit 1
140 with m
.Switch(self
.dmi
.addr_i
):
141 with m
.Case( DBGCore
.STAT
):
142 comb
+= self
.dmi
.dout
.eq(stat_reg
)
143 with m
.Case( DBGCore
.NIA
):
144 comb
+= self
.dmi
.dout
.eq(self
.state
.pc
)
145 with m
.Case( DBGCore
.MSR
):
146 comb
+= self
.dmi
.dout
.eq(self
.state
.msr
)
147 with m
.Case( DBGCore
.GSPR_DATA
):
148 comb
+= self
.dmi
.dout
.eq(self
.dbg_gpr
.data
)
149 with m
.Case( DBGCore
.LOG_ADDR
):
150 comb
+= self
.dmi
.dout
.eq(Cat(log_dmi_addr
,
151 self
.log_write_addr_o
))
152 with m
.Case( DBGCore
.LOG_DATA
):
153 comb
+= self
.dmi
.dout
.eq(log_dmi_data
)
156 # Reset the 1-cycle "do" signals
157 sync
+= do_step
.eq(0)
158 sync
+= do_reset
.eq(0)
159 sync
+= do_icreset
.eq(0)
160 sync
+= do_dmi_log_rd
.eq(0)
162 # Edge detect on dmi_req_i for 1-shot pulses
163 sync
+= dmi_req_i_1
.eq(self
.dmi
.req_i
)
164 with m
.If(self
.dmi
.req_i
& ~dmi_req_i_1
):
165 with m
.If(self
.dmi
.we_i
):
166 #sync += Display("DMI write to " & to_hstring(dmi_addr))
168 # Control register actions
171 with m
.If(self
.dmi
.addr_i
== DBGCore
.CTRL
):
172 with m
.If(self
.dmi
.din
[DBGCtrl
.RESET
]):
173 sync
+= do_reset
.eq(1)
174 sync
+= terminated
.eq(0)
175 with m
.If(self
.dmi
.din
[DBGCtrl
.STOP
]):
176 sync
+= stopping
.eq(1)
177 with m
.If(self
.dmi
.din
[DBGCtrl
.STEP
]):
178 sync
+= do_step
.eq(1)
179 sync
+= terminated
.eq(0)
180 with m
.If(self
.dmi
.din
[DBGCtrl
.ICRESET
]):
181 sync
+= do_icreset
.eq(1)
182 with m
.If(self
.dmi
.din
[DBGCtrl
.START
]):
183 sync
+= stopping
.eq(0)
184 sync
+= terminated
.eq(0)
187 with m
.Elif(self
.dmi
.addr_i
== DBGCore
.GSPR_IDX
):
188 sync
+= gspr_index
.eq(self
.dmi
.din
)
191 with m
.Elif(self
.dmi
.addr_i
== DBGCore
.LOG_ADDR
):
192 sync
+= log_dmi_addr
.eq(self
.dmi
.din
)
193 sync
+= do_dmi_log_rd
.eq(1)
195 # sync += Display("DMI read from " & to_string(dmi_addr))
198 with m
.Elif(dmi_read_log_data_1
& ~dmi_read_log_data
):
199 # Increment log_dmi_addr after end of read from DBGCore.LOG_DATA
200 lds
= log_dmi_addr
[:LOG_INDEX_BITS
+2]
201 sync
+= lds
.eq(lds
+ 1)
202 sync
+= do_dmi_log_rd
.eq(1)
204 sync
+= dmi_read_log_data_1
.eq(dmi_read_log_data
)
205 sync
+= dmi_read_log_data
.eq(self
.dmi
.req_i
&
206 (self
.dmi
.addr_i
== DBGCore
.LOG_DATA
))
208 # Set core stop on terminate. We'll be stopping some time *after*
209 # the offending instruction, at least until we can do back flushes
210 # that preserve NIA which we can't just yet.
211 with m
.If(self
.terminate_i
):
212 sync
+= stopping
.eq(1)
213 sync
+= terminated
.eq(1)
215 comb
+= self
.dbg_gpr
.addr
.eq(gspr_index
)
217 # Core control signals generated by the debug module
218 comb
+= self
.core_stop_o
.eq(stopping
& ~do_step
)
219 comb
+= self
.core_rst_o
.eq(do_reset
)
220 comb
+= self
.icache_rst_o
.eq(do_icreset
)
221 comb
+= self
.terminated_o
.eq(terminated
)
225 if self
.LOG_LENGTH
== 0:
226 self
.log_read_data_o
.eq(0)
227 self
.log_write_addr_o
.eq(0x00000001)
231 # TODO: debug logging
233 maybe_log: with m.If(LOG_LENGTH > 0 generate
234 subtype log_ptr_t is unsigned(LOG_INDEX_BITS - 1 downto 0)
235 type log_array_t is array(0 to LOG_LENGTH - 1) of std_ulogic_vector(255 downto 0)
236 signal log_array : log_array_t
237 signal log_rd_ptr : log_ptr_t
238 signal log_wr_ptr : log_ptr_t
239 signal log_toggle = Signal()
240 signal log_wr_enable = Signal()
241 signal log_rd_ptr_latched : log_ptr_t
242 signal log_rd = Signal()_vector(255 downto 0)
243 signal log_dmi_reading = Signal()
244 signal log_dmi_read_done = Signal()
246 function select_dword(data = Signal()_vector(255 downto 0)
247 addr = Signal()_vector(31 downto 0)) return std_ulogic_vector is
248 variable firstbit : integer
250 firstbit := to_integer(unsigned(addr(1 downto 0))) * 64
251 return data(firstbit + 63 downto firstbit)
254 attribute ram_style : string
255 attribute ram_style of log_array : signal is "block"
256 attribute ram_decomp : string
257 attribute ram_decomp of log_array : signal is "power"
260 # Use MSB of read addresses to stop the logging
261 log_wr_enable.eq(not (self.log_read_addr(31) or log_dmi_addr(31))
263 log_ram: process(clk)
265 with m.If(rising_edge(clk)):
266 with m.If(log_wr_enable = '1'):
267 log_array(to_integer(log_wr_ptr)).eq(self.log_data
269 log_rd.eq(log_array(to_integer(log_rd_ptr_latched))
274 log_buffer: process(clk)
276 variable data = Signal()_vector(255 downto 0)
278 with m.If(rising_edge(clk)):
279 with m.If(rst = '1'):
280 log_wr_ptr.eq((others => '0')
282 with m.Elif(log_wr_enable = '1'):
283 with m.If(log_wr_ptr = to_unsigned(LOG_LENGTH - 1, LOG_INDEX_BITS)):
284 log_toggle.eq(not log_toggle
286 log_wr_ptr.eq(log_wr_ptr + 1
288 with m.If(do_dmi_log_rd = '1'):
289 log_rd_ptr_latched.eq(unsigned(log_dmi_addr(LOG_INDEX_BITS + 1 downto 2))
291 log_rd_ptr_latched.eq(unsigned(self.log_read_addr(LOG_INDEX_BITS + 1 downto 2))
293 with m.If(log_dmi_read_done = '1'):
294 log_dmi_data.eq(select_dword(log_rd, log_dmi_addr)
296 self.log_read_data.eq(select_dword(log_rd, self.log_read_addr)
298 log_dmi_read_done.eq(log_dmi_reading
299 log_dmi_reading.eq(do_dmi_log_rd
302 self.log_write_addr(LOG_INDEX_BITS - 1 downto 0).eq(std_ulogic_vector(log_wr_ptr)
303 self.log_write_addr(LOG_INDEX_BITS).eq('1'
304 self.log_write_addr(31 downto LOG_INDEX_BITS + 1).eq((others => '0')
311 yield self
.core_stop_o
312 yield self
.core_rst_o
313 yield self
.icache_rst_o
314 yield self
.terminate_i
315 yield self
.core_stopped_i
316 yield from self
.state
317 yield from self
.dbg_gpr
318 yield self
.log_data_i
319 yield self
.log_read_addr_i
320 yield self
.log_read_data_o
321 yield self
.log_write_addr_o
322 yield self
.terminated_o
331 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
332 with
open("test_core_debug.il", "w") as f
:
335 if __name__
== '__main__':