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update test case for radix mmu
[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 #from nmigen.back.pysim import Settle
17 from copy import copy
18 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from soc.decoder.helpers import exts, gtu, ltu, undefined
21 from soc.decoder.isa.mem import Mem
22 from soc.consts import MSRb # big-endian (PowerISA versions)
23
24 import math
25 import sys
26 import unittest
27
28 # very quick, TODO move to SelectableInt utils later
29 def genmask(shift, size):
30 res = SelectableInt(0, size)
31 for i in range(size):
32 if i < shift:
33 res[size-1-i] = SelectableInt(1, 1)
34 return res
35
36 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
37 # MSB is indexed **LOWEST** (sigh)
38 # from gem5 radixwalk.hh
39 # Bitfield<63> valid; 64 - (63 + 1) = 0
40 # Bitfield<62> leaf; 64 - (62 + 1) = 1
41
42 def rpte_valid(r):
43 return bool(r[0])
44
45 def rpte_leaf(r):
46 return bool(r[1])
47
48 ## Shift address bits 61--12 right by 0--47 bits and
49 ## supply the least significant 16 bits of the result.
50 def addrshift(addr,shift):
51 print("addrshift")
52 print(addr)
53 print(shift)
54 x = addr.value >> shift.value
55 return SelectableInt(x,16)
56
57 def NLB(x):
58 """
59 Next Level Base
60 right shifted by 8
61 """
62 return x[4:55]
63
64 def NLS(x):
65 """
66 Next Level Size
67 NLS >= 5
68 """
69 return x[59:63]
70
71 def RPDB(x):
72 """
73 Root Page Directory Base
74 power isa docs says 4:55 investigate
75 """
76 return x[8:56]
77
78 """
79 Get Root Page
80
81 //Accessing 2nd double word of partition table (pate1)
82 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
83 // PTCR Layout
84 // ====================================================
85 // -----------------------------------------------
86 // | /// | PATB | /// | PATS |
87 // -----------------------------------------------
88 // 0 4 51 52 58 59 63
89 // PATB[4:51] holds the base address of the Partition Table,
90 // right shifted by 12 bits.
91 // This is because the address of the Partition base is
92 // 4k aligned. Hence, the lower 12bits, which are always
93 // 0 are ommitted from the PTCR.
94 //
95 // Thus, The Partition Table Base is obtained by (PATB << 12)
96 //
97 // PATS represents the partition table size right-shifted by 12 bits.
98 // The minimal size of the partition table is 4k.
99 // Thus partition table size = (1 << PATS + 12).
100 //
101 // Partition Table
102 // ====================================================
103 // 0 PATE0 63 PATE1 127
104 // |----------------------|----------------------|
105 // | | |
106 // |----------------------|----------------------|
107 // | | |
108 // |----------------------|----------------------|
109 // | | | <-- effLPID
110 // |----------------------|----------------------|
111 // .
112 // .
113 // .
114 // |----------------------|----------------------|
115 // | | |
116 // |----------------------|----------------------|
117 //
118 // The effective LPID forms the index into the Partition Table.
119 //
120 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
121 // corresponding to that partition.
122 //
123 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
124 //
125 // PATE0 Layout
126 // -----------------------------------------------
127 // |1|RTS1|/| RPDB | RTS2 | RPDS |
128 // -----------------------------------------------
129 // 0 1 2 3 4 55 56 58 59 63
130 //
131 // HR[0] : For Radix Page table, first bit should be 1.
132 // RTS1[1:2] : Gives one fragment of the Radix treesize
133 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
134 // RTS = (RTS1 << 3 + RTS2) + 31.
135 //
136 // RPDB[4:55] = Root Page Directory Base.
137 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
138 // Thus, Root page directory size = 1 << (RPDS + 3).
139 // Note: RPDS >= 5.
140 //
141 // PATE1 Layout
142 // -----------------------------------------------
143 // |///| PRTB | // | PRTS |
144 // -----------------------------------------------
145 // 0 3 4 51 52 58 59 63
146 //
147 // PRTB[4:51] = Process Table Base. This is aligned to size.
148 // PRTS[59: 63] = Process Table Size right shifted by 12.
149 // Minimal size of the process table is 4k.
150 // Process Table Size = (1 << PRTS + 12).
151 // Note: PRTS <= 24.
152 //
153 // Computing the size aligned Process Table Base:
154 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
155 // Thus, the lower 12+PRTS bits of table_base will
156 // be zero.
157
158
159 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
160 //
161 // Process Table
162 // ==========================
163 // 0 PRTE0 63 PRTE1 127
164 // |----------------------|----------------------|
165 // | | |
166 // |----------------------|----------------------|
167 // | | |
168 // |----------------------|----------------------|
169 // | | | <-- effPID
170 // |----------------------|----------------------|
171 // .
172 // .
173 // .
174 // |----------------------|----------------------|
175 // | | |
176 // |----------------------|----------------------|
177 //
178 // The effective Process id (PID) forms the index into the Process Table.
179 //
180 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
181 // corresponding to that process
182 //
183 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
184 //
185 // PRTE0 Layout
186 // -----------------------------------------------
187 // |/|RTS1|/| RPDB | RTS2 | RPDS |
188 // -----------------------------------------------
189 // 0 1 2 3 4 55 56 58 59 63
190 //
191 // RTS1[1:2] : Gives one fragment of the Radix treesize
192 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
193 // RTS = (RTS1 << 3 + RTS2) << 31,
194 // since minimal Radix Tree size is 4G.
195 //
196 // RPDB = Root Page Directory Base.
197 // RPDS = Root Page Directory Size right shifted by 3.
198 // Thus, Root page directory size = RPDS << 3.
199 // Note: RPDS >= 5.
200 //
201 // PRTE1 Layout
202 // -----------------------------------------------
203 // | /// |
204 // -----------------------------------------------
205 // 0 63
206 // All bits are reserved.
207
208
209 """
210
211 testmem = {
212
213 0x10000: # PARTITION_TABLE_2 (not implemented yet)
214 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
215 0x800000000100000b,
216
217 0x30000: # RADIX_ROOT_PTE
218 # V = 1 L = 0 NLB = 0x400 NLS = 9
219 0x8000000000040009,
220 0x40000: # RADIX_SECOND_LEVEL
221 # V = 1 L = 1 SW = 0 RPN = 0
222 # R = 1 C = 1 ATT = 0 EAA 0x7
223 0xc000000000000187,
224
225 0x1000000: # PROCESS_TABLE_3
226 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
227 0x40000000000300ad,
228 }
229
230 # this one has a 2nd level RADIX with a RPN of 0x5000
231 testmem2 = {
232
233 0x10000: # PARTITION_TABLE_2 (not implemented yet)
234 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
235 0x800000000100000b,
236
237 0x30000: # RADIX_ROOT_PTE
238 # V = 1 L = 0 NLB = 0x400 NLS = 9
239 0x8000000000040009,
240 0x40000: # RADIX_SECOND_LEVEL
241 # V = 1 L = 1 SW = 0 RPN = 0x5000
242 # R = 1 C = 1 ATT = 0 EAA 0x7
243 0xc000000005000187,
244
245 0x1000000: # PROCESS_TABLE_3
246 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
247 0x40000000000300ad,
248 }
249
250 testresult = """
251 prtbl = 1000000
252 DCACHE GET 1000000 PROCESS_TABLE_3
253 DCACHE GET 30000 RADIX_ROOT_PTE V = 1 L = 0
254 DCACHE GET 40000 RADIX_SECOND_LEVEL V = 1 L = 1
255 DCACHE GET 10000 PARTITION_TABLE_2
256 translated done 1 err 0 badtree 0 addr 40000 pte 0
257 """
258
259 # see qemu/target/ppc/mmu-radix64.c for reference
260 class RADIX:
261 def __init__(self, mem, caller):
262 self.mem = mem
263 self.caller = caller
264 if caller is not None:
265 print("caller")
266 print(caller)
267 self.dsisr = self.caller.spr["DSISR"]
268 self.dar = self.caller.spr["DAR"]
269 self.pidr = self.caller.spr["PIDR"]
270 self.prtbl = self.caller.spr["PRTBL"]
271 self.msr = self.caller.msr
272
273 # cached page table stuff
274 self.pgtbl0 = 0
275 self.pt0_valid = False
276 self.pgtbl3 = 0
277 self.pt3_valid = False
278
279 def __call__(self, addr, sz):
280 val = self.ld(addr.value, sz, swap=False)
281 print("RADIX memread", addr, sz, val)
282 return SelectableInt(val, sz*8)
283
284 def ld(self, address, width=8, swap=True, check_in_mem=False,
285 instr_fetch=False):
286 print("RADIX: ld from addr 0x%x width %d" % (address, width))
287
288 priv = ~(self.msr[MSRb.PR].value) # problem-state ==> privileged
289 if instr_fetch:
290 mode = 'EXECUTE'
291 else:
292 mode = 'LOAD'
293 addr = SelectableInt(address, 64)
294 (shift, mbits, pgbase) = self._decode_prte(addr)
295 #shift = SelectableInt(0, 32)
296
297 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
298
299 if type(pte)==str:
300 print("error on load",pte)
301 return 0
302
303 # use pte to load from phys address
304 return self.mem.ld(pte.value, width, swap, check_in_mem)
305
306 # XXX set SPRs on error
307
308 # TODO implement
309 def st(self, address, v, width=8, swap=True):
310 print("RADIX: st to addr 0x%x width %d data %x" % (address, width, v))
311
312 priv = ~(self.msr[MSRb.PR].value) # problem-state ==> privileged
313 mode = 'STORE'
314 addr = SelectableInt(address, 64)
315 (shift, mbits, pgbase) = self._decode_prte(addr)
316 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
317
318 # use pte to store at phys address
319 return self.mem.st(pte.value, v, width, swap)
320
321 # XXX set SPRs on error
322
323 def memassign(self, addr, sz, val):
324 print("memassign", addr, sz, val)
325 self.st(addr.value, val.value, sz, swap=False)
326
327 def _next_level(self, addr, entry_width, swap, check_in_mem):
328 # implement read access to mmu mem here
329
330 # DO NOT perform byte-swapping: load 8 bytes (that's the entry size)
331 value = self.mem.ld(addr.value, 8, False, check_in_mem)
332 if value is None:
333 return "address lookup %x not found" % addr.value
334 # assert(value is not None, "address lookup %x not found" % addr.value)
335
336 print("addr", hex(addr.value))
337 data = SelectableInt(value, 64) # convert to SelectableInt
338 print("value", hex(value))
339 # index += 1
340 return data;
341
342 def _walk_tree(self, addr, pgbase, mode, mbits, shift, priv=1):
343 """walk tree
344
345 // vaddr 64 Bit
346 // vaddr |-----------------------------------------------------|
347 // | Unused | Used |
348 // |-----------|-----------------------------------------|
349 // | 0000000 | usefulBits = X bits (typically 52) |
350 // |-----------|-----------------------------------------|
351 // | |<--Cursize---->| |
352 // | | Index | |
353 // | | into Page | |
354 // | | Directory | |
355 // |-----------------------------------------------------|
356 // | |
357 // V |
358 // PDE |---------------------------| |
359 // |V|L|//| NLB |///|NLS| |
360 // |---------------------------| |
361 // PDE = Page Directory Entry |
362 // [0] = V = Valid Bit |
363 // [1] = L = Leaf bit. If 0, then |
364 // [4:55] = NLB = Next Level Base |
365 // right shifted by 8 |
366 // [59:63] = NLS = Next Level Size |
367 // | NLS >= 5 |
368 // | V
369 // | |--------------------------|
370 // | | usfulBits = X-Cursize |
371 // | |--------------------------|
372 // |---------------------><--NLS-->| |
373 // | Index | |
374 // | into | |
375 // | PDE | |
376 // |--------------------------|
377 // |
378 // If the next PDE obtained by |
379 // (NLB << 8 + 8 * index) is a |
380 // nonleaf, then repeat the above. |
381 // |
382 // If the next PDE is a leaf, |
383 // then Leaf PDE structure is as |
384 // follows |
385 // |
386 // |
387 // Leaf PDE |
388 // |------------------------------| |----------------|
389 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
390 // |------------------------------| |----------------|
391 // [0] = V = Valid Bit |
392 // [1] = L = Leaf Bit = 1 if leaf |
393 // PDE |
394 // [2] = Sw = Sw bit 0. |
395 // [7:51] = RPN = Real Page Number, V
396 // real_page = RPN << 12 -------------> Logical OR
397 // [52:54] = Sw Bits 1:3 |
398 // [55] = R = Reference |
399 // [56] = C = Change V
400 // [58:59] = Att = Physical Address
401 // 0b00 = Normal Memory
402 // 0b01 = SAO
403 // 0b10 = Non Idenmpotent
404 // 0b11 = Tolerant I/O
405 // [60:63] = Encoded Access
406 // Authority
407 //
408 """
409 # get sprs
410 print("_walk_tree")
411 pidr = self.caller.spr["PIDR"]
412 prtbl = self.caller.spr["PRTBL"]
413 print(pidr)
414 print(prtbl)
415 p = addr[55:63]
416 print("last 8 bits ----------")
417 print
418
419 # get address of root entry
420 shift = selectconcat(SelectableInt(0,1), prtbl[58:63]) # TODO verify
421 addr_next = self._get_prtable_addr(shift, prtbl, addr, pidr)
422 print("starting with prtable, addr_next",addr_next)
423
424 assert(addr_next.bits == 64)
425 #only for first unit tests assert(addr_next.value == 0x1000000)
426
427 # read an entry from prtable
428 swap = False
429 check_in_mem = False
430 entry_width = 8
431 data = self._next_level(addr_next, entry_width, swap, check_in_mem)
432 print("pr_table",data)
433 pgtbl = data # this is cached in microwatt (as v.pgtbl3 / v.pgtbl0)
434
435 # rts = shift = unsigned('0' & data(62 downto 61) & data(7 downto 5));
436 shift = selectconcat(SelectableInt(0,1), data[1:3], data[55:58])
437 assert(shift.bits==6) # variable rts : unsigned(5 downto 0);
438 print("shift",shift)
439
440 # mbits := unsigned('0' & data(4 downto 0));
441 mbits = selectconcat(SelectableInt(0,1), data[58:63])
442 assert(mbits.bits==6) #variable mbits : unsigned(5 downto 0);
443
444 # WIP
445 if mbits==0:
446 return "invalid"
447
448 # mask_size := mbits(4 downto 0);
449 mask_size = mbits[0:5];
450 assert(mask_size.bits==5)
451 print("before segment check ==========")
452 print("mask_size:",bin(mask_size.value))
453 print("mbits:",bin(mbits.value))
454
455 print("calling segment_check")
456
457 mbits = selectconcat(SelectableInt(0,1), mask_size)
458 shift = self._segment_check(addr, mbits, shift)
459 print("shift",shift)
460
461 # v.pgbase := pgtbl(55 downto 8) & x"00";
462 # see test_RPDB for reference
463 zero8 = SelectableInt(0,8)
464
465 pgbase = selectconcat(zero8,RPDB(pgtbl),zero8)
466 print("pgbase",pgbase)
467 #assert(pgbase.value==0x30000)
468
469 if type(addr) == str:
470 return addr
471 if type(shift) == str:
472 return shift
473
474 addrsh = addrshift(addr,shift)
475 print("addrsh",addrsh)
476
477 addr_next = self._get_pgtable_addr(mask_size, pgbase, addrsh)
478 print("DONE addr_next",addr_next)
479
480 # walk tree
481 while True:
482 print("nextlevel----------------------------")
483 # read an entry
484 swap = False
485 check_in_mem = False
486 entry_width = 8
487
488 data = self._next_level(addr_next, entry_width, swap, check_in_mem)
489 valid = rpte_valid(data)
490 leaf = rpte_leaf(data)
491
492 print(" valid, leaf", valid, leaf)
493 if not valid:
494 return "invalid" # TODO: return error
495 if leaf:
496 print ("is leaf, checking perms")
497 ok = self._check_perms(data, priv, mode)
498 if ok == True: # data was ok, found phys address, return it?
499 paddr = self._get_pte(addrsh, addr, data)
500 print (" phys addr", hex(paddr.value))
501 return paddr
502 return ok # return the error code
503 else:
504 newlookup = self._new_lookup(data, shift)
505 if newlookup == 'badtree':
506 return newlookup
507 shift, mask, pgbase = newlookup
508 print (" next level", shift, mask, pgbase)
509 shift = SelectableInt(shift.value,16) #THIS is wrong !!!
510 print("calling _get_pgtable_addr")
511 print(mask) #SelectableInt(value=0x9, bits=4)
512 print(pgbase) #SelectableInt(value=0x40000, bits=56)
513 print(shift) #SelectableInt(value=0x4, bits=16) #FIXME
514 pgbase = SelectableInt(pgbase.value, 64)
515 addrsh = addrshift(addr,shift)
516 addr_next = self._get_pgtable_addr(mask, pgbase, addrsh)
517 print("addr_next",addr_next)
518 print("addrsh",addrsh)
519
520 def _new_lookup(self, data, shift):
521 """
522 mbits := unsigned('0' & data(4 downto 0));
523 if mbits < 5 or mbits > 16 or mbits > r.shift then
524 v.state := RADIX_FINISH;
525 v.badtree := '1'; -- throw error
526 else
527 v.shift := v.shift - mbits;
528 v.mask_size := mbits(4 downto 0);
529 v.pgbase := data(55 downto 8) & x"00"; NLB?
530 v.state := RADIX_LOOKUP; --> next level
531 end if;
532 """
533 mbits = data[59:64]
534 print("mbits=", mbits)
535 if mbits < 5 or mbits > 16: #fixme compare with r.shift
536 print("badtree")
537 return "badtree"
538 # reduce shift (has to be done at same bitwidth)
539 shift = shift - selectconcat(SelectableInt(0, 1), mbits)
540 mask_size = mbits[1:5] # get 4 LSBs
541 pgbase = selectconcat(data[8:56], SelectableInt(0, 8)) # shift up 8
542 return shift, mask_size, pgbase
543
544 def _decode_prte(self, data):
545 """PRTE0 Layout
546 -----------------------------------------------
547 |/|RTS1|/| RPDB | RTS2 | RPDS |
548 -----------------------------------------------
549 0 1 2 3 4 55 56 58 59 63
550 """
551 # note that SelectableInt does big-endian! so the indices
552 # below *directly* match the spec, unlike microwatt which
553 # has to turn them around (to LE)
554 zero = SelectableInt(0, 1)
555 rts = selectconcat(zero,
556 data[56:59], # RTS2
557 data[1:3], # RTS1
558 )
559 masksize = data[59:64] # RPDS
560 mbits = selectconcat(zero, masksize)
561 pgbase = selectconcat(data[8:56], # part of RPDB
562 SelectableInt(0, 16),)
563
564 return (rts, mbits, pgbase)
565
566 def _segment_check(self, addr, mbits, shift):
567 """checks segment valid
568 mbits := '0' & r.mask_size;
569 v.shift := r.shift + (31 - 12) - mbits;
570 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
571 if r.addr(63) /= r.addr(62) or nonzero = '1' then
572 v.state := RADIX_FINISH;
573 v.segerror := '1';
574 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
575 v.state := RADIX_FINISH;
576 v.badtree := '1';
577 else
578 v.state := RADIX_LOOKUP;
579 """
580 # note that SelectableInt does big-endian! so the indices
581 # below *directly* match the spec, unlike microwatt which
582 # has to turn them around (to LE)
583 mask = genmask(shift, 44)
584 nonzero = addr[2:33] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
585 print ("RADIX _segment_check nonzero", bin(nonzero.value))
586 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
587 if addr[0] != addr[1] or nonzero != 0:
588 return "segerror"
589 limit = shift + (31 - 12)
590 if mbits.value < 5 or mbits.value > 16 or mbits.value > limit.value:
591 return "badtree mbits="+str(mbits.value)+" limit="+str(limit.value)
592 new_shift = shift + (31 - 12) - mbits
593 # TODO verify that returned result is correct
594 return new_shift
595
596 def _check_perms(self, data, priv, mode):
597 """check page permissions
598 // Leaf PDE |
599 // |------------------------------| |----------------|
600 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
601 // |------------------------------| |----------------|
602 // [0] = V = Valid Bit |
603 // [1] = L = Leaf Bit = 1 if leaf |
604 // PDE |
605 // [2] = Sw = Sw bit 0. |
606 // [7:51] = RPN = Real Page Number, V
607 // real_page = RPN << 12 -------------> Logical OR
608 // [52:54] = Sw Bits 1:3 |
609 // [55] = R = Reference |
610 // [56] = C = Change V
611 // [58:59] = Att = Physical Address
612 // 0b00 = Normal Memory
613 // 0b01 = SAO
614 // 0b10 = Non Idenmpotent
615 // 0b11 = Tolerant I/O
616 // [60:63] = Encoded Access
617 // Authority
618 //
619 -- test leaf bit
620 -- check permissions and RC bits
621 perm_ok := '0';
622 if r.priv = '1' or data(3) = '0' then
623 if r.iside = '0' then
624 perm_ok := data(1) or (data(2) and not r.store);
625 else
626 -- no IAMR, so no KUEP support for now
627 -- deny execute permission if cache inhibited
628 perm_ok := data(0) and not data(5);
629 end if;
630 end if;
631 rc_ok := data(8) and (data(7) or not r.store);
632 if perm_ok = '1' and rc_ok = '1' then
633 v.state := RADIX_LOAD_TLB;
634 else
635 v.state := RADIX_FINISH;
636 v.perm_err := not perm_ok;
637 -- permission error takes precedence over RC error
638 v.rc_error := perm_ok;
639 end if;
640 """
641 # decode mode into something that matches microwatt equivalent code
642 instr_fetch, store = 0, 0
643 if mode == 'STORE':
644 store = 1
645 if mode == 'EXECUTE':
646 inst_fetch = 1
647
648 # check permissions and RC bits
649 perm_ok = 0
650 if priv == 1 or data[60] == 0:
651 if instr_fetch == 0:
652 perm_ok = data[62] | (data[61] & (store == 0))
653 # no IAMR, so no KUEP support for now
654 # deny execute permission if cache inhibited
655 perm_ok = data[63] & ~data[58]
656 rc_ok = data[55] & (data[56] | (store == 0))
657 if perm_ok == 1 and rc_ok == 1:
658 return True
659
660 return "perm_err" if perm_ok == 0 else "rc_err"
661
662 def _get_prtable_addr(self, shift, prtbl, addr, pid):
663 """
664 if r.addr(63) = '1' then
665 effpid := x"00000000";
666 else
667 effpid := r.pid;
668 end if;
669 x"00" & r.prtbl(55 downto 36) &
670 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
671 (effpid(31 downto 8) and finalmask(23 downto 0))) &
672 effpid(7 downto 0) & "0000";
673 """
674 print ("_get_prtable_addr", shift, prtbl, addr, pid)
675 finalmask = genmask(shift, 44)
676 finalmask24 = finalmask[20:44]
677 if addr[0].value == 1:
678 effpid = SelectableInt(0, 32)
679 else:
680 effpid = pid #self.pid # TODO, check on this
681 zero8 = SelectableInt(0, 8)
682 zero4 = SelectableInt(0, 4)
683 res = selectconcat(zero8,
684 prtbl[8:28], #
685 (prtbl[28:52] & ~finalmask24) | #
686 (effpid[0:24] & finalmask24), #
687 effpid[24:32],
688 zero4
689 )
690 return res
691
692 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
693 """
694 x"00" & r.pgbase(55 downto 19) &
695 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
696 "000";
697 """
698 mask16 = genmask(mask_size+5, 16)
699 zero8 = SelectableInt(0, 8)
700 zero3 = SelectableInt(0, 3)
701 res = selectconcat(zero8,
702 pgbase[8:45], #
703 (pgbase[45:61] & ~mask16) | #
704 (addrsh & mask16), #
705 zero3
706 )
707 return res
708
709 def _get_pte(self, shift, addr, pde):
710 """
711 x"00" &
712 ((r.pde(55 downto 12) and not finalmask) or
713 (r.addr(55 downto 12) and finalmask))
714 & r.pde(11 downto 0);
715 """
716 shift.value = 12
717 finalmask = genmask(shift, 44)
718 zero8 = SelectableInt(0, 8)
719 rpn = pde[8:52] # RPN = Real Page Number
720 abits = addr[8:52] # non-masked address bits
721 print(" get_pte RPN", hex(rpn.value))
722 print(" abits", hex(abits.value))
723 print(" shift", shift.value)
724 print(" finalmask", bin(finalmask.value))
725 res = selectconcat(zero8,
726 (rpn & ~finalmask) | #
727 (abits & finalmask), #
728 addr[52:64],
729 )
730 return res
731
732 class TestRadixMMU(unittest.TestCase):
733
734 def test_genmask(self):
735 shift = SelectableInt(5, 6)
736 mask = genmask(shift, 43)
737 print (" mask", bin(mask.value))
738
739 self.assertEqual(mask.value, 0b11111, "mask should be 5 1s")
740
741 def test_RPDB(self):
742 inp = SelectableInt(0x40000000000300ad, 64)
743
744 rtdb = RPDB(inp)
745 print("rtdb",rtdb,bin(rtdb.value))
746 self.assertEqual(rtdb.value,0x300,"rtdb should be 0x300")
747
748 result = selectconcat(rtdb,SelectableInt(0,8))
749 print("result",result)
750
751
752 def test_get_pgtable_addr(self):
753
754 mem = None
755 caller = None
756 dut = RADIX(mem, caller)
757
758 mask_size=4
759 pgbase = SelectableInt(0,64)
760 addrsh = SelectableInt(0,16)
761 ret = dut._get_pgtable_addr(mask_size, pgbase, addrsh)
762 print("ret=", ret)
763 self.assertEqual(ret, 0, "pgtbl_addr should be 0")
764
765 def test_walk_tree_1(self):
766
767 # test address as in
768 # https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/radix_walk_example.txt#L65
769 testaddr = 0x1000
770 expected = 0x1000
771
772 # starting prtbl
773 prtbl = 0x1000000
774
775 # set up dummy minimal ISACaller
776 spr = {'DSISR': SelectableInt(0, 64),
777 'DAR': SelectableInt(0, 64),
778 'PIDR': SelectableInt(0, 64),
779 'PRTBL': SelectableInt(prtbl, 64)
780 }
781 # set problem state == 0 (other unit tests, set to 1)
782 msr = SelectableInt(0, 64)
783 msr[MSRb.PR] = 0
784 class ISACaller: pass
785 caller = ISACaller()
786 caller.spr = spr
787 caller.msr = msr
788
789 shift = SelectableInt(5, 6)
790 mask = genmask(shift, 43)
791 print (" mask", bin(mask.value))
792
793 mem = Mem(row_bytes=8, initial_mem=testmem)
794 mem = RADIX(mem, caller)
795 # -----------------------------------------------
796 # |/|RTS1|/| RPDB | RTS2 | RPDS |
797 # -----------------------------------------------
798 # |0|1 2|3|4 55|56 58|59 63|
799 data = SelectableInt(0, 64)
800 data[1:3] = 0b01
801 data[56:59] = 0b11
802 data[59:64] = 0b01101 # mask
803 data[55] = 1
804 (rts, mbits, pgbase) = mem._decode_prte(data)
805 print (" rts", bin(rts.value), rts.bits)
806 print (" mbits", bin(mbits.value), mbits.bits)
807 print (" pgbase", hex(pgbase.value), pgbase.bits)
808 addr = SelectableInt(0x1000, 64)
809 check = mem._segment_check(addr, mbits, shift)
810 print (" segment check", check)
811
812 print("walking tree")
813 addr = SelectableInt(testaddr,64)
814 # pgbase = None
815 mode = None
816 #mbits = None
817 shift = rts
818 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
819 print(" walking tree result", result)
820 print("should be", testresult)
821 self.assertEqual(result.value, expected,
822 "expected 0x%x got 0x%x" % (expected,
823 result.value))
824
825
826 def test_walk_tree_2(self):
827
828 # test address slightly different
829 testaddr = 0x1101
830 expected = 0x5001101
831
832 # starting prtbl
833 prtbl = 0x1000000
834
835 # set up dummy minimal ISACaller
836 spr = {'DSISR': SelectableInt(0, 64),
837 'DAR': SelectableInt(0, 64),
838 'PIDR': SelectableInt(0, 64),
839 'PRTBL': SelectableInt(prtbl, 64)
840 }
841 # set problem state == 0 (other unit tests, set to 1)
842 msr = SelectableInt(0, 64)
843 msr[MSRb.PR] = 0
844 class ISACaller: pass
845 caller = ISACaller()
846 caller.spr = spr
847 caller.msr = msr
848
849 shift = SelectableInt(5, 6)
850 mask = genmask(shift, 43)
851 print (" mask", bin(mask.value))
852
853 mem = Mem(row_bytes=8, initial_mem=testmem2)
854 mem = RADIX(mem, caller)
855 # -----------------------------------------------
856 # |/|RTS1|/| RPDB | RTS2 | RPDS |
857 # -----------------------------------------------
858 # |0|1 2|3|4 55|56 58|59 63|
859 data = SelectableInt(0, 64)
860 data[1:3] = 0b01
861 data[56:59] = 0b11
862 data[59:64] = 0b01101 # mask
863 data[55] = 1
864 (rts, mbits, pgbase) = mem._decode_prte(data)
865 print (" rts", bin(rts.value), rts.bits)
866 print (" mbits", bin(mbits.value), mbits.bits)
867 print (" pgbase", hex(pgbase.value), pgbase.bits)
868 addr = SelectableInt(0x1000, 64)
869 check = mem._segment_check(addr, mbits, shift)
870 print (" segment check", check)
871
872 print("walking tree")
873 addr = SelectableInt(testaddr,64)
874 # pgbase = None
875 mode = None
876 #mbits = None
877 shift = rts
878 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
879 print(" walking tree result", result)
880 print("should be", testresult)
881 self.assertEqual(result.value, expected,
882 "expected 0x%x got 0x%x" % (expected,
883 result.value))
884
885
886 if __name__ == '__main__':
887 unittest.main()