projects / soc.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
sort out predicate zeroing in ISACaller
[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 from nmigen.back.pysim import Settle
17 from copy import copy
18 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from soc.decoder.helpers import exts, gtu, ltu, undefined
21 from soc.decoder.isa.mem import Mem
22 from soc.consts import MSRb # big-endian (PowerISA versions)
23
24 import math
25 import sys
26
27 # very quick, TODO move to SelectableInt utils later
28 def genmask(shift, size):
29 res = SelectableInt(0, size)
30 for i in range(size):
31 if i < shift:
32 res[size-1-i] = SelectableInt(1, 1)
33 return res
34
35 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
36 # MSB is indexed **LOWEST** (sigh)
37 # from gem5 radixwalk.hh
38 # Bitfield<63> valid; 64 - (63 + 1) = 0
39 # Bitfield<62> leaf; 64 - (62 + 1) = 1
40
41 def rpte_valid(r):
42 return bool(r[0])
43
44 def rpte_leaf(r):
45 return bool(r[1])
46
47 def NLB(x):
48 """
49 Next Level Base
50 right shifted by 8
51 """
52 return x[4:55]
53
54 def NLS(x):
55 """
56 Next Level Size
57 NLS >= 5
58 """
59 return x[59:63]
60
61 """
62 Get Root Page
63
64 //Accessing 2nd double word of partition table (pate1)
65 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
66 // PTCR Layout
67 // ====================================================
68 // -----------------------------------------------
69 // | /// | PATB | /// | PATS |
70 // -----------------------------------------------
71 // 0 4 51 52 58 59 63
72 // PATB[4:51] holds the base address of the Partition Table,
73 // right shifted by 12 bits.
74 // This is because the address of the Partition base is
75 // 4k aligned. Hence, the lower 12bits, which are always
76 // 0 are ommitted from the PTCR.
77 //
78 // Thus, The Partition Table Base is obtained by (PATB << 12)
79 //
80 // PATS represents the partition table size right-shifted by 12 bits.
81 // The minimal size of the partition table is 4k.
82 // Thus partition table size = (1 << PATS + 12).
83 //
84 // Partition Table
85 // ====================================================
86 // 0 PATE0 63 PATE1 127
87 // |----------------------|----------------------|
88 // | | |
89 // |----------------------|----------------------|
90 // | | |
91 // |----------------------|----------------------|
92 // | | | <-- effLPID
93 // |----------------------|----------------------|
94 // .
95 // .
96 // .
97 // |----------------------|----------------------|
98 // | | |
99 // |----------------------|----------------------|
100 //
101 // The effective LPID forms the index into the Partition Table.
102 //
103 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
104 // corresponding to that partition.
105 //
106 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
107 //
108 // PATE0 Layout
109 // -----------------------------------------------
110 // |1|RTS1|/| RPDB | RTS2 | RPDS |
111 // -----------------------------------------------
112 // 0 1 2 3 4 55 56 58 59 63
113 //
114 // HR[0] : For Radix Page table, first bit should be 1.
115 // RTS1[1:2] : Gives one fragment of the Radix treesize
116 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
117 // RTS = (RTS1 << 3 + RTS2) + 31.
118 //
119 // RPDB[4:55] = Root Page Directory Base.
120 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
121 // Thus, Root page directory size = 1 << (RPDS + 3).
122 // Note: RPDS >= 5.
123 //
124 // PATE1 Layout
125 // -----------------------------------------------
126 // |///| PRTB | // | PRTS |
127 // -----------------------------------------------
128 // 0 3 4 51 52 58 59 63
129 //
130 // PRTB[4:51] = Process Table Base. This is aligned to size.
131 // PRTS[59: 63] = Process Table Size right shifted by 12.
132 // Minimal size of the process table is 4k.
133 // Process Table Size = (1 << PRTS + 12).
134 // Note: PRTS <= 24.
135 //
136 // Computing the size aligned Process Table Base:
137 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
138 // Thus, the lower 12+PRTS bits of table_base will
139 // be zero.
140
141
142 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
143 //
144 // Process Table
145 // ==========================
146 // 0 PRTE0 63 PRTE1 127
147 // |----------------------|----------------------|
148 // | | |
149 // |----------------------|----------------------|
150 // | | |
151 // |----------------------|----------------------|
152 // | | | <-- effPID
153 // |----------------------|----------------------|
154 // .
155 // .
156 // .
157 // |----------------------|----------------------|
158 // | | |
159 // |----------------------|----------------------|
160 //
161 // The effective Process id (PID) forms the index into the Process Table.
162 //
163 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
164 // corresponding to that process
165 //
166 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
167 //
168 // PRTE0 Layout
169 // -----------------------------------------------
170 // |/|RTS1|/| RPDB | RTS2 | RPDS |
171 // -----------------------------------------------
172 // 0 1 2 3 4 55 56 58 59 63
173 //
174 // RTS1[1:2] : Gives one fragment of the Radix treesize
175 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
176 // RTS = (RTS1 << 3 + RTS2) << 31,
177 // since minimal Radix Tree size is 4G.
178 //
179 // RPDB = Root Page Directory Base.
180 // RPDS = Root Page Directory Size right shifted by 3.
181 // Thus, Root page directory size = RPDS << 3.
182 // Note: RPDS >= 5.
183 //
184 // PRTE1 Layout
185 // -----------------------------------------------
186 // | /// |
187 // -----------------------------------------------
188 // 0 63
189 // All bits are reserved.
190
191
192 """
193
194 testaddr = 0x10000
195 testmem = {
196
197 0x10000: # PARTITION_TABLE_2 (not implemented yet)
198 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
199 0x800000000100000b,
200
201 0x30000: # RADIX_ROOT_PTE
202 # V = 1 L = 0 NLB = 0x400 NLS = 9
203 0x8000000000040009,
204 ######## 0x4000000 #### wrong address calculated by _get_pgtable_addr
205 0x40000: # RADIX_SECOND_LEVEL
206 # V = 1 L = 1 SW = 0 RPN = 0
207 # R = 1 C = 1 ATT = 0 EAA 0x7
208 0xc000000000000187,
209
210 0x1000000: # PROCESS_TABLE_3
211 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
212 0x40000000000300ad,
213 }
214
215
216
217 # see qemu/target/ppc/mmu-radix64.c for reference
218 class RADIX:
219 def __init__(self, mem, caller):
220 self.mem = mem
221 self.caller = caller
222 #TODO move to lookup
223 self.dsisr = self.caller.spr["DSISR"]
224 self.dar = self.caller.spr["DAR"]
225 self.pidr = self.caller.spr["PIDR"]
226 self.prtbl = self.caller.spr["PRTBL"]
227 self.msr = self.caller.msr
228
229 # cached page table stuff
230 self.pgtbl0 = 0
231 self.pt0_valid = False
232 self.pgtbl3 = 0
233 self.pt3_valid = False
234
235 def __call__(self, addr, sz):
236 val = self.ld(addr.value, sz, swap=False)
237 print("RADIX memread", addr, sz, val)
238 return SelectableInt(val, sz*8)
239
240 def ld(self, address, width=8, swap=True, check_in_mem=False,
241 instr_fetch=False):
242 print("RADIX: ld from addr 0x%x width %d" % (address, width))
243
244 priv = ~(self.msr(MSR_PR).value) # problem-state ==> privileged
245 if instr_fetch:
246 mode = 'EXECUTE'
247 else:
248 mode = 'LOAD'
249 addr = SelectableInt(address, 64)
250 (shift, mbits, pgbase) = self._decode_prte(addr)
251 #shift = SelectableInt(0, 32)
252
253 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
254 # use pte to caclculate phys address
255 return self.mem.ld(address, width, swap, check_in_mem)
256
257 # XXX set SPRs on error
258
259 # TODO implement
260 def st(self, address, v, width=8, swap=True):
261 print("RADIX: st to addr 0x%x width %d data %x" % (address, width, v))
262
263 priv = ~(self.msr(MSR_PR).value) # problem-state ==> privileged
264 mode = 'STORE'
265 addr = SelectableInt(address, 64)
266 (shift, mbits, pgbase) = self._decode_prte(addr)
267 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
268
269 # use pte to caclculate phys address (addr)
270 return self.mem.st(addr.value, v, width, swap)
271
272 # XXX set SPRs on error
273
274 def memassign(self, addr, sz, val):
275 print("memassign", addr, sz, val)
276 self.st(addr.value, val.value, sz, swap=False)
277
278 def _next_level(self, addr, entry_width, swap, check_in_mem):
279 # implement read access to mmu mem here
280
281 value = 0
282 if addr.value in testmem:
283 value = testmem[addr.value]
284 else:
285 print("not found")
286
287 ##value = self.mem.ld(addr.value, entry_width, swap, check_in_mem)
288 print("addr", hex(addr.value))
289 data = SelectableInt(value, 64) # convert to SelectableInt
290 print("value", hex(value))
291 # index += 1
292 return data;
293
294 def _walk_tree(self, addr, pgbase, mode, mbits, shift, priv=1):
295 """walk tree
296
297 // vaddr 64 Bit
298 // vaddr |-----------------------------------------------------|
299 // | Unused | Used |
300 // |-----------|-----------------------------------------|
301 // | 0000000 | usefulBits = X bits (typically 52) |
302 // |-----------|-----------------------------------------|
303 // | |<--Cursize---->| |
304 // | | Index | |
305 // | | into Page | |
306 // | | Directory | |
307 // |-----------------------------------------------------|
308 // | |
309 // V |
310 // PDE |---------------------------| |
311 // |V|L|//| NLB |///|NLS| |
312 // |---------------------------| |
313 // PDE = Page Directory Entry |
314 // [0] = V = Valid Bit |
315 // [1] = L = Leaf bit. If 0, then |
316 // [4:55] = NLB = Next Level Base |
317 // right shifted by 8 |
318 // [59:63] = NLS = Next Level Size |
319 // | NLS >= 5 |
320 // | V
321 // | |--------------------------|
322 // | | usfulBits = X-Cursize |
323 // | |--------------------------|
324 // |---------------------><--NLS-->| |
325 // | Index | |
326 // | into | |
327 // | PDE | |
328 // |--------------------------|
329 // |
330 // If the next PDE obtained by |
331 // (NLB << 8 + 8 * index) is a |
332 // nonleaf, then repeat the above. |
333 // |
334 // If the next PDE is a leaf, |
335 // then Leaf PDE structure is as |
336 // follows |
337 // |
338 // |
339 // Leaf PDE |
340 // |------------------------------| |----------------|
341 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
342 // |------------------------------| |----------------|
343 // [0] = V = Valid Bit |
344 // [1] = L = Leaf Bit = 1 if leaf |
345 // PDE |
346 // [2] = Sw = Sw bit 0. |
347 // [7:51] = RPN = Real Page Number, V
348 // real_page = RPN << 12 -------------> Logical OR
349 // [52:54] = Sw Bits 1:3 |
350 // [55] = R = Reference |
351 // [56] = C = Change V
352 // [58:59] = Att = Physical Address
353 // 0b00 = Normal Memory
354 // 0b01 = SAO
355 // 0b10 = Non Idenmpotent
356 // 0b11 = Tolerant I/O
357 // [60:63] = Encoded Access
358 // Authority
359 //
360 """
361 # get sprs
362 print("_walk_tree")
363 pidr = self.caller.spr["PIDR"]
364 prtbl = self.caller.spr["PRTBL"]
365 print(pidr)
366 print(prtbl)
367 p = addr[55:63]
368 print("last 8 bits ----------")
369 print
370
371 # get address of root entry
372 addr_next = self._get_prtable_addr(shift, prtbl, addr, pidr)
373
374 addr_next = SelectableInt(0x30000,64) # radix root for testing
375
376 # walk tree starts on prtbl
377 while True:
378 print("nextlevel----------------------------")
379 # read an entry
380 swap = False
381 check_in_mem = False
382 entry_width = 8
383
384 data = self._next_level(addr_next, entry_width, swap, check_in_mem)
385 valid = rpte_valid(data)
386 leaf = rpte_leaf(data)
387
388 print(" valid, leaf", valid, leaf)
389 if not valid:
390 return "invalid" # TODO: return error
391 if leaf:
392 ok = self._check_perms(data, priv, mode)
393 if ok == True: # data was ok, found phys address, return it?
394 return addr_next
395 return ok # return the error code
396 else:
397 newlookup = self._new_lookup(data, mbits, shift)
398 if newlookup == 'badtree':
399 return newlookup
400 shift, mask, pgbase = newlookup
401 print (" next level", shift, mask, pgbase)
402 shift = SelectableInt(shift.value,16) #FIXME
403 addr_next = self._get_pgtable_addr(mask, pgbase, shift, prtbl)
404
405 def _new_lookup(self, data, mbits, shift):
406 """
407 mbits := unsigned('0' & data(4 downto 0));
408 if mbits < 5 or mbits > 16 or mbits > r.shift then
409 v.state := RADIX_FINISH;
410 v.badtree := '1'; -- throw error
411 else
412 v.shift := v.shift - mbits;
413 v.mask_size := mbits(4 downto 0);
414 v.pgbase := data(55 downto 8) & x"00"; NLB?
415 v.state := RADIX_LOOKUP; --> next level
416 end if;
417 """
418 mbits = data[59:64]
419 print("mbits=", mbits)
420 if mbits < 5 or mbits > 16: #fixme compare with r.shift
421 print("badtree")
422 return "badtree"
423 # reduce shift (has to be done at same bitwidth)
424 shift = shift - selectconcat(SelectableInt(0, 1), mbits)
425 mask_size = mbits[1:5] # get 4 LSBs
426 pgbase = selectconcat(data[8:56], SelectableInt(0, 8)) # shift up 8
427 return shift, mask_size, pgbase
428
429 def _decode_prte(self, data):
430 """PRTE0 Layout
431 -----------------------------------------------
432 |/|RTS1|/| RPDB | RTS2 | RPDS |
433 -----------------------------------------------
434 0 1 2 3 4 55 56 58 59 63
435 """
436 # note that SelectableInt does big-endian! so the indices
437 # below *directly* match the spec, unlike microwatt which
438 # has to turn them around (to LE)
439 zero = SelectableInt(0, 1)
440 rts = selectconcat(zero,
441 data[56:59], # RTS2
442 data[1:3], # RTS1
443 )
444 masksize = data[59:64] # RPDS
445 mbits = selectconcat(zero, masksize)
446 pgbase = selectconcat(data[8:56], # part of RPDB
447 SelectableInt(0, 16),)
448
449 return (rts, mbits, pgbase)
450
451 def _segment_check(self, addr, mbits, shift):
452 """checks segment valid
453 mbits := '0' & r.mask_size;
454 v.shift := r.shift + (31 - 12) - mbits;
455 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
456 if r.addr(63) /= r.addr(62) or nonzero = '1' then
457 v.state := RADIX_FINISH;
458 v.segerror := '1';
459 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
460 v.state := RADIX_FINISH;
461 v.badtree := '1';
462 else
463 v.state := RADIX_LOOKUP;
464 """
465 # note that SelectableInt does big-endian! so the indices
466 # below *directly* match the spec, unlike microwatt which
467 # has to turn them around (to LE)
468 mask = genmask(shift, 44)
469 nonzero = addr[1:32] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
470 print ("RADIX _segment_check nonzero", bin(nonzero.value))
471 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
472 if addr[0] != addr[1] or nonzero == 1:
473 return "segerror"
474 limit = shift + (31 - 12)
475 if mbits < 5 or mbits > 16 or mbits > limit:
476 return "badtree"
477 new_shift = shift + (31 - 12) - mbits
478 return new_shift
479
480 def _check_perms(self, data, priv, mode):
481 """check page permissions
482 // Leaf PDE |
483 // |------------------------------| |----------------|
484 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
485 // |------------------------------| |----------------|
486 // [0] = V = Valid Bit |
487 // [1] = L = Leaf Bit = 1 if leaf |
488 // PDE |
489 // [2] = Sw = Sw bit 0. |
490 // [7:51] = RPN = Real Page Number, V
491 // real_page = RPN << 12 -------------> Logical OR
492 // [52:54] = Sw Bits 1:3 |
493 // [55] = R = Reference |
494 // [56] = C = Change V
495 // [58:59] = Att = Physical Address
496 // 0b00 = Normal Memory
497 // 0b01 = SAO
498 // 0b10 = Non Idenmpotent
499 // 0b11 = Tolerant I/O
500 // [60:63] = Encoded Access
501 // Authority
502 //
503 -- test leaf bit
504 -- check permissions and RC bits
505 perm_ok := '0';
506 if r.priv = '1' or data(3) = '0' then
507 if r.iside = '0' then
508 perm_ok := data(1) or (data(2) and not r.store);
509 else
510 -- no IAMR, so no KUEP support for now
511 -- deny execute permission if cache inhibited
512 perm_ok := data(0) and not data(5);
513 end if;
514 end if;
515 rc_ok := data(8) and (data(7) or not r.store);
516 if perm_ok = '1' and rc_ok = '1' then
517 v.state := RADIX_LOAD_TLB;
518 else
519 v.state := RADIX_FINISH;
520 v.perm_err := not perm_ok;
521 -- permission error takes precedence over RC error
522 v.rc_error := perm_ok;
523 end if;
524 """
525 # decode mode into something that matches microwatt equivalent code
526 instr_fetch, store = 0, 0
527 if mode == 'STORE':
528 store = 1
529 if mode == 'EXECUTE':
530 inst_fetch = 1
531
532 # check permissions and RC bits
533 perm_ok = 0
534 if priv == 1 or data[60] == 0:
535 if instr_fetch == 0:
536 perm_ok = data[62] | (data[61] & (store == 0))
537 # no IAMR, so no KUEP support for now
538 # deny execute permission if cache inhibited
539 perm_ok = data[63] & ~data[58]
540 rc_ok = data[55] & (data[56] | (store == 0))
541 if perm_ok == 1 and rc_ok == 1:
542 return True
543
544 return "perm_err" if perm_ok == 0 else "rc_err"
545
546 def _get_prtable_addr(self, shift, prtbl, addr, pid):
547 """
548 if r.addr(63) = '1' then
549 effpid := x"00000000";
550 else
551 effpid := r.pid;
552 end if;
553 x"00" & r.prtbl(55 downto 36) &
554 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
555 (effpid(31 downto 8) and finalmask(23 downto 0))) &
556 effpid(7 downto 0) & "0000";
557 """
558 print ("_get_prtable_addr_", shift, prtbl, addr, pid)
559 finalmask = genmask(shift, 44)
560 finalmask24 = finalmask[20:44]
561 if addr[0].value == 1:
562 effpid = SelectableInt(0, 32)
563 else:
564 effpid = pid #self.pid # TODO, check on this
565 zero16 = SelectableInt(0, 16)
566 zero4 = SelectableInt(0, 4)
567 res = selectconcat(zero16,
568 prtbl[8:28], #
569 (prtbl[28:52] & ~finalmask24) | #
570 (effpid[0:24] & finalmask24), #
571 effpid[24:32],
572 zero4
573 )
574 return res
575
576 def _get_pgtable_addr(self, mask_size, pgbase, addrsh, prtbl):
577 """
578 x"00" & r.pgbase(55 downto 19) &
579 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
580 "000";
581 """
582 mask16 = genmask(mask_size+5, 16)
583 zero8 = SelectableInt(0, 8)
584 zero3 = SelectableInt(0, 3)
585 res = selectconcat(zero8,
586 pgbase[8:45], #
587 (prtbl[45:61] & ~mask16) | #
588 (addrsh & mask16), #
589 zero3
590 )
591 return res
592
593 def _get_pte(self, shift, addr, pde):
594 """
595 x"00" &
596 ((r.pde(55 downto 12) and not finalmask) or
597 (r.addr(55 downto 12) and finalmask))
598 & r.pde(11 downto 0);
599 """
600 finalmask = genmask(shift, 44)
601 zero8 = SelectableInt(0, 8)
602 res = selectconcat(zero8,
603 (pde[8:52] & ~finalmask) | #
604 (addr[8:52] & finalmask), #
605 pde[52:64],
606 )
607 return res
608
609
610 # very quick test of maskgen function (TODO, move to util later)
611 if __name__ == '__main__':
612 # set up dummy minimal ISACaller
613 spr = {'DSISR': SelectableInt(0, 64),
614 'DAR': SelectableInt(0, 64),
615 'PIDR': SelectableInt(0, 64),
616 'PRTBL': SelectableInt(0, 64)
617 }
618 # set problem state == 0 (other unit tests, set to 1)
619 msr = SelectableInt(0, 64)
620 msr[MSRb.PR] = 0
621 class ISACaller: pass
622 caller = ISACaller()
623 caller.spr = spr
624 caller.msr = msr
625
626 shift = SelectableInt(5, 6)
627 mask = genmask(shift, 43)
628 print (" mask", bin(mask.value))
629
630 mem = Mem(row_bytes=8)
631 mem = RADIX(mem, caller)
632 # -----------------------------------------------
633 # |/|RTS1|/| RPDB | RTS2 | RPDS |
634 # -----------------------------------------------
635 # |0|1 2|3|4 55|56 58|59 63|
636 data = SelectableInt(0, 64)
637 data[1:3] = 0b01
638 data[56:59] = 0b11
639 data[59:64] = 0b01101 # mask
640 data[55] = 1
641 (rts, mbits, pgbase) = mem._decode_prte(data)
642 print (" rts", bin(rts.value), rts.bits)
643 print (" mbits", bin(mbits.value), mbits.bits)
644 print (" pgbase", hex(pgbase.value), pgbase.bits)
645 addr = SelectableInt(0x1000, 64)
646 check = mem._segment_check(addr, mbits, shift)
647 print (" segment check", check)
648
649 print("walking tree")
650 addr = SelectableInt(testaddr,64)
651 # pgbase = None
652 mode = None
653 #mbits = None
654 shift = rts
655 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
656 print(" walking tree result", result)