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cleanup imports
[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 from nmigen.back.pysim import Settle
17 from copy import copy
18 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from soc.decoder.helpers import exts, gtu, ltu, undefined
21
22 import math
23 import sys
24
25 # very quick, TODO move to SelectableInt utils later
26 def genmask(shift, size):
27 res = SelectableInt(0, size)
28 for i in range(size):
29 if i < shift:
30 res[size-1-i] = SelectableInt(1, 1)
31 return res
32
33 """
34 Get Root Page
35
36 //Accessing 2nd double word of partition table (pate1)
37 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
38 // PTCR Layout
39 // ====================================================
40 // -----------------------------------------------
41 // | /// | PATB | /// | PATS |
42 // -----------------------------------------------
43 // 0 4 51 52 58 59 63
44 // PATB[4:51] holds the base address of the Partition Table,
45 // right shifted by 12 bits.
46 // This is because the address of the Partition base is
47 // 4k aligned. Hence, the lower 12bits, which are always
48 // 0 are ommitted from the PTCR.
49 //
50 // Thus, The Partition Table Base is obtained by (PATB << 12)
51 //
52 // PATS represents the partition table size right-shifted by 12 bits.
53 // The minimal size of the partition table is 4k.
54 // Thus partition table size = (1 << PATS + 12).
55 //
56 // Partition Table
57 // ====================================================
58 // 0 PATE0 63 PATE1 127
59 // |----------------------|----------------------|
60 // | | |
61 // |----------------------|----------------------|
62 // | | |
63 // |----------------------|----------------------|
64 // | | | <-- effLPID
65 // |----------------------|----------------------|
66 // .
67 // .
68 // .
69 // |----------------------|----------------------|
70 // | | |
71 // |----------------------|----------------------|
72 //
73 // The effective LPID forms the index into the Partition Table.
74 //
75 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
76 // corresponding to that partition.
77 //
78 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
79 //
80 // PATE0 Layout
81 // -----------------------------------------------
82 // |1|RTS1|/| RPDB | RTS2 | RPDS |
83 // -----------------------------------------------
84 // 0 1 2 3 4 55 56 58 59 63
85 //
86 // HR[0] : For Radix Page table, first bit should be 1.
87 // RTS1[1:2] : Gives one fragment of the Radix treesize
88 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
89 // RTS = (RTS1 << 3 + RTS2) + 31.
90 //
91 // RPDB[4:55] = Root Page Directory Base.
92 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
93 // Thus, Root page directory size = 1 << (RPDS + 3).
94 // Note: RPDS >= 5.
95 //
96 // PATE1 Layout
97 // -----------------------------------------------
98 // |///| PRTB | // | PRTS |
99 // -----------------------------------------------
100 // 0 3 4 51 52 58 59 63
101 //
102 // PRTB[4:51] = Process Table Base. This is aligned to size.
103 // PRTS[59: 63] = Process Table Size right shifted by 12.
104 // Minimal size of the process table is 4k.
105 // Process Table Size = (1 << PRTS + 12).
106 // Note: PRTS <= 24.
107 //
108 // Computing the size aligned Process Table Base:
109 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
110 // Thus, the lower 12+PRTS bits of table_base will
111 // be zero.
112
113
114 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
115 //
116 // Process Table
117 // ==========================
118 // 0 PRTE0 63 PRTE1 127
119 // |----------------------|----------------------|
120 // | | |
121 // |----------------------|----------------------|
122 // | | |
123 // |----------------------|----------------------|
124 // | | | <-- effPID
125 // |----------------------|----------------------|
126 // .
127 // .
128 // .
129 // |----------------------|----------------------|
130 // | | |
131 // |----------------------|----------------------|
132 //
133 // The effective Process id (PID) forms the index into the Process Table.
134 //
135 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
136 // corresponding to that process
137 //
138 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
139 //
140 // PRTE0 Layout
141 // -----------------------------------------------
142 // |/|RTS1|/| RPDB | RTS2 | RPDS |
143 // -----------------------------------------------
144 // 0 1 2 3 4 55 56 58 59 63
145 //
146 // RTS1[1:2] : Gives one fragment of the Radix treesize
147 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
148 // RTS = (RTS1 << 3 + RTS2) << 31,
149 // since minimal Radix Tree size is 4G.
150 //
151 // RPDB = Root Page Directory Base.
152 // RPDS = Root Page Directory Size right shifted by 3.
153 // Thus, Root page directory size = RPDS << 3.
154 // Note: RPDS >= 5.
155 //
156 // PRTE1 Layout
157 // -----------------------------------------------
158 // | /// |
159 // -----------------------------------------------
160 // 0 63
161 // All bits are reserved.
162
163
164 """
165
166 # see qemu/target/ppc/mmu-radix64.c for reference
167 class RADIX:
168 def __init__(self, mem, caller):
169 self.mem = mem
170 self.caller = caller
171 self.dsisr = self.caller.spr["DSISR"]
172 self.dar = self.caller.spr["DAR"]
173 self.pidr = self.caller.spr["PIDR"]
174 self.prtbl = self.caller.spr["PRTBL"]
175
176 # cached page table stuff
177 self.pgtbl0 = 0
178 self.pt0_valid = False
179 self.pgtbl3 = 0
180 self.pt3_valid = False
181
182 def __call__(self,*args, **kwargs):
183 print("TODO: implement RADIX.__call__()")
184 print(args)
185 print(kwargs)
186 return None
187
188 def ld(self, address, width=8, swap=True, check_in_mem=False):
189 print("RADIX: ld from addr 0x%x width %d" % (address, width))
190
191 pte = self._walk_tree()
192 # use pte to caclculate phys address
193 return self.mem.ld(address, width, swap, check_in_mem)
194
195 # XXX set SPRs on error
196
197 # TODO implement
198 def st(self, addr, v, width=8, swap=True):
199 print("RADIX: st to addr 0x%x width %d data %x" % (addr, width, v))
200
201 # use pte to caclculate phys address (addr)
202 return self.mem.st(addr, v, width, swap)
203
204 # XXX set SPRs on error
205
206 def memassign(self, addr, sz, val):
207 print("memassign", addr, sz, val)
208 self.st(addr.value, val.value, sz, swap=False)
209
210 def _next_level(self):
211 return True
212 ## DSISR_R_BADCONFIG
213 ## read_entry
214 ## DSISR_NOPTE
215 ## Prepare for next iteration
216
217 def _walk_tree(self):
218 """walk tree
219
220 // vaddr 64 Bit
221 // vaddr |-----------------------------------------------------|
222 // | Unused | Used |
223 // |-----------|-----------------------------------------|
224 // | 0000000 | usefulBits = X bits (typically 52) |
225 // |-----------|-----------------------------------------|
226 // | |<--Cursize---->| |
227 // | | Index | |
228 // | | into Page | |
229 // | | Directory | |
230 // |-----------------------------------------------------|
231 // | |
232 // V |
233 // PDE |---------------------------| |
234 // |V|L|//| NLB |///|NLS| |
235 // |---------------------------| |
236 // PDE = Page Directory Entry |
237 // [0] = V = Valid Bit |
238 // [1] = L = Leaf bit. If 0, then |
239 // [4:55] = NLB = Next Level Base |
240 // right shifted by 8 |
241 // [59:63] = NLS = Next Level Size |
242 // | NLS >= 5 |
243 // | V
244 // | |--------------------------|
245 // | | usfulBits = X-Cursize |
246 // | |--------------------------|
247 // |---------------------><--NLS-->| |
248 // | Index | |
249 // | into | |
250 // | PDE | |
251 // |--------------------------|
252 // |
253 // If the next PDE obtained by |
254 // (NLB << 8 + 8 * index) is a |
255 // nonleaf, then repeat the above. |
256 // |
257 // If the next PDE is a leaf, |
258 // then Leaf PDE structure is as |
259 // follows |
260 // |
261 // |
262 // Leaf PDE |
263 // |------------------------------| |----------------|
264 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
265 // |------------------------------| |----------------|
266 // [0] = V = Valid Bit |
267 // [1] = L = Leaf Bit = 1 if leaf |
268 // PDE |
269 // [2] = Sw = Sw bit 0. |
270 // [7:51] = RPN = Real Page Number, V
271 // real_page = RPN << 12 -------------> Logical OR
272 // [52:54] = Sw Bits 1:3 |
273 // [55] = R = Reference |
274 // [56] = C = Change V
275 // [58:59] = Att = Physical Address
276 // 0b00 = Normal Memory
277 // 0b01 = SAO
278 // 0b10 = Non Idenmpotent
279 // 0b11 = Tolerant I/O
280 // [60:63] = Encoded Access
281 // Authority
282 //
283 """
284 # walk tree starts on prtbl
285 while True:
286 ret = self._next_level()
287 if ret: return ret
288
289 def _decode_prte(self, data):
290 """PRTE0 Layout
291 -----------------------------------------------
292 |/|RTS1|/| RPDB | RTS2 | RPDS |
293 -----------------------------------------------
294 0 1 2 3 4 55 56 58 59 63
295 """
296 # note that SelectableInt does big-endian! so the indices
297 # below *directly* match the spec, unlike microwatt which
298 # has to turn them around (to LE)
299 zero = SelectableInt(0, 1)
300 rts = selectconcat(zero,
301 data[56:59], # RTS2
302 data[1:3], # RTS1
303 )
304 masksize = data[59:64] # RPDS
305 mbits = selectconcat(zero, masksize)
306 pgbase = selectconcat(data[8:56], # part of RPDB
307 SelectableInt(0, 16),)
308
309 return (rts, mbits, pgbase)
310
311 def _segment_check(self, addr, mbits, shift):
312 """checks segment valid
313 mbits := '0' & r.mask_size;
314 v.shift := r.shift + (31 - 12) - mbits;
315 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
316 if r.addr(63) /= r.addr(62) or nonzero = '1' then
317 v.state := RADIX_FINISH;
318 v.segerror := '1';
319 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
320 v.state := RADIX_FINISH;
321 v.badtree := '1';
322 else
323 v.state := RADIX_LOOKUP;
324 """
325 # note that SelectableInt does big-endian! so the indices
326 # below *directly* match the spec, unlike microwatt which
327 # has to turn them around (to LE)
328 mask = genmask(shift, 44)
329 nonzero = addr[1:32] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
330 print ("RADIX _segment_check nonzero", bin(nonzero.value))
331 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
332 if addr[0] != addr[1] or nonzero == 1:
333 return "segerror"
334 limit = shift + (31 - 12)
335 if mbits < 5 or mbits > 16 or mbits > limit:
336 return "badtree"
337 new_shift = shift + (31 - 12) - mbits
338 return new_shift
339
340 def _check_perms(self):
341 """check page permissions
342 -- test leaf bit
343 if data(62) = '1' then
344 -- check permissions and RC bits
345 perm_ok := '0';
346 if r.priv = '1' or data(3) = '0' then
347 if r.iside = '0' then
348 perm_ok := data(1) or (data(2) and not r.store);
349 else
350 -- no IAMR, so no KUEP support for now
351 -- deny execute permission if cache inhibited
352 perm_ok := data(0) and not data(5);
353 end if;
354 end if;
355 rc_ok := data(8) and (data(7) or not r.store);
356 if perm_ok = '1' and rc_ok = '1' then
357 v.state := RADIX_LOAD_TLB;
358 else
359 v.state := RADIX_FINISH;
360 v.perm_err := not perm_ok;
361 -- permission error takes precedence over RC error
362 v.rc_error := perm_ok;
363 end if;
364 """
365
366 def _get_prtable_addr(self, shift, prtbl, addr, pid):
367 """
368 if r.addr(63) = '1' then
369 effpid := x"00000000";
370 else
371 effpid := r.pid;
372 end if;
373 x"00" & r.prtbl(55 downto 36) &
374 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
375 (effpid(31 downto 8) and finalmask(23 downto 0))) &
376 effpid(7 downto 0) & "0000";
377 """
378 finalmask = genmask(shift, 44)
379 finalmask24 = finalmask[20:44]
380 if addr[0].value == 1:
381 effpid = SelectableInt(0, 32)
382 else:
383 effpid = self.pid[32:64] # TODO, check on this
384 zero16 = SelectableInt(0, 16)
385 zero4 = SelectableInt(0, 4)
386 res = selectconcat(zero16,
387 prtbl[8:28], #
388 (prtbl[28:52] & ~finalmask24) | #
389 (effpid[0:24] & finalmask24), #
390 effpid[24:32],
391 zero4
392 )
393 return res
394
395 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
396 """
397 x"00" & r.pgbase(55 downto 19) &
398 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
399 "000";
400 """
401 mask16 = genmask(mask_size+5, 16)
402 zero8 = SelectableInt(0, 8)
403 zero3 = SelectableInt(0, 3)
404 res = selectconcat(zero8,
405 pgbase[8:45], #
406 (prtbl[45:61] & ~mask16) | #
407 (addrsh & mask16), #
408 zero3
409 )
410 return res
411
412 def _get_pte(self, shift, addr, pde):
413 """
414 x"00" &
415 ((r.pde(55 downto 12) and not finalmask) or
416 (r.addr(55 downto 12) and finalmask))
417 & r.pde(11 downto 0);
418 """
419 finalmask = genmask(shift, 44)
420 zero8 = SelectableInt(0, 8)
421 res = selectconcat(zero8,
422 (pde[8:52] & ~finalmask) | #
423 (addr[8:52] & finalmask), #
424 pde[52:64],
425 )
426 return res
427
428
429 # very quick test of maskgen function (TODO, move to util later)
430 if __name__ == '__main__':
431 shift = SelectableInt(5, 6)
432 mask = genmask(shift, 43)
433 print (" mask", bin(mask.value))
434
435 mem = Mem(row_bytes=8)
436 mem = RADIX(mem, None)
437 # -----------------------------------------------
438 # |/|RTS1|/| RPDB | RTS2 | RPDS |
439 # -----------------------------------------------
440 # |0|1 2|3|4 55|56 58|59 63|
441 data = SelectableInt(0, 64)
442 data[1:3] = 0b01
443 data[56:59] = 0b11
444 data[59:64] = 0b01101 # mask
445 data[55] = 1
446 (rts, mbits, pgbase) = mem._decode_prte(data)
447 print (" rts", bin(rts.value), rts.bits)
448 print (" mbits", bin(mbits.value), mbits.bits)
449 print (" pgbase", hex(pgbase.value), pgbase.bits)
450 addr = SelectableInt(0x1000, 64)
451 check = mem._segment_check(addr, mbits, shift)
452 print (" segment check", check)