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code-cleanup in radixmmu
[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 #from nmigen.back.pysim import Settle
17 from copy import copy
18 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from soc.decoder.helpers import exts, gtu, ltu, undefined
21 from soc.decoder.isa.mem import Mem
22 from soc.consts import MSRb # big-endian (PowerISA versions)
23
24 import math
25 import sys
26 import unittest
27
28 # very quick, TODO move to SelectableInt utils later
29 def genmask(shift, size):
30 res = SelectableInt(0, size)
31 for i in range(size):
32 if i < shift:
33 res[size-1-i] = SelectableInt(1, 1)
34 return res
35
36 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
37 # MSB is indexed **LOWEST** (sigh)
38 # from gem5 radixwalk.hh
39 # Bitfield<63> valid; 64 - (63 + 1) = 0
40 # Bitfield<62> leaf; 64 - (62 + 1) = 1
41
42 def rpte_valid(r):
43 return bool(r[0])
44
45 def rpte_leaf(r):
46 return bool(r[1])
47
48 ## Shift address bits 61--12 right by 0--47 bits and
49 ## supply the least significant 16 bits of the result.
50 def addrshift(addr,shift):
51 print("addrshift")
52 print(addr)
53 print(shift)
54 x = addr.value >> shift.value
55 return SelectableInt(x, 16)
56
57 def RTS2(data):
58 return data[56:59]
59
60 def RTS1(data):
61 return data[1:3]
62
63 def RTS(data):
64 zero = SelectableInt(0, 1)
65 return selectconcat(zero, RTS2(data), RTS1(data))
66
67 def NLB(x):
68 """
69 Next Level Base
70 right shifted by 8
71 """
72 return x[4:56] # python numbering end+1
73
74 def NLS(x):
75 """
76 Next Level Size (PATS and RPDS in same bits btw)
77 NLS >= 5
78 """
79 return x[59:64] # python numbering end+1
80
81 def RPDB(x):
82 """
83 Root Page Directory Base
84 power isa docs says 4:55 investigate
85 """
86 return x[8:56] # python numbering end+1
87
88 """
89 Get Root Page
90
91 //Accessing 2nd double word of partition table (pate1)
92 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
93 // PTCR Layout
94 // ====================================================
95 // -----------------------------------------------
96 // | /// | PATB | /// | PATS |
97 // -----------------------------------------------
98 // 0 4 51 52 58 59 63
99 // PATB[4:51] holds the base address of the Partition Table,
100 // right shifted by 12 bits.
101 // This is because the address of the Partition base is
102 // 4k aligned. Hence, the lower 12bits, which are always
103 // 0 are ommitted from the PTCR.
104 //
105 // Thus, The Partition Table Base is obtained by (PATB << 12)
106 //
107 // PATS represents the partition table size right-shifted by 12 bits.
108 // The minimal size of the partition table is 4k.
109 // Thus partition table size = (1 << PATS + 12).
110 //
111 // Partition Table
112 // ====================================================
113 // 0 PATE0 63 PATE1 127
114 // |----------------------|----------------------|
115 // | | |
116 // |----------------------|----------------------|
117 // | | |
118 // |----------------------|----------------------|
119 // | | | <-- effLPID
120 // |----------------------|----------------------|
121 // .
122 // .
123 // .
124 // |----------------------|----------------------|
125 // | | |
126 // |----------------------|----------------------|
127 //
128 // The effective LPID forms the index into the Partition Table.
129 //
130 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
131 // corresponding to that partition.
132 //
133 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
134 //
135 // PATE0 Layout
136 // -----------------------------------------------
137 // |1|RTS1|/| RPDB | RTS2 | RPDS |
138 // -----------------------------------------------
139 // 0 1 2 3 4 55 56 58 59 63
140 //
141 // HR[0] : For Radix Page table, first bit should be 1.
142 // RTS1[1:2] : Gives one fragment of the Radix treesize
143 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
144 // RTS = (RTS1 << 3 + RTS2) + 31.
145 //
146 // RPDB[4:55] = Root Page Directory Base.
147 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
148 // Thus, Root page directory size = 1 << (RPDS + 3).
149 // Note: RPDS >= 5.
150 //
151 // PATE1 Layout
152 // -----------------------------------------------
153 // |///| PRTB | // | PRTS |
154 // -----------------------------------------------
155 // 0 3 4 51 52 58 59 63
156 //
157 // PRTB[4:51] = Process Table Base. This is aligned to size.
158 // PRTS[59: 63] = Process Table Size right shifted by 12.
159 // Minimal size of the process table is 4k.
160 // Process Table Size = (1 << PRTS + 12).
161 // Note: PRTS <= 24.
162 //
163 // Computing the size aligned Process Table Base:
164 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
165 // Thus, the lower 12+PRTS bits of table_base will
166 // be zero.
167
168
169 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
170 //
171 // Process Table
172 // ==========================
173 // 0 PRTE0 63 PRTE1 127
174 // |----------------------|----------------------|
175 // | | |
176 // |----------------------|----------------------|
177 // | | |
178 // |----------------------|----------------------|
179 // | | | <-- effPID
180 // |----------------------|----------------------|
181 // .
182 // .
183 // .
184 // |----------------------|----------------------|
185 // | | |
186 // |----------------------|----------------------|
187 //
188 // The effective Process id (PID) forms the index into the Process Table.
189 //
190 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
191 // corresponding to that process
192 //
193 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
194 //
195 // PRTE0 Layout
196 // -----------------------------------------------
197 // |/|RTS1|/| RPDB | RTS2 | RPDS |
198 // -----------------------------------------------
199 // 0 1 2 3 4 55 56 58 59 63
200 //
201 // RTS1[1:2] : Gives one fragment of the Radix treesize
202 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
203 // RTS = (RTS1 << 3 + RTS2) << 31,
204 // since minimal Radix Tree size is 4G.
205 //
206 // RPDB = Root Page Directory Base.
207 // RPDS = Root Page Directory Size right shifted by 3.
208 // Thus, Root page directory size = RPDS << 3.
209 // Note: RPDS >= 5.
210 //
211 // PRTE1 Layout
212 // -----------------------------------------------
213 // | /// |
214 // -----------------------------------------------
215 // 0 63
216 // All bits are reserved.
217
218
219 """
220
221 testmem = {
222
223 0x10000: # PARTITION_TABLE_2 (not implemented yet)
224 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
225 0x800000000100000b,
226
227 0x30000: # RADIX_ROOT_PTE
228 # V = 1 L = 0 NLB = 0x400 NLS = 9
229 0x8000000000040009,
230 0x40000: # RADIX_SECOND_LEVEL
231 # V = 1 L = 1 SW = 0 RPN = 0
232 # R = 1 C = 1 ATT = 0 EAA 0x7
233 0xc000000000000187,
234
235 0x1000000: # PROCESS_TABLE_3
236 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
237 0x40000000000300ad,
238 }
239
240 # this one has a 2nd level RADIX with a RPN of 0x5000
241 testmem2 = {
242
243 0x10000: # PARTITION_TABLE_2 (not implemented yet)
244 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
245 0x800000000100000b,
246
247 0x30000: # RADIX_ROOT_PTE
248 # V = 1 L = 0 NLB = 0x400 NLS = 9
249 0x8000000000040009,
250 0x40000: # RADIX_SECOND_LEVEL
251 # V = 1 L = 1 SW = 0 RPN = 0x5000
252 # R = 1 C = 1 ATT = 0 EAA 0x7
253 0xc000000005000187,
254
255 0x1000000: # PROCESS_TABLE_3
256 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
257 0x40000000000300ad,
258 }
259
260 testresult = """
261 prtbl = 1000000
262 DCACHE GET 1000000 PROCESS_TABLE_3
263 DCACHE GET 30000 RADIX_ROOT_PTE V = 1 L = 0
264 DCACHE GET 40000 RADIX_SECOND_LEVEL V = 1 L = 1
265 DCACHE GET 10000 PARTITION_TABLE_2
266 translated done 1 err 0 badtree 0 addr 40000 pte 0
267 """
268
269 # see qemu/target/ppc/mmu-radix64.c for reference
270 class RADIX:
271 def __init__(self, mem, caller):
272 self.mem = mem
273 self.caller = caller
274 if caller is not None:
275 print("caller")
276 print(caller)
277 self.dsisr = self.caller.spr["DSISR"]
278 self.dar = self.caller.spr["DAR"]
279 self.pidr = self.caller.spr["PIDR"]
280 self.prtbl = self.caller.spr["PRTBL"]
281 self.msr = self.caller.msr
282
283 # cached page table stuff
284 self.pgtbl0 = 0
285 self.pt0_valid = False
286 self.pgtbl3 = 0
287 self.pt3_valid = False
288
289 def __call__(self, addr, sz):
290 val = self.ld(addr.value, sz, swap=False)
291 print("RADIX memread", addr, sz, val)
292 return SelectableInt(val, sz*8)
293
294 def ld(self, address, width=8, swap=True, check_in_mem=False,
295 instr_fetch=False):
296 print("RADIX: ld from addr 0x%x width %d" % (address, width))
297
298 priv = ~(self.msr[MSRb.PR].value) # problem-state ==> privileged
299 if instr_fetch:
300 mode = 'EXECUTE'
301 else:
302 mode = 'LOAD'
303 addr = SelectableInt(address, 64)
304 pte = self._walk_tree(addr, mode, priv)
305
306 if type(pte)==str:
307 print("error on load",pte)
308 return 0
309
310 # use pte to load from phys address
311 return self.mem.ld(pte.value, width, swap, check_in_mem)
312
313 # XXX set SPRs on error
314
315 # TODO implement
316 def st(self, address, v, width=8, swap=True):
317 print("RADIX: st to addr 0x%x width %d data %x" % (address, width, v))
318
319 priv = ~(self.msr[MSRb.PR].value) # problem-state ==> privileged
320 mode = 'STORE'
321 addr = SelectableInt(address, 64)
322 pte = self._walk_tree(addr, mode, priv)
323
324 # use pte to store at phys address
325 return self.mem.st(pte.value, v, width, swap)
326
327 # XXX set SPRs on error
328
329 def memassign(self, addr, sz, val):
330 print("memassign", addr, sz, val)
331 self.st(addr.value, val.value, sz, swap=False)
332
333 def _next_level(self, addr, entry_width, swap, check_in_mem):
334 # implement read access to mmu mem here
335
336 # DO NOT perform byte-swapping: load 8 bytes (that's the entry size)
337 value = self.mem.ld(addr.value, 8, False, check_in_mem)
338 if value is None:
339 return "address lookup %x not found" % addr.value
340 # assert(value is not None, "address lookup %x not found" % addr.value)
341
342 print("addr", hex(addr.value))
343 data = SelectableInt(value, 64) # convert to SelectableInt
344 print("value", hex(value))
345 # index += 1
346 return data;
347
348 def _walk_tree(self, addr, mode, priv=1):
349 """walk tree
350
351 // vaddr 64 Bit
352 // vaddr |-----------------------------------------------------|
353 // | Unused | Used |
354 // |-----------|-----------------------------------------|
355 // | 0000000 | usefulBits = X bits (typically 52) |
356 // |-----------|-----------------------------------------|
357 // | |<--Cursize---->| |
358 // | | Index | |
359 // | | into Page | |
360 // | | Directory | |
361 // |-----------------------------------------------------|
362 // | |
363 // V |
364 // PDE |---------------------------| |
365 // |V|L|//| NLB |///|NLS| |
366 // |---------------------------| |
367 // PDE = Page Directory Entry |
368 // [0] = V = Valid Bit |
369 // [1] = L = Leaf bit. If 0, then |
370 // [4:55] = NLB = Next Level Base |
371 // right shifted by 8 |
372 // [59:63] = NLS = Next Level Size |
373 // | NLS >= 5 |
374 // | V
375 // | |--------------------------|
376 // | | usfulBits = X-Cursize |
377 // | |--------------------------|
378 // |---------------------><--NLS-->| |
379 // | Index | |
380 // | into | |
381 // | PDE | |
382 // |--------------------------|
383 // |
384 // If the next PDE obtained by |
385 // (NLB << 8 + 8 * index) is a |
386 // nonleaf, then repeat the above. |
387 // |
388 // If the next PDE is a leaf, |
389 // then Leaf PDE structure is as |
390 // follows |
391 // |
392 // |
393 // Leaf PDE |
394 // |------------------------------| |----------------|
395 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
396 // |------------------------------| |----------------|
397 // [0] = V = Valid Bit |
398 // [1] = L = Leaf Bit = 1 if leaf |
399 // PDE |
400 // [2] = Sw = Sw bit 0. |
401 // [7:51] = RPN = Real Page Number, V
402 // real_page = RPN << 12 -------------> Logical OR
403 // [52:54] = Sw Bits 1:3 |
404 // [55] = R = Reference |
405 // [56] = C = Change V
406 // [58:59] = Att = Physical Address
407 // 0b00 = Normal Memory
408 // 0b01 = SAO
409 // 0b10 = Non Idenmpotent
410 // 0b11 = Tolerant I/O
411 // [60:63] = Encoded Access
412 // Authority
413 //
414 """
415 # get sprs
416 print("_walk_tree")
417 pidr = self.caller.spr["PIDR"]
418 prtbl = self.caller.spr["PRTBL"]
419 print(pidr)
420 print(prtbl)
421 p = addr[55:63]
422 print("last 8 bits ----------")
423 print
424
425 # get address of root entry
426 # need to fetch process table entry
427 # v.shift := unsigned('0' & r.prtbl(4 downto 0));
428 shift = selectconcat(SelectableInt(0, 1), NLS(prtbl))
429 addr_next = self._get_prtable_addr(shift, prtbl, addr, pidr)
430 print("starting with prtable, addr_next", addr_next)
431
432 assert(addr_next.bits == 64)
433 #only for first unit tests assert(addr_next.value == 0x1000000)
434
435 # read an entry from prtable, decode PTRE
436 swap = False
437 check_in_mem = False
438 entry_width = 8
439 data = self._next_level(addr_next, entry_width, swap, check_in_mem)
440 print("pr_table", data)
441 pgtbl = data # this is cached in microwatt (as v.pgtbl3 / v.pgtbl0)
442 (rts, mbits, pgbase) = self._decode_prte(pgtbl)
443 print("pgbase", pgbase)
444
445 # WIP
446 if mbits == 0:
447 return "invalid"
448
449 # mask_size := mbits(4 downto 0);
450 mask_size = mbits[0:5]
451 assert(mask_size.bits == 5)
452 print("before segment check ==========")
453 print("mask_size:", bin(mask_size.value))
454 print("mbits:", bin(mbits.value))
455
456 print("calling segment_check")
457
458 mbits = selectconcat(SelectableInt(0,1), mask_size)
459 shift = self._segment_check(addr, mbits, shift)
460 print("shift", shift)
461
462 if isinstance(addr, str):
463 return addr
464 if isinstance(shift, str):
465 return shift
466
467 addrsh = addrshift(addr, shift)
468 print("addrsh",addrsh)
469
470 addr_next = self._get_pgtable_addr(mask_size, pgbase, addrsh)
471 print("DONE addr_next", addr_next)
472
473 # walk tree
474 while True:
475 print("nextlevel----------------------------")
476 # read an entry
477 swap = False
478 check_in_mem = False
479 entry_width = 8
480
481 data = self._next_level(addr_next, entry_width, swap, check_in_mem)
482 valid = rpte_valid(data)
483 leaf = rpte_leaf(data)
484
485 print(" valid, leaf", valid, leaf)
486 if not valid:
487 return "invalid" # TODO: return error
488 if leaf:
489 print ("is leaf, checking perms")
490 ok = self._check_perms(data, priv, mode)
491 if ok == True: # data was ok, found phys address, return it?
492 paddr = self._get_pte(addrsh, addr, data)
493 print (" phys addr", hex(paddr.value))
494 return paddr
495 return ok # return the error code
496 else:
497 newlookup = self._new_lookup(data, shift)
498 if type(newlookup) == str:
499 return newlookup
500 shift, mask, pgbase = newlookup
501 print (" next level", shift, mask, pgbase)
502 shift = SelectableInt(shift.value,16) #THIS is wrong !!!
503 print("calling _get_pgtable_addr")
504 print(mask) #SelectableInt(value=0x9, bits=4)
505 print(pgbase) #SelectableInt(value=0x40000, bits=56)
506 print(shift) #SelectableInt(value=0x4, bits=16) #FIXME
507 pgbase = SelectableInt(pgbase.value, 64)
508 addrsh = addrshift(addr,shift)
509 addr_next = self._get_pgtable_addr(mask, pgbase, addrsh)
510 print("addr_next",addr_next)
511 print("addrsh",addrsh)
512
513 def _get_pgbase(self, data):
514 """
515 v.pgbase := data(55 downto 8) & x"00"; NLB?
516 """
517 zero8 = SelectableInt(0, 8)
518 return selectconcat(zero8, data[8:56], zero8) # shift up 8
519
520 def _new_lookup(self, data, shift):
521 """
522 mbits := unsigned('0' & data(4 downto 0));
523 if mbits < 5 or mbits > 16 or mbits > r.shift then
524 v.state := RADIX_FINISH;
525 v.badtree := '1'; -- throw error
526 else
527 v.shift := v.shift - mbits;
528 v.mask_size := mbits(4 downto 0);
529 v.pgbase := data(55 downto 8) & x"00"; NLB?
530 v.state := RADIX_LOOKUP; --> next level
531 end if;
532 """
533 mbits = selectconcat(SelectableInt(0, 1), NLS(data))
534 print("mbits=", mbits)
535 if mbits < 5 or mbits > 16: #fixme compare with r.shift
536 print("badtree")
537 return "badtree"
538 # reduce shift (has to be done at same bitwidth)
539 shift = shift - mbits
540 assert mbits.bits == 6
541 mask_size = mbits[2:6] # get 4 LSBs from 6-bit (using MSB0 numbering)
542 pgbase = self._get_pgbase(data)
543 return shift, mask_size, pgbase
544
545 def _decode_prte(self, data):
546 """PRTE0 Layout
547 -----------------------------------------------
548 |/|RTS1|/| RPDB | RTS2 | RPDS |
549 -----------------------------------------------
550 0 1 2 3 4 55 56 58 59 63
551 """
552 # note that SelectableInt does big-endian! so the indices
553 # below *directly* match the spec, unlike microwatt which
554 # has to turn them around (to LE)
555 rts, mbits = self._get_rts_nls(data)
556 pgbase = self._get_pgbase(data)
557
558 return (rts, mbits, pgbase)
559
560 def _get_rts_nls(self, data):
561 # rts = shift = unsigned('0' & data(62 downto 61) & data(7 downto 5));
562 # RTS1 RTS2
563 rts = RTS(data)
564 assert(rts.bits == 6) # variable rts : unsigned(5 downto 0);
565 print("shift", rts)
566
567 # mbits := unsigned('0' & data(4 downto 0));
568 mbits = selectconcat(SelectableInt(0, 1), NLS(data))
569 assert(mbits.bits == 6) #variable mbits : unsigned(5 downto 0);
570
571 return rts, mbits
572
573 def _segment_check(self, addr, mbits, shift):
574 """checks segment valid
575 mbits := '0' & r.mask_size;
576 v.shift := r.shift + (31 - 12) - mbits;
577 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
578 if r.addr(63) /= r.addr(62) or nonzero = '1' then
579 v.state := RADIX_FINISH;
580 v.segerror := '1';
581 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
582 v.state := RADIX_FINISH;
583 v.badtree := '1';
584 else
585 v.state := RADIX_LOOKUP;
586 """
587 # note that SelectableInt does big-endian! so the indices
588 # below *directly* match the spec, unlike microwatt which
589 # has to turn them around (to LE)
590 mask = genmask(shift, 44)
591 nonzero = addr[2:33] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
592 print ("RADIX _segment_check nonzero", bin(nonzero.value))
593 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
594 if addr[0] != addr[1] or nonzero != 0:
595 return "segerror"
596 limit = shift + (31 - 12)
597 if mbits.value < 5 or mbits.value > 16 or mbits.value > limit.value:
598 return "badtree"
599 new_shift = shift + (31 - 12) - mbits
600 # TODO verify that returned result is correct
601 return new_shift
602
603 def _check_perms(self, data, priv, mode):
604 """check page permissions
605 // Leaf PDE |
606 // |------------------------------| |----------------|
607 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
608 // |------------------------------| |----------------|
609 // [0] = V = Valid Bit |
610 // [1] = L = Leaf Bit = 1 if leaf |
611 // PDE |
612 // [2] = Sw = Sw bit 0. |
613 // [7:51] = RPN = Real Page Number, V
614 // real_page = RPN << 12 -------------> Logical OR
615 // [52:54] = Sw Bits 1:3 |
616 // [55] = R = Reference |
617 // [56] = C = Change V
618 // [58:59] = Att = Physical Address
619 // 0b00 = Normal Memory
620 // 0b01 = SAO
621 // 0b10 = Non Idenmpotent
622 // 0b11 = Tolerant I/O
623 // [60:63] = Encoded Access
624 // Authority
625 //
626 -- test leaf bit
627 -- check permissions and RC bits
628 perm_ok := '0';
629 if r.priv = '1' or data(3) = '0' then
630 if r.iside = '0' then
631 perm_ok := data(1) or (data(2) and not r.store);
632 else
633 -- no IAMR, so no KUEP support for now
634 -- deny execute permission if cache inhibited
635 perm_ok := data(0) and not data(5);
636 end if;
637 end if;
638 rc_ok := data(8) and (data(7) or not r.store);
639 if perm_ok = '1' and rc_ok = '1' then
640 v.state := RADIX_LOAD_TLB;
641 else
642 v.state := RADIX_FINISH;
643 v.perm_err := not perm_ok;
644 -- permission error takes precedence over RC error
645 v.rc_error := perm_ok;
646 end if;
647 """
648 # decode mode into something that matches microwatt equivalent code
649 instr_fetch, store = 0, 0
650 if mode == 'STORE':
651 store = 1
652 if mode == 'EXECUTE':
653 inst_fetch = 1
654
655 # check permissions and RC bits
656 perm_ok = 0
657 if priv == 1 or data[60] == 0:
658 if instr_fetch == 0:
659 perm_ok = data[62] | (data[61] & (store == 0))
660 # no IAMR, so no KUEP support for now
661 # deny execute permission if cache inhibited
662 perm_ok = data[63] & ~data[58]
663 rc_ok = data[55] & (data[56] | (store == 0))
664 if perm_ok == 1 and rc_ok == 1:
665 return True
666
667 return "perm_err" if perm_ok == 0 else "rc_err"
668
669 def _get_prtable_addr(self, shift, prtbl, addr, pid):
670 """
671 if r.addr(63) = '1' then
672 effpid := x"00000000";
673 else
674 effpid := r.pid;
675 end if;
676 x"00" & r.prtbl(55 downto 36) &
677 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
678 (effpid(31 downto 8) and finalmask(23 downto 0))) &
679 effpid(7 downto 0) & "0000";
680 """
681 print ("_get_prtable_addr", shift, prtbl, addr, pid)
682 finalmask = genmask(shift, 44)
683 finalmask24 = finalmask[20:44]
684 if addr[0].value == 1:
685 effpid = SelectableInt(0, 32)
686 else:
687 effpid = pid #self.pid # TODO, check on this
688 zero8 = SelectableInt(0, 8)
689 zero4 = SelectableInt(0, 4)
690 res = selectconcat(zero8,
691 prtbl[8:28], #
692 (prtbl[28:52] & ~finalmask24) | #
693 (effpid[0:24] & finalmask24), #
694 effpid[24:32],
695 zero4
696 )
697 return res
698
699 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
700 """
701 x"00" & r.pgbase(55 downto 19) &
702 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
703 "000";
704 """
705 mask16 = genmask(mask_size+5, 16)
706 zero8 = SelectableInt(0, 8)
707 zero3 = SelectableInt(0, 3)
708 res = selectconcat(zero8,
709 pgbase[8:45], #
710 (pgbase[45:61] & ~mask16) | #
711 (addrsh & mask16), #
712 zero3
713 )
714 return res
715
716 def _get_pte(self, shift, addr, pde):
717 """
718 x"00" &
719 ((r.pde(55 downto 12) and not finalmask) or
720 (r.addr(55 downto 12) and finalmask))
721 & r.pde(11 downto 0);
722 """
723 shift.value = 12
724 finalmask = genmask(shift, 44)
725 zero8 = SelectableInt(0, 8)
726 rpn = pde[8:52] # RPN = Real Page Number
727 abits = addr[8:52] # non-masked address bits
728 print(" get_pte RPN", hex(rpn.value))
729 print(" abits", hex(abits.value))
730 print(" shift", shift.value)
731 print(" finalmask", bin(finalmask.value))
732 res = selectconcat(zero8,
733 (rpn & ~finalmask) | #
734 (abits & finalmask), #
735 addr[52:64],
736 )
737 return res
738
739
740 class TestRadixMMU(unittest.TestCase):
741
742 def test_genmask(self):
743 shift = SelectableInt(5, 6)
744 mask = genmask(shift, 43)
745 print (" mask", bin(mask.value))
746
747 self.assertEqual(mask.value, 0b11111, "mask should be 5 1s")
748
749 def test_RPDB(self):
750 inp = SelectableInt(0x40000000000300ad, 64)
751
752 rtdb = RPDB(inp)
753 print("rtdb",rtdb,bin(rtdb.value))
754 self.assertEqual(rtdb.value,0x300,"rtdb should be 0x300")
755
756 result = selectconcat(rtdb,SelectableInt(0,8))
757 print("result",result)
758
759 def test_get_pgtable_addr(self):
760
761 mem = None
762 caller = None
763 dut = RADIX(mem, caller)
764
765 mask_size=4
766 pgbase = SelectableInt(0,64)
767 addrsh = SelectableInt(0,16)
768 ret = dut._get_pgtable_addr(mask_size, pgbase, addrsh)
769 print("ret=", ret)
770 self.assertEqual(ret, 0, "pgtbl_addr should be 0")
771
772 def test_walk_tree_1(self):
773
774 # test address as in
775 # https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/radix_walk_example.txt#L65
776 testaddr = 0x1000
777 expected = 0x1000
778
779 # starting prtbl
780 prtbl = 0x1000000
781
782 # set up dummy minimal ISACaller
783 spr = {'DSISR': SelectableInt(0, 64),
784 'DAR': SelectableInt(0, 64),
785 'PIDR': SelectableInt(0, 64),
786 'PRTBL': SelectableInt(prtbl, 64)
787 }
788 # set problem state == 0 (other unit tests, set to 1)
789 msr = SelectableInt(0, 64)
790 msr[MSRb.PR] = 0
791 class ISACaller: pass
792 caller = ISACaller()
793 caller.spr = spr
794 caller.msr = msr
795
796 shift = SelectableInt(5, 6)
797 mask = genmask(shift, 43)
798 print (" mask", bin(mask.value))
799
800 mem = Mem(row_bytes=8, initial_mem=testmem)
801 mem = RADIX(mem, caller)
802 # -----------------------------------------------
803 # |/|RTS1|/| RPDB | RTS2 | RPDS |
804 # -----------------------------------------------
805 # |0|1 2|3|4 55|56 58|59 63|
806 data = SelectableInt(0, 64)
807 data[1:3] = 0b01
808 data[56:59] = 0b11
809 data[59:64] = 0b01101 # mask
810 data[55] = 1
811 (rts, mbits, pgbase) = mem._decode_prte(data)
812 print (" rts", bin(rts.value), rts.bits)
813 print (" mbits", bin(mbits.value), mbits.bits)
814 print (" pgbase", hex(pgbase.value), pgbase.bits)
815 addr = SelectableInt(0x1000, 64)
816 check = mem._segment_check(addr, mbits, shift)
817 print (" segment check", check)
818
819 print("walking tree")
820 addr = SelectableInt(testaddr,64)
821 # pgbase = None
822 mode = None
823 #mbits = None
824 shift = rts
825 result = mem._walk_tree(addr, mode)
826 print(" walking tree result", result)
827 print("should be", testresult)
828 self.assertEqual(result.value, expected,
829 "expected 0x%x got 0x%x" % (expected,
830 result.value))
831
832 def test_walk_tree_2(self):
833
834 # test address slightly different
835 testaddr = 0x1101
836 expected = 0x5001101
837
838 # starting prtbl
839 prtbl = 0x1000000
840
841 # set up dummy minimal ISACaller
842 spr = {'DSISR': SelectableInt(0, 64),
843 'DAR': SelectableInt(0, 64),
844 'PIDR': SelectableInt(0, 64),
845 'PRTBL': SelectableInt(prtbl, 64)
846 }
847 # set problem state == 0 (other unit tests, set to 1)
848 msr = SelectableInt(0, 64)
849 msr[MSRb.PR] = 0
850 class ISACaller: pass
851 caller = ISACaller()
852 caller.spr = spr
853 caller.msr = msr
854
855 shift = SelectableInt(5, 6)
856 mask = genmask(shift, 43)
857 print (" mask", bin(mask.value))
858
859 mem = Mem(row_bytes=8, initial_mem=testmem2)
860 mem = RADIX(mem, caller)
861 # -----------------------------------------------
862 # |/|RTS1|/| RPDB | RTS2 | RPDS |
863 # -----------------------------------------------
864 # |0|1 2|3|4 55|56 58|59 63|
865 data = SelectableInt(0, 64)
866 data[1:3] = 0b01
867 data[56:59] = 0b11
868 data[59:64] = 0b01101 # mask
869 data[55] = 1
870 (rts, mbits, pgbase) = mem._decode_prte(data)
871 print (" rts", bin(rts.value), rts.bits)
872 print (" mbits", bin(mbits.value), mbits.bits)
873 print (" pgbase", hex(pgbase.value), pgbase.bits)
874 addr = SelectableInt(0x1000, 64)
875 check = mem._segment_check(addr, mbits, shift)
876 print (" segment check", check)
877
878 print("walking tree")
879 addr = SelectableInt(testaddr,64)
880 # pgbase = None
881 mode = None
882 #mbits = None
883 shift = rts
884 result = mem._walk_tree(addr, mode)
885 print(" walking tree result", result)
886 print("should be", testresult)
887 self.assertEqual(result.value, expected,
888 "expected 0x%x got 0x%x" % (expected,
889 result.value))
890
891
892 if __name__ == '__main__':
893 unittest.main()