1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
16 from nmigen
.back
.pysim
import Settle
18 from soc
.decoder
.selectable_int
import (FieldSelectableInt
, SelectableInt
,
20 from soc
.decoder
.helpers
import exts
, gtu
, ltu
, undefined
21 from soc
.decoder
.isa
.mem
import Mem
26 # very quick, TODO move to SelectableInt utils later
27 def genmask(shift
, size
):
28 res
= SelectableInt(0, size
)
31 res
[size
-1-i
] = SelectableInt(1, 1)
34 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
35 # MSB is indexed **LOWEST** (sigh)
36 # from gem5 radixwalk.hh
37 # Bitfield<63> valid; 64 - (63 + 1) = 0
38 # Bitfield<62> leaf; 64 - (62 + 1) = 1
49 //Accessing 2nd double word of partition table (pate1)
50 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
52 // ====================================================
53 // -----------------------------------------------
54 // | /// | PATB | /// | PATS |
55 // -----------------------------------------------
57 // PATB[4:51] holds the base address of the Partition Table,
58 // right shifted by 12 bits.
59 // This is because the address of the Partition base is
60 // 4k aligned. Hence, the lower 12bits, which are always
61 // 0 are ommitted from the PTCR.
63 // Thus, The Partition Table Base is obtained by (PATB << 12)
65 // PATS represents the partition table size right-shifted by 12 bits.
66 // The minimal size of the partition table is 4k.
67 // Thus partition table size = (1 << PATS + 12).
70 // ====================================================
71 // 0 PATE0 63 PATE1 127
72 // |----------------------|----------------------|
74 // |----------------------|----------------------|
76 // |----------------------|----------------------|
78 // |----------------------|----------------------|
82 // |----------------------|----------------------|
84 // |----------------------|----------------------|
86 // The effective LPID forms the index into the Partition Table.
88 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
89 // corresponding to that partition.
91 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
94 // -----------------------------------------------
95 // |1|RTS1|/| RPDB | RTS2 | RPDS |
96 // -----------------------------------------------
97 // 0 1 2 3 4 55 56 58 59 63
99 // HR[0] : For Radix Page table, first bit should be 1.
100 // RTS1[1:2] : Gives one fragment of the Radix treesize
101 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
102 // RTS = (RTS1 << 3 + RTS2) + 31.
104 // RPDB[4:55] = Root Page Directory Base.
105 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
106 // Thus, Root page directory size = 1 << (RPDS + 3).
110 // -----------------------------------------------
111 // |///| PRTB | // | PRTS |
112 // -----------------------------------------------
113 // 0 3 4 51 52 58 59 63
115 // PRTB[4:51] = Process Table Base. This is aligned to size.
116 // PRTS[59: 63] = Process Table Size right shifted by 12.
117 // Minimal size of the process table is 4k.
118 // Process Table Size = (1 << PRTS + 12).
121 // Computing the size aligned Process Table Base:
122 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
123 // Thus, the lower 12+PRTS bits of table_base will
127 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
130 // ==========================
131 // 0 PRTE0 63 PRTE1 127
132 // |----------------------|----------------------|
134 // |----------------------|----------------------|
136 // |----------------------|----------------------|
138 // |----------------------|----------------------|
142 // |----------------------|----------------------|
144 // |----------------------|----------------------|
146 // The effective Process id (PID) forms the index into the Process Table.
148 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
149 // corresponding to that process
151 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
154 // -----------------------------------------------
155 // |/|RTS1|/| RPDB | RTS2 | RPDS |
156 // -----------------------------------------------
157 // 0 1 2 3 4 55 56 58 59 63
159 // RTS1[1:2] : Gives one fragment of the Radix treesize
160 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
161 // RTS = (RTS1 << 3 + RTS2) << 31,
162 // since minimal Radix Tree size is 4G.
164 // RPDB = Root Page Directory Base.
165 // RPDS = Root Page Directory Size right shifted by 3.
166 // Thus, Root page directory size = RPDS << 3.
170 // -----------------------------------------------
172 // -----------------------------------------------
174 // All bits are reserved.
179 # see qemu/target/ppc/mmu-radix64.c for reference
181 def __init__(self
, mem
, caller
):
185 self
.dsisr
= self
.caller
.spr
["DSISR"]
186 self
.dar
= self
.caller
.spr
["DAR"]
187 self
.pidr
= self
.caller
.spr
["PIDR"]
188 self
.prtbl
= self
.caller
.spr
["PRTBL"]
190 # cached page table stuff
192 self
.pt0_valid
= False
194 self
.pt3_valid
= False
196 def __call__(self
, addr
, sz
):
197 val
= self
.ld(addr
.value
, sz
, swap
=False)
198 print("RADIX memread", addr
, sz
, val
)
199 return SelectableInt(val
, sz
*8)
201 def ld(self
, address
, width
=8, swap
=True, check_in_mem
=False):
202 print("RADIX: ld from addr 0x%x width %d" % (address
, width
))
204 mode
= 'LOAD' # XXX TODO: executable load (icache)
205 addr
= SelectableInt(address
, 64)
206 (shift
, mbits
, pgbase
) = self
._decode
_prte
(addr
)
207 #shift = SelectableInt(0, 32)
209 pte
= self
._walk
_tree
(addr
, pgbase
, mode
, mbits
, shift
)
210 # use pte to caclculate phys address
211 return self
.mem
.ld(address
, width
, swap
, check_in_mem
)
213 # XXX set SPRs on error
216 def st(self
, address
, v
, width
=8, swap
=True):
217 print("RADIX: st to addr 0x%x width %d data %x" % (address
, width
, v
))
220 addr
= SelectableInt(address
, 64)
221 (shift
, mbits
, pgbase
) = self
._decode
_prte
(addr
)
222 pte
= self
._walk
_tree
(addr
, pgbase
, mode
, mbits
, shift
)
224 # use pte to caclculate phys address (addr)
225 return self
.mem
.st(addr
.value
, v
, width
, swap
)
227 # XXX set SPRs on error
229 def memassign(self
, addr
, sz
, val
):
230 print("memassign", addr
, sz
, val
)
231 self
.st(addr
.value
, val
.value
, sz
, swap
=False)
233 def _next_level(self
,r
):
234 return rpte_valid(r
), rpte_leaf(r
)
238 ## Prepare for next iteration
240 def _walk_tree(self
, addr
, pgbase
, mode
, mbits
, shift
):
244 // vaddr |-----------------------------------------------------|
246 // |-----------|-----------------------------------------|
247 // | 0000000 | usefulBits = X bits (typically 52) |
248 // |-----------|-----------------------------------------|
249 // | |<--Cursize---->| |
253 // |-----------------------------------------------------|
256 // PDE |---------------------------| |
257 // |V|L|//| NLB |///|NLS| |
258 // |---------------------------| |
259 // PDE = Page Directory Entry |
260 // [0] = V = Valid Bit |
261 // [1] = L = Leaf bit. If 0, then |
262 // [4:55] = NLB = Next Level Base |
263 // right shifted by 8 |
264 // [59:63] = NLS = Next Level Size |
267 // | |--------------------------|
268 // | | usfulBits = X-Cursize |
269 // | |--------------------------|
270 // |---------------------><--NLS-->| |
274 // |--------------------------|
276 // If the next PDE obtained by |
277 // (NLB << 8 + 8 * index) is a |
278 // nonleaf, then repeat the above. |
280 // If the next PDE is a leaf, |
281 // then Leaf PDE structure is as |
286 // |------------------------------| |----------------|
287 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
288 // |------------------------------| |----------------|
289 // [0] = V = Valid Bit |
290 // [1] = L = Leaf Bit = 1 if leaf |
292 // [2] = Sw = Sw bit 0. |
293 // [7:51] = RPN = Real Page Number, V
294 // real_page = RPN << 12 -------------> Logical OR
295 // [52:54] = Sw Bits 1:3 |
296 // [55] = R = Reference |
297 // [56] = C = Change V
298 // [58:59] = Att = Physical Address
299 // 0b00 = Normal Memory
301 // 0b10 = Non Idenmpotent
302 // 0b11 = Tolerant I/O
303 // [60:63] = Encoded Access
309 pidr
= self
.caller
.spr
["PIDR"]
310 prtbl
= self
.caller
.spr
["PRTBL"]
314 # get address of root entry
315 prtable_addr
= self
._get
_prtable
_addr
(shift
, prtbl
, addr
, pidr
)
316 print("prtable_addr",prtable_addr
)
318 # read root entry - imcomplete
322 value
= self
.mem
.ld(prtable_addr
.value
, entry_width
, swap
, check_in_mem
)
326 SelectableInt(0x8000000000000000, 64), #valid
327 SelectableInt(0xc000000000000000, 64) #exit
331 # walk tree starts on prtbl
333 print("nextlevel----------------------------")
334 l
= test_input
[index
]
336 valid
,leaf
= self
._next
_level
(l
)
339 if not valid
: return None
342 def _decode_prte(self
, data
):
344 -----------------------------------------------
345 |/|RTS1|/| RPDB | RTS2 | RPDS |
346 -----------------------------------------------
347 0 1 2 3 4 55 56 58 59 63
349 # note that SelectableInt does big-endian! so the indices
350 # below *directly* match the spec, unlike microwatt which
351 # has to turn them around (to LE)
352 zero
= SelectableInt(0, 1)
353 rts
= selectconcat(zero
,
357 masksize
= data
[59:64] # RPDS
358 mbits
= selectconcat(zero
, masksize
)
359 pgbase
= selectconcat(data
[8:56], # part of RPDB
360 SelectableInt(0, 16),)
362 return (rts
, mbits
, pgbase
)
364 def _segment_check(self
, addr
, mbits
, shift
):
365 """checks segment valid
366 mbits := '0' & r.mask_size;
367 v.shift := r.shift + (31 - 12) - mbits;
368 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
369 if r.addr(63) /= r.addr(62) or nonzero = '1' then
370 v.state := RADIX_FINISH;
372 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
373 v.state := RADIX_FINISH;
376 v.state := RADIX_LOOKUP;
378 # note that SelectableInt does big-endian! so the indices
379 # below *directly* match the spec, unlike microwatt which
380 # has to turn them around (to LE)
381 mask
= genmask(shift
, 44)
382 nonzero
= addr
[1:32] & mask
[13:44] # mask 31 LSBs (BE numbered 13:44)
383 print ("RADIX _segment_check nonzero", bin(nonzero
.value
))
384 print ("RADIX _segment_check addr[0-1]", addr
[0].value
, addr
[1].value
)
385 if addr
[0] != addr
[1] or nonzero
== 1:
387 limit
= shift
+ (31 - 12)
388 if mbits
< 5 or mbits
> 16 or mbits
> limit
:
390 new_shift
= shift
+ (31 - 12) - mbits
393 def _check_perms(self
, data
, priv
, iside
, store
):
394 """check page permissions
396 // |------------------------------| |----------------|
397 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
398 // |------------------------------| |----------------|
399 // [0] = V = Valid Bit |
400 // [1] = L = Leaf Bit = 1 if leaf |
402 // [2] = Sw = Sw bit 0. |
403 // [7:51] = RPN = Real Page Number, V
404 // real_page = RPN << 12 -------------> Logical OR
405 // [52:54] = Sw Bits 1:3 |
406 // [55] = R = Reference |
407 // [56] = C = Change V
408 // [58:59] = Att = Physical Address
409 // 0b00 = Normal Memory
411 // 0b10 = Non Idenmpotent
412 // 0b11 = Tolerant I/O
413 // [60:63] = Encoded Access
417 -- check permissions and RC bits
419 if r.priv = '1' or data(3) = '0' then
420 if r.iside = '0' then
421 perm_ok := data(1) or (data(2) and not r.store);
423 -- no IAMR, so no KUEP support for now
424 -- deny execute permission if cache inhibited
425 perm_ok := data(0) and not data(5);
428 rc_ok := data(8) and (data(7) or not r.store);
429 if perm_ok = '1' and rc_ok = '1' then
430 v.state := RADIX_LOAD_TLB;
432 v.state := RADIX_FINISH;
433 v.perm_err := not perm_ok;
434 -- permission error takes precedence over RC error
435 v.rc_error := perm_ok;
438 # check permissions and RC bits
440 if priv
== 1 or data
[60] == 0:
442 perm_ok
= data
[62] |
(data
[61] & (store
== 0))
443 # no IAMR, so no KUEP support for now
444 # deny execute permission if cache inhibited
445 perm_ok
= data
[63] & ~data
[58]
446 rc_ok
= data
[55] & (data
[56] |
(store
== 0))
447 if perm_ok
== 1 and rc_ok
== 1:
449 return "perm_err" if perm_ok
== 0 else "rc_err"
451 def _get_prtable_addr(self
, shift
, prtbl
, addr
, pid
):
453 if r.addr(63) = '1' then
454 effpid := x"00000000";
458 x"00" & r.prtbl(55 downto 36) &
459 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
460 (effpid(31 downto 8) and finalmask(23 downto 0))) &
461 effpid(7 downto 0) & "0000";
463 print ("_get_prtable_addr_", shift
, prtbl
, addr
, pid
)
464 finalmask
= genmask(shift
, 44)
465 finalmask24
= finalmask
[20:44]
466 if addr
[0].value
== 1:
467 effpid
= SelectableInt(0, 32)
469 effpid
= pid
#self.pid # TODO, check on this
470 zero16
= SelectableInt(0, 16)
471 zero4
= SelectableInt(0, 4)
472 res
= selectconcat(zero16
,
474 (prtbl
[28:52] & ~finalmask24
) |
#
475 (effpid
[0:24] & finalmask24
), #
481 def _get_pgtable_addr(self
, mask_size
, pgbase
, addrsh
):
483 x"00" & r.pgbase(55 downto 19) &
484 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
487 mask16
= genmask(mask_size
+5, 16)
488 zero8
= SelectableInt(0, 8)
489 zero3
= SelectableInt(0, 3)
490 res
= selectconcat(zero8
,
492 (prtbl
[45:61] & ~mask16
) |
#
498 def _get_pte(self
, shift
, addr
, pde
):
501 ((r.pde(55 downto 12) and not finalmask) or
502 (r.addr(55 downto 12) and finalmask))
503 & r.pde(11 downto 0);
505 finalmask
= genmask(shift
, 44)
506 zero8
= SelectableInt(0, 8)
507 res
= selectconcat(zero8
,
508 (pde
[8:52] & ~finalmask
) |
#
509 (addr
[8:52] & finalmask
), #
515 # very quick test of maskgen function (TODO, move to util later)
516 if __name__
== '__main__':
517 # set up dummy minimal ISACaller
518 spr
= {'DSISR': SelectableInt(0, 64),
519 'DAR': SelectableInt(0, 64),
520 'PIDR': SelectableInt(0, 64),
521 'PRTBL': SelectableInt(0, 64)
523 class ISACaller
: pass
527 shift
= SelectableInt(5, 6)
528 mask
= genmask(shift
, 43)
529 print (" mask", bin(mask
.value
))
531 mem
= Mem(row_bytes
=8)
532 mem
= RADIX(mem
, caller
)
533 # -----------------------------------------------
534 # |/|RTS1|/| RPDB | RTS2 | RPDS |
535 # -----------------------------------------------
536 # |0|1 2|3|4 55|56 58|59 63|
537 data
= SelectableInt(0, 64)
540 data
[59:64] = 0b01101 # mask
542 (rts
, mbits
, pgbase
) = mem
._decode
_prte
(data
)
543 print (" rts", bin(rts
.value
), rts
.bits
)
544 print (" mbits", bin(mbits
.value
), mbits
.bits
)
545 print (" pgbase", hex(pgbase
.value
), pgbase
.bits
)
546 addr
= SelectableInt(0x1000, 64)
547 check
= mem
._segment
_check
(addr
, mbits
, shift
)
548 print (" segment check", check
)
550 print("walking tree")
556 result
= mem
._walk
_tree
(addr
, pgbase
, mode
, mbits
, shift
)