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move radixmmu to unit test format
[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 from nmigen.back.pysim import Settle
17 from copy import copy
18 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from soc.decoder.helpers import exts, gtu, ltu, undefined
21 from soc.decoder.isa.mem import Mem
22 from soc.consts import MSRb # big-endian (PowerISA versions)
23
24 import math
25 import sys
26 import unittest
27
28 # very quick, TODO move to SelectableInt utils later
29 def genmask(shift, size):
30 res = SelectableInt(0, size)
31 for i in range(size):
32 if i < shift:
33 res[size-1-i] = SelectableInt(1, 1)
34 return res
35
36 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
37 # MSB is indexed **LOWEST** (sigh)
38 # from gem5 radixwalk.hh
39 # Bitfield<63> valid; 64 - (63 + 1) = 0
40 # Bitfield<62> leaf; 64 - (62 + 1) = 1
41
42 def rpte_valid(r):
43 return bool(r[0])
44
45 def rpte_leaf(r):
46 return bool(r[1])
47
48 def NLB(x):
49 """
50 Next Level Base
51 right shifted by 8
52 """
53 return x[4:55]
54
55 def NLS(x):
56 """
57 Next Level Size
58 NLS >= 5
59 """
60 return x[59:63]
61
62 """
63 Get Root Page
64
65 //Accessing 2nd double word of partition table (pate1)
66 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
67 // PTCR Layout
68 // ====================================================
69 // -----------------------------------------------
70 // | /// | PATB | /// | PATS |
71 // -----------------------------------------------
72 // 0 4 51 52 58 59 63
73 // PATB[4:51] holds the base address of the Partition Table,
74 // right shifted by 12 bits.
75 // This is because the address of the Partition base is
76 // 4k aligned. Hence, the lower 12bits, which are always
77 // 0 are ommitted from the PTCR.
78 //
79 // Thus, The Partition Table Base is obtained by (PATB << 12)
80 //
81 // PATS represents the partition table size right-shifted by 12 bits.
82 // The minimal size of the partition table is 4k.
83 // Thus partition table size = (1 << PATS + 12).
84 //
85 // Partition Table
86 // ====================================================
87 // 0 PATE0 63 PATE1 127
88 // |----------------------|----------------------|
89 // | | |
90 // |----------------------|----------------------|
91 // | | |
92 // |----------------------|----------------------|
93 // | | | <-- effLPID
94 // |----------------------|----------------------|
95 // .
96 // .
97 // .
98 // |----------------------|----------------------|
99 // | | |
100 // |----------------------|----------------------|
101 //
102 // The effective LPID forms the index into the Partition Table.
103 //
104 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
105 // corresponding to that partition.
106 //
107 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
108 //
109 // PATE0 Layout
110 // -----------------------------------------------
111 // |1|RTS1|/| RPDB | RTS2 | RPDS |
112 // -----------------------------------------------
113 // 0 1 2 3 4 55 56 58 59 63
114 //
115 // HR[0] : For Radix Page table, first bit should be 1.
116 // RTS1[1:2] : Gives one fragment of the Radix treesize
117 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
118 // RTS = (RTS1 << 3 + RTS2) + 31.
119 //
120 // RPDB[4:55] = Root Page Directory Base.
121 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
122 // Thus, Root page directory size = 1 << (RPDS + 3).
123 // Note: RPDS >= 5.
124 //
125 // PATE1 Layout
126 // -----------------------------------------------
127 // |///| PRTB | // | PRTS |
128 // -----------------------------------------------
129 // 0 3 4 51 52 58 59 63
130 //
131 // PRTB[4:51] = Process Table Base. This is aligned to size.
132 // PRTS[59: 63] = Process Table Size right shifted by 12.
133 // Minimal size of the process table is 4k.
134 // Process Table Size = (1 << PRTS + 12).
135 // Note: PRTS <= 24.
136 //
137 // Computing the size aligned Process Table Base:
138 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
139 // Thus, the lower 12+PRTS bits of table_base will
140 // be zero.
141
142
143 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
144 //
145 // Process Table
146 // ==========================
147 // 0 PRTE0 63 PRTE1 127
148 // |----------------------|----------------------|
149 // | | |
150 // |----------------------|----------------------|
151 // | | |
152 // |----------------------|----------------------|
153 // | | | <-- effPID
154 // |----------------------|----------------------|
155 // .
156 // .
157 // .
158 // |----------------------|----------------------|
159 // | | |
160 // |----------------------|----------------------|
161 //
162 // The effective Process id (PID) forms the index into the Process Table.
163 //
164 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
165 // corresponding to that process
166 //
167 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
168 //
169 // PRTE0 Layout
170 // -----------------------------------------------
171 // |/|RTS1|/| RPDB | RTS2 | RPDS |
172 // -----------------------------------------------
173 // 0 1 2 3 4 55 56 58 59 63
174 //
175 // RTS1[1:2] : Gives one fragment of the Radix treesize
176 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
177 // RTS = (RTS1 << 3 + RTS2) << 31,
178 // since minimal Radix Tree size is 4G.
179 //
180 // RPDB = Root Page Directory Base.
181 // RPDS = Root Page Directory Size right shifted by 3.
182 // Thus, Root page directory size = RPDS << 3.
183 // Note: RPDS >= 5.
184 //
185 // PRTE1 Layout
186 // -----------------------------------------------
187 // | /// |
188 // -----------------------------------------------
189 // 0 63
190 // All bits are reserved.
191
192
193 """
194
195 testaddr = 0x10000
196 testmem = {
197
198 0x10000: # PARTITION_TABLE_2 (not implemented yet)
199 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
200 0x800000000100000b,
201
202 0x30000: # RADIX_ROOT_PTE
203 # V = 1 L = 0 NLB = 0x400 NLS = 9
204 0x8000000000040009,
205 ######## 0x4000000 #### wrong address calculated by _get_pgtable_addr
206 0x40000: # RADIX_SECOND_LEVEL
207 # V = 1 L = 1 SW = 0 RPN = 0
208 # R = 1 C = 1 ATT = 0 EAA 0x7
209 0xc000000000000187,
210
211 0x1000000: # PROCESS_TABLE_3
212 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
213 0x40000000000300ad,
214 }
215
216
217
218 # see qemu/target/ppc/mmu-radix64.c for reference
219 class RADIX:
220 def __init__(self, mem, caller):
221 self.mem = mem
222 self.caller = caller
223 #TODO move to lookup
224 self.dsisr = self.caller.spr["DSISR"]
225 self.dar = self.caller.spr["DAR"]
226 self.pidr = self.caller.spr["PIDR"]
227 self.prtbl = self.caller.spr["PRTBL"]
228 self.msr = self.caller.msr
229
230 # cached page table stuff
231 self.pgtbl0 = 0
232 self.pt0_valid = False
233 self.pgtbl3 = 0
234 self.pt3_valid = False
235
236 def __call__(self, addr, sz):
237 val = self.ld(addr.value, sz, swap=False)
238 print("RADIX memread", addr, sz, val)
239 return SelectableInt(val, sz*8)
240
241 def ld(self, address, width=8, swap=True, check_in_mem=False,
242 instr_fetch=False):
243 print("RADIX: ld from addr 0x%x width %d" % (address, width))
244
245 priv = ~(self.msr(MSR_PR).value) # problem-state ==> privileged
246 if instr_fetch:
247 mode = 'EXECUTE'
248 else:
249 mode = 'LOAD'
250 addr = SelectableInt(address, 64)
251 (shift, mbits, pgbase) = self._decode_prte(addr)
252 #shift = SelectableInt(0, 32)
253
254 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
255 # use pte to caclculate phys address
256 return self.mem.ld(address, width, swap, check_in_mem)
257
258 # XXX set SPRs on error
259
260 # TODO implement
261 def st(self, address, v, width=8, swap=True):
262 print("RADIX: st to addr 0x%x width %d data %x" % (address, width, v))
263
264 priv = ~(self.msr(MSR_PR).value) # problem-state ==> privileged
265 mode = 'STORE'
266 addr = SelectableInt(address, 64)
267 (shift, mbits, pgbase) = self._decode_prte(addr)
268 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
269
270 # use pte to caclculate phys address (addr)
271 return self.mem.st(addr.value, v, width, swap)
272
273 # XXX set SPRs on error
274
275 def memassign(self, addr, sz, val):
276 print("memassign", addr, sz, val)
277 self.st(addr.value, val.value, sz, swap=False)
278
279 def _next_level(self, addr, entry_width, swap, check_in_mem):
280 # implement read access to mmu mem here
281
282 value = 0
283 if addr.value in testmem:
284 value = testmem[addr.value]
285 else:
286 print("not found")
287
288 ##value = self.mem.ld(addr.value, entry_width, swap, check_in_mem)
289 print("addr", hex(addr.value))
290 data = SelectableInt(value, 64) # convert to SelectableInt
291 print("value", hex(value))
292 # index += 1
293 return data;
294
295 def _walk_tree(self, addr, pgbase, mode, mbits, shift, priv=1):
296 """walk tree
297
298 // vaddr 64 Bit
299 // vaddr |-----------------------------------------------------|
300 // | Unused | Used |
301 // |-----------|-----------------------------------------|
302 // | 0000000 | usefulBits = X bits (typically 52) |
303 // |-----------|-----------------------------------------|
304 // | |<--Cursize---->| |
305 // | | Index | |
306 // | | into Page | |
307 // | | Directory | |
308 // |-----------------------------------------------------|
309 // | |
310 // V |
311 // PDE |---------------------------| |
312 // |V|L|//| NLB |///|NLS| |
313 // |---------------------------| |
314 // PDE = Page Directory Entry |
315 // [0] = V = Valid Bit |
316 // [1] = L = Leaf bit. If 0, then |
317 // [4:55] = NLB = Next Level Base |
318 // right shifted by 8 |
319 // [59:63] = NLS = Next Level Size |
320 // | NLS >= 5 |
321 // | V
322 // | |--------------------------|
323 // | | usfulBits = X-Cursize |
324 // | |--------------------------|
325 // |---------------------><--NLS-->| |
326 // | Index | |
327 // | into | |
328 // | PDE | |
329 // |--------------------------|
330 // |
331 // If the next PDE obtained by |
332 // (NLB << 8 + 8 * index) is a |
333 // nonleaf, then repeat the above. |
334 // |
335 // If the next PDE is a leaf, |
336 // then Leaf PDE structure is as |
337 // follows |
338 // |
339 // |
340 // Leaf PDE |
341 // |------------------------------| |----------------|
342 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
343 // |------------------------------| |----------------|
344 // [0] = V = Valid Bit |
345 // [1] = L = Leaf Bit = 1 if leaf |
346 // PDE |
347 // [2] = Sw = Sw bit 0. |
348 // [7:51] = RPN = Real Page Number, V
349 // real_page = RPN << 12 -------------> Logical OR
350 // [52:54] = Sw Bits 1:3 |
351 // [55] = R = Reference |
352 // [56] = C = Change V
353 // [58:59] = Att = Physical Address
354 // 0b00 = Normal Memory
355 // 0b01 = SAO
356 // 0b10 = Non Idenmpotent
357 // 0b11 = Tolerant I/O
358 // [60:63] = Encoded Access
359 // Authority
360 //
361 """
362 # get sprs
363 print("_walk_tree")
364 pidr = self.caller.spr["PIDR"]
365 prtbl = self.caller.spr["PRTBL"]
366 print(pidr)
367 print(prtbl)
368 p = addr[55:63]
369 print("last 8 bits ----------")
370 print
371
372 # get address of root entry
373 addr_next = self._get_prtable_addr(shift, prtbl, addr, pidr)
374
375 addr_next = SelectableInt(0x30000,64) # radix root for testing
376
377 # walk tree starts on prtbl
378 while True:
379 print("nextlevel----------------------------")
380 # read an entry
381 swap = False
382 check_in_mem = False
383 entry_width = 8
384
385 data = self._next_level(addr_next, entry_width, swap, check_in_mem)
386 valid = rpte_valid(data)
387 leaf = rpte_leaf(data)
388
389 print(" valid, leaf", valid, leaf)
390 if not valid:
391 return "invalid" # TODO: return error
392 if leaf:
393 ok = self._check_perms(data, priv, mode)
394 if ok == True: # data was ok, found phys address, return it?
395 return addr_next
396 return ok # return the error code
397 else:
398 newlookup = self._new_lookup(data, mbits, shift)
399 if newlookup == 'badtree':
400 return newlookup
401 shift, mask, pgbase = newlookup
402 print (" next level", shift, mask, pgbase)
403 shift = SelectableInt(shift.value,16) #FIXME
404 addr_next = self._get_pgtable_addr(mask, pgbase, shift, prtbl)
405
406 def _new_lookup(self, data, mbits, shift):
407 """
408 mbits := unsigned('0' & data(4 downto 0));
409 if mbits < 5 or mbits > 16 or mbits > r.shift then
410 v.state := RADIX_FINISH;
411 v.badtree := '1'; -- throw error
412 else
413 v.shift := v.shift - mbits;
414 v.mask_size := mbits(4 downto 0);
415 v.pgbase := data(55 downto 8) & x"00"; NLB?
416 v.state := RADIX_LOOKUP; --> next level
417 end if;
418 """
419 mbits = data[59:64]
420 print("mbits=", mbits)
421 if mbits < 5 or mbits > 16: #fixme compare with r.shift
422 print("badtree")
423 return "badtree"
424 # reduce shift (has to be done at same bitwidth)
425 shift = shift - selectconcat(SelectableInt(0, 1), mbits)
426 mask_size = mbits[1:5] # get 4 LSBs
427 pgbase = selectconcat(data[8:56], SelectableInt(0, 8)) # shift up 8
428 return shift, mask_size, pgbase
429
430 def _decode_prte(self, data):
431 """PRTE0 Layout
432 -----------------------------------------------
433 |/|RTS1|/| RPDB | RTS2 | RPDS |
434 -----------------------------------------------
435 0 1 2 3 4 55 56 58 59 63
436 """
437 # note that SelectableInt does big-endian! so the indices
438 # below *directly* match the spec, unlike microwatt which
439 # has to turn them around (to LE)
440 zero = SelectableInt(0, 1)
441 rts = selectconcat(zero,
442 data[56:59], # RTS2
443 data[1:3], # RTS1
444 )
445 masksize = data[59:64] # RPDS
446 mbits = selectconcat(zero, masksize)
447 pgbase = selectconcat(data[8:56], # part of RPDB
448 SelectableInt(0, 16),)
449
450 return (rts, mbits, pgbase)
451
452 def _segment_check(self, addr, mbits, shift):
453 """checks segment valid
454 mbits := '0' & r.mask_size;
455 v.shift := r.shift + (31 - 12) - mbits;
456 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
457 if r.addr(63) /= r.addr(62) or nonzero = '1' then
458 v.state := RADIX_FINISH;
459 v.segerror := '1';
460 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
461 v.state := RADIX_FINISH;
462 v.badtree := '1';
463 else
464 v.state := RADIX_LOOKUP;
465 """
466 # note that SelectableInt does big-endian! so the indices
467 # below *directly* match the spec, unlike microwatt which
468 # has to turn them around (to LE)
469 mask = genmask(shift, 44)
470 nonzero = addr[1:32] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
471 print ("RADIX _segment_check nonzero", bin(nonzero.value))
472 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
473 if addr[0] != addr[1] or nonzero == 1:
474 return "segerror"
475 limit = shift + (31 - 12)
476 if mbits < 5 or mbits > 16 or mbits > limit:
477 return "badtree"
478 new_shift = shift + (31 - 12) - mbits
479 return new_shift
480
481 def _check_perms(self, data, priv, mode):
482 """check page permissions
483 // Leaf PDE |
484 // |------------------------------| |----------------|
485 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
486 // |------------------------------| |----------------|
487 // [0] = V = Valid Bit |
488 // [1] = L = Leaf Bit = 1 if leaf |
489 // PDE |
490 // [2] = Sw = Sw bit 0. |
491 // [7:51] = RPN = Real Page Number, V
492 // real_page = RPN << 12 -------------> Logical OR
493 // [52:54] = Sw Bits 1:3 |
494 // [55] = R = Reference |
495 // [56] = C = Change V
496 // [58:59] = Att = Physical Address
497 // 0b00 = Normal Memory
498 // 0b01 = SAO
499 // 0b10 = Non Idenmpotent
500 // 0b11 = Tolerant I/O
501 // [60:63] = Encoded Access
502 // Authority
503 //
504 -- test leaf bit
505 -- check permissions and RC bits
506 perm_ok := '0';
507 if r.priv = '1' or data(3) = '0' then
508 if r.iside = '0' then
509 perm_ok := data(1) or (data(2) and not r.store);
510 else
511 -- no IAMR, so no KUEP support for now
512 -- deny execute permission if cache inhibited
513 perm_ok := data(0) and not data(5);
514 end if;
515 end if;
516 rc_ok := data(8) and (data(7) or not r.store);
517 if perm_ok = '1' and rc_ok = '1' then
518 v.state := RADIX_LOAD_TLB;
519 else
520 v.state := RADIX_FINISH;
521 v.perm_err := not perm_ok;
522 -- permission error takes precedence over RC error
523 v.rc_error := perm_ok;
524 end if;
525 """
526 # decode mode into something that matches microwatt equivalent code
527 instr_fetch, store = 0, 0
528 if mode == 'STORE':
529 store = 1
530 if mode == 'EXECUTE':
531 inst_fetch = 1
532
533 # check permissions and RC bits
534 perm_ok = 0
535 if priv == 1 or data[60] == 0:
536 if instr_fetch == 0:
537 perm_ok = data[62] | (data[61] & (store == 0))
538 # no IAMR, so no KUEP support for now
539 # deny execute permission if cache inhibited
540 perm_ok = data[63] & ~data[58]
541 rc_ok = data[55] & (data[56] | (store == 0))
542 if perm_ok == 1 and rc_ok == 1:
543 return True
544
545 return "perm_err" if perm_ok == 0 else "rc_err"
546
547 def _get_prtable_addr(self, shift, prtbl, addr, pid):
548 """
549 if r.addr(63) = '1' then
550 effpid := x"00000000";
551 else
552 effpid := r.pid;
553 end if;
554 x"00" & r.prtbl(55 downto 36) &
555 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
556 (effpid(31 downto 8) and finalmask(23 downto 0))) &
557 effpid(7 downto 0) & "0000";
558 """
559 print ("_get_prtable_addr_", shift, prtbl, addr, pid)
560 finalmask = genmask(shift, 44)
561 finalmask24 = finalmask[20:44]
562 if addr[0].value == 1:
563 effpid = SelectableInt(0, 32)
564 else:
565 effpid = pid #self.pid # TODO, check on this
566 zero16 = SelectableInt(0, 16)
567 zero4 = SelectableInt(0, 4)
568 res = selectconcat(zero16,
569 prtbl[8:28], #
570 (prtbl[28:52] & ~finalmask24) | #
571 (effpid[0:24] & finalmask24), #
572 effpid[24:32],
573 zero4
574 )
575 return res
576
577 def _get_pgtable_addr(self, mask_size, pgbase, addrsh, prtbl):
578 """
579 x"00" & r.pgbase(55 downto 19) &
580 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
581 "000";
582 """
583 mask16 = genmask(mask_size+5, 16)
584 zero8 = SelectableInt(0, 8)
585 zero3 = SelectableInt(0, 3)
586 res = selectconcat(zero8,
587 pgbase[8:45], #
588 (prtbl[45:61] & ~mask16) | #
589 (addrsh & mask16), #
590 zero3
591 )
592 return res
593
594 def _get_pte(self, shift, addr, pde):
595 """
596 x"00" &
597 ((r.pde(55 downto 12) and not finalmask) or
598 (r.addr(55 downto 12) and finalmask))
599 & r.pde(11 downto 0);
600 """
601 finalmask = genmask(shift, 44)
602 zero8 = SelectableInt(0, 8)
603 res = selectconcat(zero8,
604 (pde[8:52] & ~finalmask) | #
605 (addr[8:52] & finalmask), #
606 pde[52:64],
607 )
608 return res
609
610
611 class TestRadixMMU(unittest.TestCase):
612
613 def test_genmask(self):
614 shift = SelectableInt(5, 6)
615 mask = genmask(shift, 43)
616 print (" mask", bin(mask.value))
617
618 self.assertEqual(sum([1, 2, 3]), 6, "Should be 6")
619
620
621 def test_walk_tree(self):
622 # set up dummy minimal ISACaller
623 spr = {'DSISR': SelectableInt(0, 64),
624 'DAR': SelectableInt(0, 64),
625 'PIDR': SelectableInt(0, 64),
626 'PRTBL': SelectableInt(0, 64)
627 }
628 # set problem state == 0 (other unit tests, set to 1)
629 msr = SelectableInt(0, 64)
630 msr[MSRb.PR] = 0
631 class ISACaller: pass
632 caller = ISACaller()
633 caller.spr = spr
634 caller.msr = msr
635
636 shift = SelectableInt(5, 6)
637 mask = genmask(shift, 43)
638 print (" mask", bin(mask.value))
639
640 mem = Mem(row_bytes=8)
641 mem = RADIX(mem, caller)
642 # -----------------------------------------------
643 # |/|RTS1|/| RPDB | RTS2 | RPDS |
644 # -----------------------------------------------
645 # |0|1 2|3|4 55|56 58|59 63|
646 data = SelectableInt(0, 64)
647 data[1:3] = 0b01
648 data[56:59] = 0b11
649 data[59:64] = 0b01101 # mask
650 data[55] = 1
651 (rts, mbits, pgbase) = mem._decode_prte(data)
652 print (" rts", bin(rts.value), rts.bits)
653 print (" mbits", bin(mbits.value), mbits.bits)
654 print (" pgbase", hex(pgbase.value), pgbase.bits)
655 addr = SelectableInt(0x1000, 64)
656 check = mem._segment_check(addr, mbits, shift)
657 print (" segment check", check)
658
659 print("walking tree")
660 addr = SelectableInt(testaddr,64)
661 # pgbase = None
662 mode = None
663 #mbits = None
664 shift = rts
665 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
666 print(" walking tree result", result)
667
668
669 if __name__ == '__main__':
670 unittest.main()