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whoops PIDR is defined as 32-bits in SPRs.csv (and spec)
[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 from nmigen.back.pysim import Settle
17 from copy import copy
18 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from soc.decoder.helpers import exts, gtu, ltu, undefined
21 from soc.decoder.isa.mem import Mem
22
23 import math
24 import sys
25
26 # very quick, TODO move to SelectableInt utils later
27 def genmask(shift, size):
28 res = SelectableInt(0, size)
29 for i in range(size):
30 if i < shift:
31 res[size-1-i] = SelectableInt(1, 1)
32 return res
33
34 """
35 Get Root Page
36
37 //Accessing 2nd double word of partition table (pate1)
38 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
39 // PTCR Layout
40 // ====================================================
41 // -----------------------------------------------
42 // | /// | PATB | /// | PATS |
43 // -----------------------------------------------
44 // 0 4 51 52 58 59 63
45 // PATB[4:51] holds the base address of the Partition Table,
46 // right shifted by 12 bits.
47 // This is because the address of the Partition base is
48 // 4k aligned. Hence, the lower 12bits, which are always
49 // 0 are ommitted from the PTCR.
50 //
51 // Thus, The Partition Table Base is obtained by (PATB << 12)
52 //
53 // PATS represents the partition table size right-shifted by 12 bits.
54 // The minimal size of the partition table is 4k.
55 // Thus partition table size = (1 << PATS + 12).
56 //
57 // Partition Table
58 // ====================================================
59 // 0 PATE0 63 PATE1 127
60 // |----------------------|----------------------|
61 // | | |
62 // |----------------------|----------------------|
63 // | | |
64 // |----------------------|----------------------|
65 // | | | <-- effLPID
66 // |----------------------|----------------------|
67 // .
68 // .
69 // .
70 // |----------------------|----------------------|
71 // | | |
72 // |----------------------|----------------------|
73 //
74 // The effective LPID forms the index into the Partition Table.
75 //
76 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
77 // corresponding to that partition.
78 //
79 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
80 //
81 // PATE0 Layout
82 // -----------------------------------------------
83 // |1|RTS1|/| RPDB | RTS2 | RPDS |
84 // -----------------------------------------------
85 // 0 1 2 3 4 55 56 58 59 63
86 //
87 // HR[0] : For Radix Page table, first bit should be 1.
88 // RTS1[1:2] : Gives one fragment of the Radix treesize
89 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
90 // RTS = (RTS1 << 3 + RTS2) + 31.
91 //
92 // RPDB[4:55] = Root Page Directory Base.
93 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
94 // Thus, Root page directory size = 1 << (RPDS + 3).
95 // Note: RPDS >= 5.
96 //
97 // PATE1 Layout
98 // -----------------------------------------------
99 // |///| PRTB | // | PRTS |
100 // -----------------------------------------------
101 // 0 3 4 51 52 58 59 63
102 //
103 // PRTB[4:51] = Process Table Base. This is aligned to size.
104 // PRTS[59: 63] = Process Table Size right shifted by 12.
105 // Minimal size of the process table is 4k.
106 // Process Table Size = (1 << PRTS + 12).
107 // Note: PRTS <= 24.
108 //
109 // Computing the size aligned Process Table Base:
110 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
111 // Thus, the lower 12+PRTS bits of table_base will
112 // be zero.
113
114
115 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
116 //
117 // Process Table
118 // ==========================
119 // 0 PRTE0 63 PRTE1 127
120 // |----------------------|----------------------|
121 // | | |
122 // |----------------------|----------------------|
123 // | | |
124 // |----------------------|----------------------|
125 // | | | <-- effPID
126 // |----------------------|----------------------|
127 // .
128 // .
129 // .
130 // |----------------------|----------------------|
131 // | | |
132 // |----------------------|----------------------|
133 //
134 // The effective Process id (PID) forms the index into the Process Table.
135 //
136 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
137 // corresponding to that process
138 //
139 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
140 //
141 // PRTE0 Layout
142 // -----------------------------------------------
143 // |/|RTS1|/| RPDB | RTS2 | RPDS |
144 // -----------------------------------------------
145 // 0 1 2 3 4 55 56 58 59 63
146 //
147 // RTS1[1:2] : Gives one fragment of the Radix treesize
148 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
149 // RTS = (RTS1 << 3 + RTS2) << 31,
150 // since minimal Radix Tree size is 4G.
151 //
152 // RPDB = Root Page Directory Base.
153 // RPDS = Root Page Directory Size right shifted by 3.
154 // Thus, Root page directory size = RPDS << 3.
155 // Note: RPDS >= 5.
156 //
157 // PRTE1 Layout
158 // -----------------------------------------------
159 // | /// |
160 // -----------------------------------------------
161 // 0 63
162 // All bits are reserved.
163
164
165 """
166
167 # see qemu/target/ppc/mmu-radix64.c for reference
168 class RADIX:
169 def __init__(self, mem, caller):
170 self.mem = mem
171 self.caller = caller
172 #TODO move to lookup
173 self.dsisr = self.caller.spr["DSISR"]
174 self.dar = self.caller.spr["DAR"]
175 self.pidr = self.caller.spr["PIDR"]
176 self.prtbl = self.caller.spr["PRTBL"]
177
178 # cached page table stuff
179 self.pgtbl0 = 0
180 self.pt0_valid = False
181 self.pgtbl3 = 0
182 self.pt3_valid = False
183
184 def __call__(self, addr, sz):
185 val = self.ld(addr.value, sz, swap=False)
186 print("RADIX memread", addr, sz, val)
187 return SelectableInt(val, sz*8)
188
189 def ld(self, address, width=8, swap=True, check_in_mem=False):
190 print("RADIX: ld from addr 0x%x width %d" % (address, width))
191
192 mode = 'LOAD' # XXX TODO: executable load (icache)
193 addr = SelectableInt(address, 64)
194 (shift, mbits, pgbase) = self._decode_prte(addr)
195 #shift = SelectableInt(0, 32)
196
197 pte = self._walk_tree(addr, pgbase, mode, mbits, shift)
198 # use pte to caclculate phys address
199 return self.mem.ld(address, width, swap, check_in_mem)
200
201 # XXX set SPRs on error
202
203 # TODO implement
204 def st(self, address, v, width=8, swap=True):
205 print("RADIX: st to addr 0x%x width %d data %x" % (address, width, v))
206
207 mode = 'STORE'
208 addr = SelectableInt(address, 64)
209 (shift, mbits, pgbase) = self._decode_prte(addr)
210 pte = self._walk_tree(addr, pgbase, mode, mbits, shift)
211
212 # use pte to caclculate phys address (addr)
213 return self.mem.st(addr.value, v, width, swap)
214
215 # XXX set SPRs on error
216
217 def memassign(self, addr, sz, val):
218 print("memassign", addr, sz, val)
219 self.st(addr.value, val.value, sz, swap=False)
220
221 def _next_level(self):
222 return True
223 ## DSISR_R_BADCONFIG
224 ## read_entry
225 ## DSISR_NOPTE
226 ## Prepare for next iteration
227
228 def _walk_tree(self, addr, pgbase, mode, mbits, shift):
229 """walk tree
230
231 // vaddr 64 Bit
232 // vaddr |-----------------------------------------------------|
233 // | Unused | Used |
234 // |-----------|-----------------------------------------|
235 // | 0000000 | usefulBits = X bits (typically 52) |
236 // |-----------|-----------------------------------------|
237 // | |<--Cursize---->| |
238 // | | Index | |
239 // | | into Page | |
240 // | | Directory | |
241 // |-----------------------------------------------------|
242 // | |
243 // V |
244 // PDE |---------------------------| |
245 // |V|L|//| NLB |///|NLS| |
246 // |---------------------------| |
247 // PDE = Page Directory Entry |
248 // [0] = V = Valid Bit |
249 // [1] = L = Leaf bit. If 0, then |
250 // [4:55] = NLB = Next Level Base |
251 // right shifted by 8 |
252 // [59:63] = NLS = Next Level Size |
253 // | NLS >= 5 |
254 // | V
255 // | |--------------------------|
256 // | | usfulBits = X-Cursize |
257 // | |--------------------------|
258 // |---------------------><--NLS-->| |
259 // | Index | |
260 // | into | |
261 // | PDE | |
262 // |--------------------------|
263 // |
264 // If the next PDE obtained by |
265 // (NLB << 8 + 8 * index) is a |
266 // nonleaf, then repeat the above. |
267 // |
268 // If the next PDE is a leaf, |
269 // then Leaf PDE structure is as |
270 // follows |
271 // |
272 // |
273 // Leaf PDE |
274 // |------------------------------| |----------------|
275 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
276 // |------------------------------| |----------------|
277 // [0] = V = Valid Bit |
278 // [1] = L = Leaf Bit = 1 if leaf |
279 // PDE |
280 // [2] = Sw = Sw bit 0. |
281 // [7:51] = RPN = Real Page Number, V
282 // real_page = RPN << 12 -------------> Logical OR
283 // [52:54] = Sw Bits 1:3 |
284 // [55] = R = Reference |
285 // [56] = C = Change V
286 // [58:59] = Att = Physical Address
287 // 0b00 = Normal Memory
288 // 0b01 = SAO
289 // 0b10 = Non Idenmpotent
290 // 0b11 = Tolerant I/O
291 // [60:63] = Encoded Access
292 // Authority
293 //
294 """
295 # get sprs
296 print("_walk_tree")
297 pidr = self.caller.spr["PIDR"]
298 prtbl = self.caller.spr["PRTBL"]
299 print(pidr)
300 print(prtbl)
301
302 # get address of root entry
303 prtable_addr = self._get_prtable_addr(shift, prtbl, addr, pidr)
304 print("prtable_addr",prtable_addr)
305
306 # read root entry - imcomplete
307 swap = False
308 check_in_mem = False
309 entry_width = 8
310 value = self.mem.ld(prtable_addr.value, entry_width, swap, check_in_mem)
311 print("value",value)
312
313
314 # walk tree starts on prtbl
315 while True:
316 ret = self._next_level()
317 if ret: return ret
318 # TODO fix AttributeError: 'RADIX' object has no attribute 'pid'
319
320 def _decode_prte(self, data):
321 """PRTE0 Layout
322 -----------------------------------------------
323 |/|RTS1|/| RPDB | RTS2 | RPDS |
324 -----------------------------------------------
325 0 1 2 3 4 55 56 58 59 63
326 """
327 # note that SelectableInt does big-endian! so the indices
328 # below *directly* match the spec, unlike microwatt which
329 # has to turn them around (to LE)
330 zero = SelectableInt(0, 1)
331 rts = selectconcat(zero,
332 data[56:59], # RTS2
333 data[1:3], # RTS1
334 )
335 masksize = data[59:64] # RPDS
336 mbits = selectconcat(zero, masksize)
337 pgbase = selectconcat(data[8:56], # part of RPDB
338 SelectableInt(0, 16),)
339
340 return (rts, mbits, pgbase)
341
342 def _segment_check(self, addr, mbits, shift):
343 """checks segment valid
344 mbits := '0' & r.mask_size;
345 v.shift := r.shift + (31 - 12) - mbits;
346 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
347 if r.addr(63) /= r.addr(62) or nonzero = '1' then
348 v.state := RADIX_FINISH;
349 v.segerror := '1';
350 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
351 v.state := RADIX_FINISH;
352 v.badtree := '1';
353 else
354 v.state := RADIX_LOOKUP;
355 """
356 # note that SelectableInt does big-endian! so the indices
357 # below *directly* match the spec, unlike microwatt which
358 # has to turn them around (to LE)
359 mask = genmask(shift, 44)
360 nonzero = addr[1:32] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
361 print ("RADIX _segment_check nonzero", bin(nonzero.value))
362 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
363 if addr[0] != addr[1] or nonzero == 1:
364 return "segerror"
365 limit = shift + (31 - 12)
366 if mbits < 5 or mbits > 16 or mbits > limit:
367 return "badtree"
368 new_shift = shift + (31 - 12) - mbits
369 return new_shift
370
371 def _check_perms(self, data, priv, iside, store):
372 """check page permissions
373 // Leaf PDE |
374 // |------------------------------| |----------------|
375 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
376 // |------------------------------| |----------------|
377 // [0] = V = Valid Bit |
378 // [1] = L = Leaf Bit = 1 if leaf |
379 // PDE |
380 // [2] = Sw = Sw bit 0. |
381 // [7:51] = RPN = Real Page Number, V
382 // real_page = RPN << 12 -------------> Logical OR
383 // [52:54] = Sw Bits 1:3 |
384 // [55] = R = Reference |
385 // [56] = C = Change V
386 // [58:59] = Att = Physical Address
387 // 0b00 = Normal Memory
388 // 0b01 = SAO
389 // 0b10 = Non Idenmpotent
390 // 0b11 = Tolerant I/O
391 // [60:63] = Encoded Access
392 // Authority
393 //
394 -- test leaf bit
395 -- check permissions and RC bits
396 perm_ok := '0';
397 if r.priv = '1' or data(3) = '0' then
398 if r.iside = '0' then
399 perm_ok := data(1) or (data(2) and not r.store);
400 else
401 -- no IAMR, so no KUEP support for now
402 -- deny execute permission if cache inhibited
403 perm_ok := data(0) and not data(5);
404 end if;
405 end if;
406 rc_ok := data(8) and (data(7) or not r.store);
407 if perm_ok = '1' and rc_ok = '1' then
408 v.state := RADIX_LOAD_TLB;
409 else
410 v.state := RADIX_FINISH;
411 v.perm_err := not perm_ok;
412 -- permission error takes precedence over RC error
413 v.rc_error := perm_ok;
414 end if;
415 """
416 # check permissions and RC bits
417 perm_ok = 0
418 if priv == 1 or data[60] == 0:
419 if iside == 0:
420 perm_ok = data[62] | (data[61] & (store == 0))
421 # no IAMR, so no KUEP support for now
422 # deny execute permission if cache inhibited
423 perm_ok = data[63] & ~data[58]
424 rc_ok = data[55] & (data[56] | (store == 0))
425 if perm_ok == 1 and rc_ok == 1:
426 return True
427 return "perm_err" if perm_ok == 0 else "rc_err"
428
429 def _get_prtable_addr(self, shift, prtbl, addr, pid):
430 """
431 if r.addr(63) = '1' then
432 effpid := x"00000000";
433 else
434 effpid := r.pid;
435 end if;
436 x"00" & r.prtbl(55 downto 36) &
437 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
438 (effpid(31 downto 8) and finalmask(23 downto 0))) &
439 effpid(7 downto 0) & "0000";
440 """
441 print ("_get_prtable_addr_", shift, prtbl, addr, pid)
442 finalmask = genmask(shift, 44)
443 finalmask24 = finalmask[20:44]
444 if addr[0].value == 1:
445 effpid = SelectableInt(0, 32)
446 else:
447 effpid = pid #self.pid # TODO, check on this
448 zero16 = SelectableInt(0, 16)
449 zero4 = SelectableInt(0, 4)
450 res = selectconcat(zero16,
451 prtbl[8:28], #
452 (prtbl[28:52] & ~finalmask24) | #
453 (effpid[0:24] & finalmask24), #
454 effpid[24:32],
455 zero4
456 )
457 return res
458
459 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
460 """
461 x"00" & r.pgbase(55 downto 19) &
462 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
463 "000";
464 """
465 mask16 = genmask(mask_size+5, 16)
466 zero8 = SelectableInt(0, 8)
467 zero3 = SelectableInt(0, 3)
468 res = selectconcat(zero8,
469 pgbase[8:45], #
470 (prtbl[45:61] & ~mask16) | #
471 (addrsh & mask16), #
472 zero3
473 )
474 return res
475
476 def _get_pte(self, shift, addr, pde):
477 """
478 x"00" &
479 ((r.pde(55 downto 12) and not finalmask) or
480 (r.addr(55 downto 12) and finalmask))
481 & r.pde(11 downto 0);
482 """
483 finalmask = genmask(shift, 44)
484 zero8 = SelectableInt(0, 8)
485 res = selectconcat(zero8,
486 (pde[8:52] & ~finalmask) | #
487 (addr[8:52] & finalmask), #
488 pde[52:64],
489 )
490 return res
491
492
493 # very quick test of maskgen function (TODO, move to util later)
494 if __name__ == '__main__':
495 # set up dummy minimal ISACaller
496 spr = {'DSISR': SelectableInt(0, 64),
497 'DAR': SelectableInt(0, 64),
498 'PIDR': SelectableInt(0, 64),
499 'PRTBL': SelectableInt(0, 64)
500 }
501 class ISACaller: pass
502 caller = ISACaller()
503 caller.spr = spr
504
505 shift = SelectableInt(5, 6)
506 mask = genmask(shift, 43)
507 print (" mask", bin(mask.value))
508
509 mem = Mem(row_bytes=8)
510 mem = RADIX(mem, caller)
511 # -----------------------------------------------
512 # |/|RTS1|/| RPDB | RTS2 | RPDS |
513 # -----------------------------------------------
514 # |0|1 2|3|4 55|56 58|59 63|
515 data = SelectableInt(0, 64)
516 data[1:3] = 0b01
517 data[56:59] = 0b11
518 data[59:64] = 0b01101 # mask
519 data[55] = 1
520 (rts, mbits, pgbase) = mem._decode_prte(data)
521 print (" rts", bin(rts.value), rts.bits)
522 print (" mbits", bin(mbits.value), mbits.bits)
523 print (" pgbase", hex(pgbase.value), pgbase.bits)
524 addr = SelectableInt(0x1000, 64)
525 check = mem._segment_check(addr, mbits, shift)
526 print (" segment check", check)
527
528 print("walking tree")
529 # addr = unchanged
530 # pgbase = None
531 mode = None
532 #mbits = None
533 shift = rts
534 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
535 print(result)