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whoops shift has to be done at same bitwidth
[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 from nmigen.back.pysim import Settle
17 from copy import copy
18 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from soc.decoder.helpers import exts, gtu, ltu, undefined
21 from soc.decoder.isa.mem import Mem
22
23 import math
24 import sys
25
26 # very quick, TODO move to SelectableInt utils later
27 def genmask(shift, size):
28 res = SelectableInt(0, size)
29 for i in range(size):
30 if i < shift:
31 res[size-1-i] = SelectableInt(1, 1)
32 return res
33
34 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
35 # MSB is indexed **LOWEST** (sigh)
36 # from gem5 radixwalk.hh
37 # Bitfield<63> valid; 64 - (63 + 1) = 0
38 # Bitfield<62> leaf; 64 - (62 + 1) = 1
39
40 def rpte_valid(r):
41 return bool(r[0])
42
43 def rpte_leaf(r):
44 return bool(r[1])
45
46 def NLB(x):
47 """
48 Next Level Base
49 right shifted by 8
50 """
51 return x[4:55]
52
53 def NLS(x):
54 """
55 Next Level Size
56 NLS >= 5
57 """
58 return x[59:63]
59
60 """
61 Get Root Page
62
63 //Accessing 2nd double word of partition table (pate1)
64 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
65 // PTCR Layout
66 // ====================================================
67 // -----------------------------------------------
68 // | /// | PATB | /// | PATS |
69 // -----------------------------------------------
70 // 0 4 51 52 58 59 63
71 // PATB[4:51] holds the base address of the Partition Table,
72 // right shifted by 12 bits.
73 // This is because the address of the Partition base is
74 // 4k aligned. Hence, the lower 12bits, which are always
75 // 0 are ommitted from the PTCR.
76 //
77 // Thus, The Partition Table Base is obtained by (PATB << 12)
78 //
79 // PATS represents the partition table size right-shifted by 12 bits.
80 // The minimal size of the partition table is 4k.
81 // Thus partition table size = (1 << PATS + 12).
82 //
83 // Partition Table
84 // ====================================================
85 // 0 PATE0 63 PATE1 127
86 // |----------------------|----------------------|
87 // | | |
88 // |----------------------|----------------------|
89 // | | |
90 // |----------------------|----------------------|
91 // | | | <-- effLPID
92 // |----------------------|----------------------|
93 // .
94 // .
95 // .
96 // |----------------------|----------------------|
97 // | | |
98 // |----------------------|----------------------|
99 //
100 // The effective LPID forms the index into the Partition Table.
101 //
102 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
103 // corresponding to that partition.
104 //
105 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
106 //
107 // PATE0 Layout
108 // -----------------------------------------------
109 // |1|RTS1|/| RPDB | RTS2 | RPDS |
110 // -----------------------------------------------
111 // 0 1 2 3 4 55 56 58 59 63
112 //
113 // HR[0] : For Radix Page table, first bit should be 1.
114 // RTS1[1:2] : Gives one fragment of the Radix treesize
115 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
116 // RTS = (RTS1 << 3 + RTS2) + 31.
117 //
118 // RPDB[4:55] = Root Page Directory Base.
119 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
120 // Thus, Root page directory size = 1 << (RPDS + 3).
121 // Note: RPDS >= 5.
122 //
123 // PATE1 Layout
124 // -----------------------------------------------
125 // |///| PRTB | // | PRTS |
126 // -----------------------------------------------
127 // 0 3 4 51 52 58 59 63
128 //
129 // PRTB[4:51] = Process Table Base. This is aligned to size.
130 // PRTS[59: 63] = Process Table Size right shifted by 12.
131 // Minimal size of the process table is 4k.
132 // Process Table Size = (1 << PRTS + 12).
133 // Note: PRTS <= 24.
134 //
135 // Computing the size aligned Process Table Base:
136 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
137 // Thus, the lower 12+PRTS bits of table_base will
138 // be zero.
139
140
141 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
142 //
143 // Process Table
144 // ==========================
145 // 0 PRTE0 63 PRTE1 127
146 // |----------------------|----------------------|
147 // | | |
148 // |----------------------|----------------------|
149 // | | |
150 // |----------------------|----------------------|
151 // | | | <-- effPID
152 // |----------------------|----------------------|
153 // .
154 // .
155 // .
156 // |----------------------|----------------------|
157 // | | |
158 // |----------------------|----------------------|
159 //
160 // The effective Process id (PID) forms the index into the Process Table.
161 //
162 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
163 // corresponding to that process
164 //
165 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
166 //
167 // PRTE0 Layout
168 // -----------------------------------------------
169 // |/|RTS1|/| RPDB | RTS2 | RPDS |
170 // -----------------------------------------------
171 // 0 1 2 3 4 55 56 58 59 63
172 //
173 // RTS1[1:2] : Gives one fragment of the Radix treesize
174 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
175 // RTS = (RTS1 << 3 + RTS2) << 31,
176 // since minimal Radix Tree size is 4G.
177 //
178 // RPDB = Root Page Directory Base.
179 // RPDS = Root Page Directory Size right shifted by 3.
180 // Thus, Root page directory size = RPDS << 3.
181 // Note: RPDS >= 5.
182 //
183 // PRTE1 Layout
184 // -----------------------------------------------
185 // | /// |
186 // -----------------------------------------------
187 // 0 63
188 // All bits are reserved.
189
190
191 """
192
193 # see qemu/target/ppc/mmu-radix64.c for reference
194 class RADIX:
195 def __init__(self, mem, caller):
196 self.mem = mem
197 self.caller = caller
198 #TODO move to lookup
199 self.dsisr = self.caller.spr["DSISR"]
200 self.dar = self.caller.spr["DAR"]
201 self.pidr = self.caller.spr["PIDR"]
202 self.prtbl = self.caller.spr["PRTBL"]
203
204 # cached page table stuff
205 self.pgtbl0 = 0
206 self.pt0_valid = False
207 self.pgtbl3 = 0
208 self.pt3_valid = False
209
210 def __call__(self, addr, sz):
211 val = self.ld(addr.value, sz, swap=False)
212 print("RADIX memread", addr, sz, val)
213 return SelectableInt(val, sz*8)
214
215 def ld(self, address, width=8, swap=True, check_in_mem=False,
216 instr_fetch=False):
217 print("RADIX: ld from addr 0x%x width %d" % (address, width))
218
219 priv = 1 # XXX TODO: read MSR PR bit here priv = not ctrl.msr(MSR_PR);
220 if instr_fetch:
221 mode = 'EXECUTE'
222 else:
223 mode = 'LOAD'
224 addr = SelectableInt(address, 64)
225 (shift, mbits, pgbase) = self._decode_prte(addr)
226 #shift = SelectableInt(0, 32)
227
228 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
229 # use pte to caclculate phys address
230 return self.mem.ld(address, width, swap, check_in_mem)
231
232 # XXX set SPRs on error
233
234 # TODO implement
235 def st(self, address, v, width=8, swap=True):
236 print("RADIX: st to addr 0x%x width %d data %x" % (address, width, v))
237
238 priv = 1 # XXX TODO: read MSR PR bit here priv = not ctrl.msr(MSR_PR);
239 mode = 'STORE'
240 addr = SelectableInt(address, 64)
241 (shift, mbits, pgbase) = self._decode_prte(addr)
242 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
243
244 # use pte to caclculate phys address (addr)
245 return self.mem.st(addr.value, v, width, swap)
246
247 # XXX set SPRs on error
248
249 def memassign(self, addr, sz, val):
250 print("memassign", addr, sz, val)
251 self.st(addr.value, val.value, sz, swap=False)
252
253 def _next_level(self,r):
254 return rpte_valid(r), rpte_leaf(r)
255 ## DSISR_R_BADCONFIG
256 ## read_entry
257 ## DSISR_NOPTE
258 ## Prepare for next iteration
259
260 def _walk_tree(self, addr, pgbase, mode, mbits, shift, priv=1):
261 """walk tree
262
263 // vaddr 64 Bit
264 // vaddr |-----------------------------------------------------|
265 // | Unused | Used |
266 // |-----------|-----------------------------------------|
267 // | 0000000 | usefulBits = X bits (typically 52) |
268 // |-----------|-----------------------------------------|
269 // | |<--Cursize---->| |
270 // | | Index | |
271 // | | into Page | |
272 // | | Directory | |
273 // |-----------------------------------------------------|
274 // | |
275 // V |
276 // PDE |---------------------------| |
277 // |V|L|//| NLB |///|NLS| |
278 // |---------------------------| |
279 // PDE = Page Directory Entry |
280 // [0] = V = Valid Bit |
281 // [1] = L = Leaf bit. If 0, then |
282 // [4:55] = NLB = Next Level Base |
283 // right shifted by 8 |
284 // [59:63] = NLS = Next Level Size |
285 // | NLS >= 5 |
286 // | V
287 // | |--------------------------|
288 // | | usfulBits = X-Cursize |
289 // | |--------------------------|
290 // |---------------------><--NLS-->| |
291 // | Index | |
292 // | into | |
293 // | PDE | |
294 // |--------------------------|
295 // |
296 // If the next PDE obtained by |
297 // (NLB << 8 + 8 * index) is a |
298 // nonleaf, then repeat the above. |
299 // |
300 // If the next PDE is a leaf, |
301 // then Leaf PDE structure is as |
302 // follows |
303 // |
304 // |
305 // Leaf PDE |
306 // |------------------------------| |----------------|
307 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
308 // |------------------------------| |----------------|
309 // [0] = V = Valid Bit |
310 // [1] = L = Leaf Bit = 1 if leaf |
311 // PDE |
312 // [2] = Sw = Sw bit 0. |
313 // [7:51] = RPN = Real Page Number, V
314 // real_page = RPN << 12 -------------> Logical OR
315 // [52:54] = Sw Bits 1:3 |
316 // [55] = R = Reference |
317 // [56] = C = Change V
318 // [58:59] = Att = Physical Address
319 // 0b00 = Normal Memory
320 // 0b01 = SAO
321 // 0b10 = Non Idenmpotent
322 // 0b11 = Tolerant I/O
323 // [60:63] = Encoded Access
324 // Authority
325 //
326 """
327 # get sprs
328 print("_walk_tree")
329 pidr = self.caller.spr["PIDR"]
330 prtbl = self.caller.spr["PRTBL"]
331 print(pidr)
332 print(prtbl)
333 p = addr[55:63]
334 print("last 8 bits ----------")
335 print
336
337 # get address of root entry
338 prtable_addr = self._get_prtable_addr(shift, prtbl, addr, pidr)
339 print("prtable_addr",prtable_addr)
340
341 # read root entry - imcomplete
342 swap = False
343 check_in_mem = False
344 entry_width = 8
345 value = self.mem.ld(prtable_addr.value, entry_width, swap, check_in_mem)
346 data = SelectableInt(value, 64) # convert to SelectableInt
347 print("value",value)
348
349 test_input = [
350 SelectableInt(0x8000000000000007, 64), #valid
351 SelectableInt(0xc000000000000000, 64) #exit
352 ]
353 index = 0
354
355 # walk tree starts on prtbl
356 while True:
357 print("nextlevel----------------------------")
358 l = test_input[index]
359 index += 1
360 valid, leaf = self._next_level(l)
361 print(" valid, leaf", valid, leaf)
362 if leaf:
363 ok = self._check_perms(data, priv, mode)
364 # TODO: check permissions
365 else:
366 data = l # TODO put actual data here
367 newlookup = self._new_lookup(data, mbits, shift)
368 if newlookup == 'badtree':
369 return None
370 shift, mask, pgbase = newlookup
371 print (" next level", shift, mask, pgbase)
372 if not valid:
373 return None # TODO: return error
374 if leaf:
375 return None # TODO return something
376
377 def _new_lookup(self, data, mbits, shift):
378 """
379 mbits := unsigned('0' & data(4 downto 0));
380 if mbits < 5 or mbits > 16 or mbits > r.shift then
381 v.state := RADIX_FINISH;
382 v.badtree := '1'; -- throw error
383 else
384 v.shift := v.shift - mbits;
385 v.mask_size := mbits(4 downto 0);
386 v.pgbase := data(55 downto 8) & x"00"; NLB?
387 v.state := RADIX_LOOKUP; --> next level
388 end if;
389 """
390 mbits = data[59:64]
391 print("mbits=", mbits)
392 if mbits < 5 or mbits > 16:
393 print("badtree")
394 return "badtree"
395 # reduce shift (has to be done at same bitwidth)
396 shift = shift - selectconcat(SelectableInt(0, 1), mbits)
397 mask_size = mbits[1:5] # get 4 LSBs
398 pgbase = selectconcat(data[8:56], SelectableInt(0, 8)) # shift up 8
399 return shift, mask_size, pgbase
400
401 def _decode_prte(self, data):
402 """PRTE0 Layout
403 -----------------------------------------------
404 |/|RTS1|/| RPDB | RTS2 | RPDS |
405 -----------------------------------------------
406 0 1 2 3 4 55 56 58 59 63
407 """
408 # note that SelectableInt does big-endian! so the indices
409 # below *directly* match the spec, unlike microwatt which
410 # has to turn them around (to LE)
411 zero = SelectableInt(0, 1)
412 rts = selectconcat(zero,
413 data[56:59], # RTS2
414 data[1:3], # RTS1
415 )
416 masksize = data[59:64] # RPDS
417 mbits = selectconcat(zero, masksize)
418 pgbase = selectconcat(data[8:56], # part of RPDB
419 SelectableInt(0, 16),)
420
421 return (rts, mbits, pgbase)
422
423 def _segment_check(self, addr, mbits, shift):
424 """checks segment valid
425 mbits := '0' & r.mask_size;
426 v.shift := r.shift + (31 - 12) - mbits;
427 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
428 if r.addr(63) /= r.addr(62) or nonzero = '1' then
429 v.state := RADIX_FINISH;
430 v.segerror := '1';
431 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
432 v.state := RADIX_FINISH;
433 v.badtree := '1';
434 else
435 v.state := RADIX_LOOKUP;
436 """
437 # note that SelectableInt does big-endian! so the indices
438 # below *directly* match the spec, unlike microwatt which
439 # has to turn them around (to LE)
440 mask = genmask(shift, 44)
441 nonzero = addr[1:32] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
442 print ("RADIX _segment_check nonzero", bin(nonzero.value))
443 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
444 if addr[0] != addr[1] or nonzero == 1:
445 return "segerror"
446 limit = shift + (31 - 12)
447 if mbits < 5 or mbits > 16 or mbits > limit:
448 return "badtree"
449 new_shift = shift + (31 - 12) - mbits
450 return new_shift
451
452 def _check_perms(self, data, priv, mode):
453 """check page permissions
454 // Leaf PDE |
455 // |------------------------------| |----------------|
456 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
457 // |------------------------------| |----------------|
458 // [0] = V = Valid Bit |
459 // [1] = L = Leaf Bit = 1 if leaf |
460 // PDE |
461 // [2] = Sw = Sw bit 0. |
462 // [7:51] = RPN = Real Page Number, V
463 // real_page = RPN << 12 -------------> Logical OR
464 // [52:54] = Sw Bits 1:3 |
465 // [55] = R = Reference |
466 // [56] = C = Change V
467 // [58:59] = Att = Physical Address
468 // 0b00 = Normal Memory
469 // 0b01 = SAO
470 // 0b10 = Non Idenmpotent
471 // 0b11 = Tolerant I/O
472 // [60:63] = Encoded Access
473 // Authority
474 //
475 -- test leaf bit
476 -- check permissions and RC bits
477 perm_ok := '0';
478 if r.priv = '1' or data(3) = '0' then
479 if r.iside = '0' then
480 perm_ok := data(1) or (data(2) and not r.store);
481 else
482 -- no IAMR, so no KUEP support for now
483 -- deny execute permission if cache inhibited
484 perm_ok := data(0) and not data(5);
485 end if;
486 end if;
487 rc_ok := data(8) and (data(7) or not r.store);
488 if perm_ok = '1' and rc_ok = '1' then
489 v.state := RADIX_LOAD_TLB;
490 else
491 v.state := RADIX_FINISH;
492 v.perm_err := not perm_ok;
493 -- permission error takes precedence over RC error
494 v.rc_error := perm_ok;
495 end if;
496 """
497 # decode mode into something that matches microwatt equivalent code
498 instr_fetch, store = 0, 0
499 if mode == 'STORE':
500 store = 1
501 if mode == 'EXECUTE':
502 inst_fetch = 1
503
504 # check permissions and RC bits
505 perm_ok = 0
506 if priv == 1 or data[60] == 0:
507 if instr_fetch == 0:
508 perm_ok = data[62] | (data[61] & (store == 0))
509 # no IAMR, so no KUEP support for now
510 # deny execute permission if cache inhibited
511 perm_ok = data[63] & ~data[58]
512 rc_ok = data[55] & (data[56] | (store == 0))
513 if perm_ok == 1 and rc_ok == 1:
514 return True
515
516 return "perm_err" if perm_ok == 0 else "rc_err"
517
518 def _get_prtable_addr(self, shift, prtbl, addr, pid):
519 """
520 if r.addr(63) = '1' then
521 effpid := x"00000000";
522 else
523 effpid := r.pid;
524 end if;
525 x"00" & r.prtbl(55 downto 36) &
526 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
527 (effpid(31 downto 8) and finalmask(23 downto 0))) &
528 effpid(7 downto 0) & "0000";
529 """
530 print ("_get_prtable_addr_", shift, prtbl, addr, pid)
531 finalmask = genmask(shift, 44)
532 finalmask24 = finalmask[20:44]
533 if addr[0].value == 1:
534 effpid = SelectableInt(0, 32)
535 else:
536 effpid = pid #self.pid # TODO, check on this
537 zero16 = SelectableInt(0, 16)
538 zero4 = SelectableInt(0, 4)
539 res = selectconcat(zero16,
540 prtbl[8:28], #
541 (prtbl[28:52] & ~finalmask24) | #
542 (effpid[0:24] & finalmask24), #
543 effpid[24:32],
544 zero4
545 )
546 return res
547
548 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
549 """
550 x"00" & r.pgbase(55 downto 19) &
551 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
552 "000";
553 """
554 mask16 = genmask(mask_size+5, 16)
555 zero8 = SelectableInt(0, 8)
556 zero3 = SelectableInt(0, 3)
557 res = selectconcat(zero8,
558 pgbase[8:45], #
559 (prtbl[45:61] & ~mask16) | #
560 (addrsh & mask16), #
561 zero3
562 )
563 return res
564
565 def _get_pte(self, shift, addr, pde):
566 """
567 x"00" &
568 ((r.pde(55 downto 12) and not finalmask) or
569 (r.addr(55 downto 12) and finalmask))
570 & r.pde(11 downto 0);
571 """
572 finalmask = genmask(shift, 44)
573 zero8 = SelectableInt(0, 8)
574 res = selectconcat(zero8,
575 (pde[8:52] & ~finalmask) | #
576 (addr[8:52] & finalmask), #
577 pde[52:64],
578 )
579 return res
580
581
582 # very quick test of maskgen function (TODO, move to util later)
583 if __name__ == '__main__':
584 # set up dummy minimal ISACaller
585 spr = {'DSISR': SelectableInt(0, 64),
586 'DAR': SelectableInt(0, 64),
587 'PIDR': SelectableInt(0, 64),
588 'PRTBL': SelectableInt(0, 64)
589 }
590 class ISACaller: pass
591 caller = ISACaller()
592 caller.spr = spr
593
594 shift = SelectableInt(5, 6)
595 mask = genmask(shift, 43)
596 print (" mask", bin(mask.value))
597
598 mem = Mem(row_bytes=8)
599 mem = RADIX(mem, caller)
600 # -----------------------------------------------
601 # |/|RTS1|/| RPDB | RTS2 | RPDS |
602 # -----------------------------------------------
603 # |0|1 2|3|4 55|56 58|59 63|
604 data = SelectableInt(0, 64)
605 data[1:3] = 0b01
606 data[56:59] = 0b11
607 data[59:64] = 0b01101 # mask
608 data[55] = 1
609 (rts, mbits, pgbase) = mem._decode_prte(data)
610 print (" rts", bin(rts.value), rts.bits)
611 print (" mbits", bin(mbits.value), mbits.bits)
612 print (" pgbase", hex(pgbase.value), pgbase.bits)
613 addr = SelectableInt(0x1000, 64)
614 check = mem._segment_check(addr, mbits, shift)
615 print (" segment check", check)
616
617 print("walking tree")
618 # addr = unchanged
619 # pgbase = None
620 mode = None
621 #mbits = None
622 shift = rts
623 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
624 print(result)