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more fixes for radixmmu.py
[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 #from nmigen.back.pysim import Settle
17 from copy import copy
18 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from soc.decoder.helpers import exts, gtu, ltu, undefined
21 from soc.decoder.isa.mem import Mem
22 from soc.consts import MSRb # big-endian (PowerISA versions)
23
24 import math
25 import sys
26 import unittest
27
28 # very quick, TODO move to SelectableInt utils later
29 def genmask(shift, size):
30 res = SelectableInt(0, size)
31 for i in range(size):
32 if i < shift:
33 res[size-1-i] = SelectableInt(1, 1)
34 return res
35
36 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
37 # MSB is indexed **LOWEST** (sigh)
38 # from gem5 radixwalk.hh
39 # Bitfield<63> valid; 64 - (63 + 1) = 0
40 # Bitfield<62> leaf; 64 - (62 + 1) = 1
41
42 def rpte_valid(r):
43 return bool(r[0])
44
45 def rpte_leaf(r):
46 return bool(r[1])
47
48 ## Shift address bits 61--12 right by 0--47 bits and
49 ## supply the least significant 16 bits of the result.
50 def addrshift(addr,shift):
51 print("addrshift")
52 print(addr)
53 print(shift)
54 x = addr.value >> shift.value
55 return SelectableInt(x,16)
56
57 def NLB(x):
58 """
59 Next Level Base
60 right shifted by 8
61 """
62 return x[4:55]
63
64 def NLS(x):
65 """
66 Next Level Size
67 NLS >= 5
68 """
69 return x[59:63]
70
71 def RPDB(x):
72 """
73 Root Page Directory Base
74 power isa docs says 4:55 investigate
75 """
76 return x[8:56]
77
78 """
79 Get Root Page
80
81 //Accessing 2nd double word of partition table (pate1)
82 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
83 // PTCR Layout
84 // ====================================================
85 // -----------------------------------------------
86 // | /// | PATB | /// | PATS |
87 // -----------------------------------------------
88 // 0 4 51 52 58 59 63
89 // PATB[4:51] holds the base address of the Partition Table,
90 // right shifted by 12 bits.
91 // This is because the address of the Partition base is
92 // 4k aligned. Hence, the lower 12bits, which are always
93 // 0 are ommitted from the PTCR.
94 //
95 // Thus, The Partition Table Base is obtained by (PATB << 12)
96 //
97 // PATS represents the partition table size right-shifted by 12 bits.
98 // The minimal size of the partition table is 4k.
99 // Thus partition table size = (1 << PATS + 12).
100 //
101 // Partition Table
102 // ====================================================
103 // 0 PATE0 63 PATE1 127
104 // |----------------------|----------------------|
105 // | | |
106 // |----------------------|----------------------|
107 // | | |
108 // |----------------------|----------------------|
109 // | | | <-- effLPID
110 // |----------------------|----------------------|
111 // .
112 // .
113 // .
114 // |----------------------|----------------------|
115 // | | |
116 // |----------------------|----------------------|
117 //
118 // The effective LPID forms the index into the Partition Table.
119 //
120 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
121 // corresponding to that partition.
122 //
123 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
124 //
125 // PATE0 Layout
126 // -----------------------------------------------
127 // |1|RTS1|/| RPDB | RTS2 | RPDS |
128 // -----------------------------------------------
129 // 0 1 2 3 4 55 56 58 59 63
130 //
131 // HR[0] : For Radix Page table, first bit should be 1.
132 // RTS1[1:2] : Gives one fragment of the Radix treesize
133 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
134 // RTS = (RTS1 << 3 + RTS2) + 31.
135 //
136 // RPDB[4:55] = Root Page Directory Base.
137 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
138 // Thus, Root page directory size = 1 << (RPDS + 3).
139 // Note: RPDS >= 5.
140 //
141 // PATE1 Layout
142 // -----------------------------------------------
143 // |///| PRTB | // | PRTS |
144 // -----------------------------------------------
145 // 0 3 4 51 52 58 59 63
146 //
147 // PRTB[4:51] = Process Table Base. This is aligned to size.
148 // PRTS[59: 63] = Process Table Size right shifted by 12.
149 // Minimal size of the process table is 4k.
150 // Process Table Size = (1 << PRTS + 12).
151 // Note: PRTS <= 24.
152 //
153 // Computing the size aligned Process Table Base:
154 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
155 // Thus, the lower 12+PRTS bits of table_base will
156 // be zero.
157
158
159 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
160 //
161 // Process Table
162 // ==========================
163 // 0 PRTE0 63 PRTE1 127
164 // |----------------------|----------------------|
165 // | | |
166 // |----------------------|----------------------|
167 // | | |
168 // |----------------------|----------------------|
169 // | | | <-- effPID
170 // |----------------------|----------------------|
171 // .
172 // .
173 // .
174 // |----------------------|----------------------|
175 // | | |
176 // |----------------------|----------------------|
177 //
178 // The effective Process id (PID) forms the index into the Process Table.
179 //
180 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
181 // corresponding to that process
182 //
183 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
184 //
185 // PRTE0 Layout
186 // -----------------------------------------------
187 // |/|RTS1|/| RPDB | RTS2 | RPDS |
188 // -----------------------------------------------
189 // 0 1 2 3 4 55 56 58 59 63
190 //
191 // RTS1[1:2] : Gives one fragment of the Radix treesize
192 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
193 // RTS = (RTS1 << 3 + RTS2) << 31,
194 // since minimal Radix Tree size is 4G.
195 //
196 // RPDB = Root Page Directory Base.
197 // RPDS = Root Page Directory Size right shifted by 3.
198 // Thus, Root page directory size = RPDS << 3.
199 // Note: RPDS >= 5.
200 //
201 // PRTE1 Layout
202 // -----------------------------------------------
203 // | /// |
204 // -----------------------------------------------
205 // 0 63
206 // All bits are reserved.
207
208
209 """
210
211 testmem = {
212
213 0x10000: # PARTITION_TABLE_2 (not implemented yet)
214 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
215 0x800000000100000b,
216
217 0x30000: # RADIX_ROOT_PTE
218 # V = 1 L = 0 NLB = 0x400 NLS = 9
219 0x8000000000040009,
220 0x40000: # RADIX_SECOND_LEVEL
221 # V = 1 L = 1 SW = 0 RPN = 0
222 # R = 1 C = 1 ATT = 0 EAA 0x7
223 0xc000000000000187,
224
225 0x1000000: # PROCESS_TABLE_3
226 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
227 0x40000000000300ad,
228 }
229
230 # this one has a 2nd level RADIX with a RPN of 0x5000
231 testmem2 = {
232
233 0x10000: # PARTITION_TABLE_2 (not implemented yet)
234 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
235 0x800000000100000b,
236
237 0x30000: # RADIX_ROOT_PTE
238 # V = 1 L = 0 NLB = 0x400 NLS = 9
239 0x8000000000040009,
240 0x40000: # RADIX_SECOND_LEVEL
241 # V = 1 L = 1 SW = 0 RPN = 0x5000
242 # R = 1 C = 1 ATT = 0 EAA 0x7
243 0xc000000005000187,
244
245 0x1000000: # PROCESS_TABLE_3
246 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
247 0x40000000000300ad,
248 }
249
250 testresult = """
251 prtbl = 1000000
252 DCACHE GET 1000000 PROCESS_TABLE_3
253 DCACHE GET 30000 RADIX_ROOT_PTE V = 1 L = 0
254 DCACHE GET 40000 RADIX_SECOND_LEVEL V = 1 L = 1
255 DCACHE GET 10000 PARTITION_TABLE_2
256 translated done 1 err 0 badtree 0 addr 40000 pte 0
257 """
258
259 # see qemu/target/ppc/mmu-radix64.c for reference
260 class RADIX:
261 def __init__(self, mem, caller):
262 self.mem = mem
263 self.caller = caller
264 if caller is not None:
265 print("caller")
266 print(caller)
267 self.dsisr = self.caller.spr["DSISR"]
268 self.dar = self.caller.spr["DAR"]
269 self.pidr = self.caller.spr["PIDR"]
270 self.prtbl = self.caller.spr["PRTBL"]
271 self.msr = self.caller.msr
272
273 # cached page table stuff
274 self.pgtbl0 = 0
275 self.pt0_valid = False
276 self.pgtbl3 = 0
277 self.pt3_valid = False
278
279 def __call__(self, addr, sz):
280 val = self.ld(addr.value, sz, swap=False)
281 print("RADIX memread", addr, sz, val)
282 return SelectableInt(val, sz*8)
283
284 def ld(self, address, width=8, swap=True, check_in_mem=False,
285 instr_fetch=False):
286 print("RADIX: ld from addr 0x%x width %d" % (address, width))
287
288 priv = ~(self.msr[MSRb.PR].value) # problem-state ==> privileged
289 if instr_fetch:
290 mode = 'EXECUTE'
291 else:
292 mode = 'LOAD'
293 addr = SelectableInt(address, 64)
294 (shift, mbits, pgbase) = self._decode_prte(addr)
295 #shift = SelectableInt(0, 32)
296
297 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
298
299 # use pte to load from phys address
300 return self.mem.ld(pte.value, width, swap, check_in_mem)
301
302 # XXX set SPRs on error
303
304 # TODO implement
305 def st(self, address, v, width=8, swap=True):
306 print("RADIX: st to addr 0x%x width %d data %x" % (address, width, v))
307
308 priv = ~(self.msr[MSRb.PR].value) # problem-state ==> privileged
309 mode = 'STORE'
310 addr = SelectableInt(address, 64)
311 (shift, mbits, pgbase) = self._decode_prte(addr)
312 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
313
314 # use pte to store at phys address
315 return self.mem.st(pte.value, v, width, swap)
316
317 # XXX set SPRs on error
318
319 def memassign(self, addr, sz, val):
320 print("memassign", addr, sz, val)
321 self.st(addr.value, val.value, sz, swap=False)
322
323 def _next_level(self, addr, entry_width, swap, check_in_mem):
324 # implement read access to mmu mem here
325
326 # DO NOT perform byte-swapping: load 8 bytes (that's the entry size)
327 value = self.mem.ld(addr.value, 8, False, check_in_mem)
328 if value is None:
329 return "address lookup %x not found" % addr.value
330 # assert(value is not None, "address lookup %x not found" % addr.value)
331
332 print("addr", hex(addr.value))
333 data = SelectableInt(value, 64) # convert to SelectableInt
334 print("value", hex(value))
335 # index += 1
336 return data;
337
338 def _walk_tree(self, addr, pgbase, mode, mbits, shift, priv=1):
339 """walk tree
340
341 // vaddr 64 Bit
342 // vaddr |-----------------------------------------------------|
343 // | Unused | Used |
344 // |-----------|-----------------------------------------|
345 // | 0000000 | usefulBits = X bits (typically 52) |
346 // |-----------|-----------------------------------------|
347 // | |<--Cursize---->| |
348 // | | Index | |
349 // | | into Page | |
350 // | | Directory | |
351 // |-----------------------------------------------------|
352 // | |
353 // V |
354 // PDE |---------------------------| |
355 // |V|L|//| NLB |///|NLS| |
356 // |---------------------------| |
357 // PDE = Page Directory Entry |
358 // [0] = V = Valid Bit |
359 // [1] = L = Leaf bit. If 0, then |
360 // [4:55] = NLB = Next Level Base |
361 // right shifted by 8 |
362 // [59:63] = NLS = Next Level Size |
363 // | NLS >= 5 |
364 // | V
365 // | |--------------------------|
366 // | | usfulBits = X-Cursize |
367 // | |--------------------------|
368 // |---------------------><--NLS-->| |
369 // | Index | |
370 // | into | |
371 // | PDE | |
372 // |--------------------------|
373 // |
374 // If the next PDE obtained by |
375 // (NLB << 8 + 8 * index) is a |
376 // nonleaf, then repeat the above. |
377 // |
378 // If the next PDE is a leaf, |
379 // then Leaf PDE structure is as |
380 // follows |
381 // |
382 // |
383 // Leaf PDE |
384 // |------------------------------| |----------------|
385 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
386 // |------------------------------| |----------------|
387 // [0] = V = Valid Bit |
388 // [1] = L = Leaf Bit = 1 if leaf |
389 // PDE |
390 // [2] = Sw = Sw bit 0. |
391 // [7:51] = RPN = Real Page Number, V
392 // real_page = RPN << 12 -------------> Logical OR
393 // [52:54] = Sw Bits 1:3 |
394 // [55] = R = Reference |
395 // [56] = C = Change V
396 // [58:59] = Att = Physical Address
397 // 0b00 = Normal Memory
398 // 0b01 = SAO
399 // 0b10 = Non Idenmpotent
400 // 0b11 = Tolerant I/O
401 // [60:63] = Encoded Access
402 // Authority
403 //
404 """
405 # get sprs
406 print("_walk_tree")
407 pidr = self.caller.spr["PIDR"]
408 prtbl = self.caller.spr["PRTBL"]
409 print(pidr)
410 print(prtbl)
411 p = addr[55:63]
412 print("last 8 bits ----------")
413 print
414
415 # get address of root entry
416 shift = selectconcat(SelectableInt(0,1), prtbl[58:63]) # TODO verify
417 addr_next = self._get_prtable_addr(shift, prtbl, addr, pidr)
418 print("starting with prtable, addr_next",addr_next)
419
420 assert(addr_next.bits == 64)
421 #only for first unit tests assert(addr_next.value == 0x1000000)
422
423 # read an entry from prtable
424 swap = False
425 check_in_mem = False
426 entry_width = 8
427 data = self._next_level(addr_next, entry_width, swap, check_in_mem)
428 print("pr_table",data)
429 pgtbl = data # this is cached in microwatt (as v.pgtbl3 / v.pgtbl0)
430
431 # rts = shift = unsigned('0' & data(62 downto 61) & data(7 downto 5));
432 shift = selectconcat(SelectableInt(0,1), data[1:3], data[55:58])
433 assert(shift.bits==6) # variable rts : unsigned(5 downto 0);
434 print("shift",shift)
435
436 # mbits := unsigned('0' & data(4 downto 0));
437 mbits = selectconcat(SelectableInt(0,1), data[58:63])
438 assert(mbits.bits==6) #variable mbits : unsigned(5 downto 0);
439
440 # WIP
441 if mbits==0:
442 return "invalid"
443
444 # mask_size := mbits(4 downto 0);
445 mask_size = mbits[0:5];
446 assert(mask_size.bits==5)
447 print("before segment check ==========")
448 print("mask_size:",bin(mask_size.value))
449 print("mbits:",bin(mbits.value))
450
451 print("calling segment_check")
452
453 mbits = selectconcat(SelectableInt(0,1), mask_size)
454 shift = self._segment_check(addr, mbits, shift)
455 print("shift",shift)
456
457 # v.pgbase := pgtbl(55 downto 8) & x"00";
458 # see test_RPDB for reference
459 zero8 = SelectableInt(0,8)
460
461 pgbase = selectconcat(zero8,RPDB(pgtbl),zero8)
462 print("pgbase",pgbase)
463 #assert(pgbase.value==0x30000)
464
465 addrsh = addrshift(addr,shift)
466 print("addrsh",addrsh)
467
468 addr_next = self._get_pgtable_addr(mask_size, pgbase, addrsh)
469 print("DONE addr_next",addr_next)
470
471 # walk tree
472 while True:
473 print("nextlevel----------------------------")
474 # read an entry
475 swap = False
476 check_in_mem = False
477 entry_width = 8
478
479 data = self._next_level(addr_next, entry_width, swap, check_in_mem)
480 valid = rpte_valid(data)
481 leaf = rpte_leaf(data)
482
483 print(" valid, leaf", valid, leaf)
484 if not valid:
485 return "invalid" # TODO: return error
486 if leaf:
487 print ("is leaf, checking perms")
488 ok = self._check_perms(data, priv, mode)
489 if ok == True: # data was ok, found phys address, return it?
490 paddr = self._get_pte(addrsh, addr, data)
491 print (" phys addr", hex(paddr.value))
492 return paddr
493 return ok # return the error code
494 else:
495 newlookup = self._new_lookup(data, shift)
496 if newlookup == 'badtree':
497 return newlookup
498 shift, mask, pgbase = newlookup
499 print (" next level", shift, mask, pgbase)
500 shift = SelectableInt(shift.value,16) #THIS is wrong !!!
501 print("calling _get_pgtable_addr")
502 print(mask) #SelectableInt(value=0x9, bits=4)
503 print(pgbase) #SelectableInt(value=0x40000, bits=56)
504 print(shift) #SelectableInt(value=0x4, bits=16) #FIXME
505 pgbase = SelectableInt(pgbase.value, 64)
506 addrsh = addrshift(addr,shift)
507 addr_next = self._get_pgtable_addr(mask, pgbase, addrsh)
508 print("addr_next",addr_next)
509 print("addrsh",addrsh)
510
511 def _new_lookup(self, data, shift):
512 """
513 mbits := unsigned('0' & data(4 downto 0));
514 if mbits < 5 or mbits > 16 or mbits > r.shift then
515 v.state := RADIX_FINISH;
516 v.badtree := '1'; -- throw error
517 else
518 v.shift := v.shift - mbits;
519 v.mask_size := mbits(4 downto 0);
520 v.pgbase := data(55 downto 8) & x"00"; NLB?
521 v.state := RADIX_LOOKUP; --> next level
522 end if;
523 """
524 mbits = data[59:64]
525 print("mbits=", mbits)
526 if mbits < 5 or mbits > 16: #fixme compare with r.shift
527 print("badtree")
528 return "badtree"
529 # reduce shift (has to be done at same bitwidth)
530 shift = shift - selectconcat(SelectableInt(0, 1), mbits)
531 mask_size = mbits[1:5] # get 4 LSBs
532 pgbase = selectconcat(data[8:56], SelectableInt(0, 8)) # shift up 8
533 return shift, mask_size, pgbase
534
535 def _decode_prte(self, data):
536 """PRTE0 Layout
537 -----------------------------------------------
538 |/|RTS1|/| RPDB | RTS2 | RPDS |
539 -----------------------------------------------
540 0 1 2 3 4 55 56 58 59 63
541 """
542 # note that SelectableInt does big-endian! so the indices
543 # below *directly* match the spec, unlike microwatt which
544 # has to turn them around (to LE)
545 zero = SelectableInt(0, 1)
546 rts = selectconcat(zero,
547 data[56:59], # RTS2
548 data[1:3], # RTS1
549 )
550 masksize = data[59:64] # RPDS
551 mbits = selectconcat(zero, masksize)
552 pgbase = selectconcat(data[8:56], # part of RPDB
553 SelectableInt(0, 16),)
554
555 return (rts, mbits, pgbase)
556
557 def _segment_check(self, addr, mbits, shift):
558 """checks segment valid
559 mbits := '0' & r.mask_size;
560 v.shift := r.shift + (31 - 12) - mbits;
561 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
562 if r.addr(63) /= r.addr(62) or nonzero = '1' then
563 v.state := RADIX_FINISH;
564 v.segerror := '1';
565 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
566 v.state := RADIX_FINISH;
567 v.badtree := '1';
568 else
569 v.state := RADIX_LOOKUP;
570 """
571 # note that SelectableInt does big-endian! so the indices
572 # below *directly* match the spec, unlike microwatt which
573 # has to turn them around (to LE)
574 mask = genmask(shift, 44)
575 nonzero = addr[2:33] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
576 print ("RADIX _segment_check nonzero", bin(nonzero.value))
577 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
578 if addr[0] != addr[1] or nonzero != 0:
579 return "segerror"
580 limit = shift + (31 - 12)
581 if mbits.value < 5 or mbits.value > 16 or mbits.value > limit.value:
582 return "badtree mbits="+str(mbits.value)+" limit="+str(limit.value)
583 new_shift = shift + (31 - 12) - mbits
584 # TODO verify that returned result is correct
585 return new_shift
586
587 def _check_perms(self, data, priv, mode):
588 """check page permissions
589 // Leaf PDE |
590 // |------------------------------| |----------------|
591 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
592 // |------------------------------| |----------------|
593 // [0] = V = Valid Bit |
594 // [1] = L = Leaf Bit = 1 if leaf |
595 // PDE |
596 // [2] = Sw = Sw bit 0. |
597 // [7:51] = RPN = Real Page Number, V
598 // real_page = RPN << 12 -------------> Logical OR
599 // [52:54] = Sw Bits 1:3 |
600 // [55] = R = Reference |
601 // [56] = C = Change V
602 // [58:59] = Att = Physical Address
603 // 0b00 = Normal Memory
604 // 0b01 = SAO
605 // 0b10 = Non Idenmpotent
606 // 0b11 = Tolerant I/O
607 // [60:63] = Encoded Access
608 // Authority
609 //
610 -- test leaf bit
611 -- check permissions and RC bits
612 perm_ok := '0';
613 if r.priv = '1' or data(3) = '0' then
614 if r.iside = '0' then
615 perm_ok := data(1) or (data(2) and not r.store);
616 else
617 -- no IAMR, so no KUEP support for now
618 -- deny execute permission if cache inhibited
619 perm_ok := data(0) and not data(5);
620 end if;
621 end if;
622 rc_ok := data(8) and (data(7) or not r.store);
623 if perm_ok = '1' and rc_ok = '1' then
624 v.state := RADIX_LOAD_TLB;
625 else
626 v.state := RADIX_FINISH;
627 v.perm_err := not perm_ok;
628 -- permission error takes precedence over RC error
629 v.rc_error := perm_ok;
630 end if;
631 """
632 # decode mode into something that matches microwatt equivalent code
633 instr_fetch, store = 0, 0
634 if mode == 'STORE':
635 store = 1
636 if mode == 'EXECUTE':
637 inst_fetch = 1
638
639 # check permissions and RC bits
640 perm_ok = 0
641 if priv == 1 or data[60] == 0:
642 if instr_fetch == 0:
643 perm_ok = data[62] | (data[61] & (store == 0))
644 # no IAMR, so no KUEP support for now
645 # deny execute permission if cache inhibited
646 perm_ok = data[63] & ~data[58]
647 rc_ok = data[55] & (data[56] | (store == 0))
648 if perm_ok == 1 and rc_ok == 1:
649 return True
650
651 return "perm_err" if perm_ok == 0 else "rc_err"
652
653 def _get_prtable_addr(self, shift, prtbl, addr, pid):
654 """
655 if r.addr(63) = '1' then
656 effpid := x"00000000";
657 else
658 effpid := r.pid;
659 end if;
660 x"00" & r.prtbl(55 downto 36) &
661 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
662 (effpid(31 downto 8) and finalmask(23 downto 0))) &
663 effpid(7 downto 0) & "0000";
664 """
665 print ("_get_prtable_addr", shift, prtbl, addr, pid)
666 finalmask = genmask(shift, 44)
667 finalmask24 = finalmask[20:44]
668 if addr[0].value == 1:
669 effpid = SelectableInt(0, 32)
670 else:
671 effpid = pid #self.pid # TODO, check on this
672 zero8 = SelectableInt(0, 8)
673 zero4 = SelectableInt(0, 4)
674 res = selectconcat(zero8,
675 prtbl[8:28], #
676 (prtbl[28:52] & ~finalmask24) | #
677 (effpid[0:24] & finalmask24), #
678 effpid[24:32],
679 zero4
680 )
681 return res
682
683 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
684 """
685 x"00" & r.pgbase(55 downto 19) &
686 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
687 "000";
688 """
689 mask16 = genmask(mask_size+5, 16)
690 zero8 = SelectableInt(0, 8)
691 zero3 = SelectableInt(0, 3)
692 res = selectconcat(zero8,
693 pgbase[8:45], #
694 (pgbase[45:61] & ~mask16) | #
695 (addrsh & mask16), #
696 zero3
697 )
698 return res
699
700 def _get_pte(self, shift, addr, pde):
701 """
702 x"00" &
703 ((r.pde(55 downto 12) and not finalmask) or
704 (r.addr(55 downto 12) and finalmask))
705 & r.pde(11 downto 0);
706 """
707 shift.value = 12
708 finalmask = genmask(shift, 44)
709 zero8 = SelectableInt(0, 8)
710 rpn = pde[8:52] # RPN = Real Page Number
711 abits = addr[8:52] # non-masked address bits
712 print(" get_pte RPN", hex(rpn.value))
713 print(" abits", hex(abits.value))
714 print(" shift", shift.value)
715 print(" finalmask", bin(finalmask.value))
716 res = selectconcat(zero8,
717 (rpn & ~finalmask) | #
718 (abits & finalmask), #
719 addr[52:64],
720 )
721 return res
722
723 class TestRadixMMU(unittest.TestCase):
724
725 def test_genmask(self):
726 shift = SelectableInt(5, 6)
727 mask = genmask(shift, 43)
728 print (" mask", bin(mask.value))
729
730 self.assertEqual(mask.value, 0b11111, "mask should be 5 1s")
731
732 def test_RPDB(self):
733 inp = SelectableInt(0x40000000000300ad, 64)
734
735 rtdb = RPDB(inp)
736 print("rtdb",rtdb,bin(rtdb.value))
737 self.assertEqual(rtdb.value,0x300,"rtdb should be 0x300")
738
739 result = selectconcat(rtdb,SelectableInt(0,8))
740 print("result",result)
741
742
743 def test_get_pgtable_addr(self):
744
745 mem = None
746 caller = None
747 dut = RADIX(mem, caller)
748
749 mask_size=4
750 pgbase = SelectableInt(0,64)
751 addrsh = SelectableInt(0,16)
752 ret = dut._get_pgtable_addr(mask_size, pgbase, addrsh)
753 print("ret=", ret)
754 self.assertEqual(ret, 0, "pgtbl_addr should be 0")
755
756 def test_walk_tree_1(self):
757
758 # test address as in
759 # https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/radix_walk_example.txt#L65
760 testaddr = 0x1000
761 expected = 0x1000
762
763 # starting prtbl
764 prtbl = 0x1000000
765
766 # set up dummy minimal ISACaller
767 spr = {'DSISR': SelectableInt(0, 64),
768 'DAR': SelectableInt(0, 64),
769 'PIDR': SelectableInt(0, 64),
770 'PRTBL': SelectableInt(prtbl, 64)
771 }
772 # set problem state == 0 (other unit tests, set to 1)
773 msr = SelectableInt(0, 64)
774 msr[MSRb.PR] = 0
775 class ISACaller: pass
776 caller = ISACaller()
777 caller.spr = spr
778 caller.msr = msr
779
780 shift = SelectableInt(5, 6)
781 mask = genmask(shift, 43)
782 print (" mask", bin(mask.value))
783
784 mem = Mem(row_bytes=8, initial_mem=testmem)
785 mem = RADIX(mem, caller)
786 # -----------------------------------------------
787 # |/|RTS1|/| RPDB | RTS2 | RPDS |
788 # -----------------------------------------------
789 # |0|1 2|3|4 55|56 58|59 63|
790 data = SelectableInt(0, 64)
791 data[1:3] = 0b01
792 data[56:59] = 0b11
793 data[59:64] = 0b01101 # mask
794 data[55] = 1
795 (rts, mbits, pgbase) = mem._decode_prte(data)
796 print (" rts", bin(rts.value), rts.bits)
797 print (" mbits", bin(mbits.value), mbits.bits)
798 print (" pgbase", hex(pgbase.value), pgbase.bits)
799 addr = SelectableInt(0x1000, 64)
800 check = mem._segment_check(addr, mbits, shift)
801 print (" segment check", check)
802
803 print("walking tree")
804 addr = SelectableInt(testaddr,64)
805 # pgbase = None
806 mode = None
807 #mbits = None
808 shift = rts
809 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
810 print(" walking tree result", result)
811 print("should be", testresult)
812 self.assertEqual(result.value, expected,
813 "expected 0x%x got 0x%x" % (expected,
814 result.value))
815
816
817 def test_walk_tree_2(self):
818
819 # test address slightly different
820 testaddr = 0x1101
821 expected = 0x5001101
822
823 # starting prtbl
824 prtbl = 0x1000000
825
826 # set up dummy minimal ISACaller
827 spr = {'DSISR': SelectableInt(0, 64),
828 'DAR': SelectableInt(0, 64),
829 'PIDR': SelectableInt(0, 64),
830 'PRTBL': SelectableInt(prtbl, 64)
831 }
832 # set problem state == 0 (other unit tests, set to 1)
833 msr = SelectableInt(0, 64)
834 msr[MSRb.PR] = 0
835 class ISACaller: pass
836 caller = ISACaller()
837 caller.spr = spr
838 caller.msr = msr
839
840 shift = SelectableInt(5, 6)
841 mask = genmask(shift, 43)
842 print (" mask", bin(mask.value))
843
844 mem = Mem(row_bytes=8, initial_mem=testmem2)
845 mem = RADIX(mem, caller)
846 # -----------------------------------------------
847 # |/|RTS1|/| RPDB | RTS2 | RPDS |
848 # -----------------------------------------------
849 # |0|1 2|3|4 55|56 58|59 63|
850 data = SelectableInt(0, 64)
851 data[1:3] = 0b01
852 data[56:59] = 0b11
853 data[59:64] = 0b01101 # mask
854 data[55] = 1
855 (rts, mbits, pgbase) = mem._decode_prte(data)
856 print (" rts", bin(rts.value), rts.bits)
857 print (" mbits", bin(mbits.value), mbits.bits)
858 print (" pgbase", hex(pgbase.value), pgbase.bits)
859 addr = SelectableInt(0x1000, 64)
860 check = mem._segment_check(addr, mbits, shift)
861 print (" segment check", check)
862
863 print("walking tree")
864 addr = SelectableInt(testaddr,64)
865 # pgbase = None
866 mode = None
867 #mbits = None
868 shift = rts
869 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
870 print(" walking tree result", result)
871 print("should be", testresult)
872 self.assertEqual(result.value, expected,
873 "expected 0x%x got 0x%x" % (expected,
874 result.value))
875
876
877 if __name__ == '__main__':
878 unittest.main()