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experiment with alternative PID in radix mmu
[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 #from nmigen.back.pysim import Settle
17 from copy import copy
18 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from soc.decoder.helpers import exts, gtu, ltu, undefined
21 from soc.decoder.isa.mem import Mem
22 from soc.consts import MSRb # big-endian (PowerISA versions)
23
24 import math
25 import sys
26 import unittest
27
28 # very quick, TODO move to SelectableInt utils later
29 def genmask(shift, size):
30 res = SelectableInt(0, size)
31 for i in range(size):
32 if i < shift:
33 res[size-1-i] = SelectableInt(1, 1)
34 return res
35
36 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
37 # MSB is indexed **LOWEST** (sigh)
38 # from gem5 radixwalk.hh
39 # Bitfield<63> valid; 64 - (63 + 1) = 0
40 # Bitfield<62> leaf; 64 - (62 + 1) = 1
41
42 def rpte_valid(r):
43 return bool(r[0])
44
45 def rpte_leaf(r):
46 return bool(r[1])
47
48 ## Shift address bits 61--12 right by 0--47 bits and
49 ## supply the least significant 16 bits of the result.
50 def addrshift(addr,shift):
51 print("addrshift")
52 print(addr)
53 print(shift)
54 x = addr.value >> shift.value
55 return SelectableInt(x, 16)
56
57 def RTS2(data):
58 return data[56:59]
59
60 def RTS1(data):
61 return data[1:3]
62
63 def RTS(data):
64 zero = SelectableInt(0, 1)
65 return selectconcat(zero, RTS2(data), RTS1(data))
66
67 def NLB(x):
68 """
69 Next Level Base
70 right shifted by 8
71 """
72 return x[4:56] # python numbering end+1
73
74 def NLS(x):
75 """
76 Next Level Size (PATS and RPDS in same bits btw)
77 NLS >= 5
78 """
79 return x[59:64] # python numbering end+1
80
81 def RPDB(x):
82 """
83 Root Page Directory Base
84 power isa docs says 4:55 investigate
85 """
86 return x[8:56] # python numbering end+1
87
88 """
89 Get Root Page
90
91 //Accessing 2nd double word of partition table (pate1)
92 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
93 // PTCR Layout
94 // ====================================================
95 // -----------------------------------------------
96 // | /// | PATB | /// | PATS |
97 // -----------------------------------------------
98 // 0 4 51 52 58 59 63
99 // PATB[4:51] holds the base address of the Partition Table,
100 // right shifted by 12 bits.
101 // This is because the address of the Partition base is
102 // 4k aligned. Hence, the lower 12bits, which are always
103 // 0 are ommitted from the PTCR.
104 //
105 // Thus, The Partition Table Base is obtained by (PATB << 12)
106 //
107 // PATS represents the partition table size right-shifted by 12 bits.
108 // The minimal size of the partition table is 4k.
109 // Thus partition table size = (1 << PATS + 12).
110 //
111 // Partition Table
112 // ====================================================
113 // 0 PATE0 63 PATE1 127
114 // |----------------------|----------------------|
115 // | | |
116 // |----------------------|----------------------|
117 // | | |
118 // |----------------------|----------------------|
119 // | | | <-- effLPID
120 // |----------------------|----------------------|
121 // .
122 // .
123 // .
124 // |----------------------|----------------------|
125 // | | |
126 // |----------------------|----------------------|
127 //
128 // The effective LPID forms the index into the Partition Table.
129 //
130 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
131 // corresponding to that partition.
132 //
133 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
134 //
135 // PATE0 Layout
136 // -----------------------------------------------
137 // |1|RTS1|/| RPDB | RTS2 | RPDS |
138 // -----------------------------------------------
139 // 0 1 2 3 4 55 56 58 59 63
140 //
141 // HR[0] : For Radix Page table, first bit should be 1.
142 // RTS1[1:2] : Gives one fragment of the Radix treesize
143 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
144 // RTS = (RTS1 << 3 + RTS2) + 31.
145 //
146 // RPDB[4:55] = Root Page Directory Base.
147 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
148 // Thus, Root page directory size = 1 << (RPDS + 3).
149 // Note: RPDS >= 5.
150 //
151 // PATE1 Layout
152 // -----------------------------------------------
153 // |///| PRTB | // | PRTS |
154 // -----------------------------------------------
155 // 0 3 4 51 52 58 59 63
156 //
157 // PRTB[4:51] = Process Table Base. This is aligned to size.
158 // PRTS[59: 63] = Process Table Size right shifted by 12.
159 // Minimal size of the process table is 4k.
160 // Process Table Size = (1 << PRTS + 12).
161 // Note: PRTS <= 24.
162 //
163 // Computing the size aligned Process Table Base:
164 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
165 // Thus, the lower 12+PRTS bits of table_base will
166 // be zero.
167
168
169 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
170 //
171 // Process Table
172 // ==========================
173 // 0 PRTE0 63 PRTE1 127
174 // |----------------------|----------------------|
175 // | | |
176 // |----------------------|----------------------|
177 // | | |
178 // |----------------------|----------------------|
179 // | | | <-- effPID
180 // |----------------------|----------------------|
181 // .
182 // .
183 // .
184 // |----------------------|----------------------|
185 // | | |
186 // |----------------------|----------------------|
187 //
188 // The effective Process id (PID) forms the index into the Process Table.
189 //
190 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
191 // corresponding to that process
192 //
193 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
194 //
195 // PRTE0 Layout
196 // -----------------------------------------------
197 // |/|RTS1|/| RPDB | RTS2 | RPDS |
198 // -----------------------------------------------
199 // 0 1 2 3 4 55 56 58 59 63
200 //
201 // RTS1[1:2] : Gives one fragment of the Radix treesize
202 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
203 // RTS = (RTS1 << 3 + RTS2) << 31,
204 // since minimal Radix Tree size is 4G.
205 //
206 // RPDB = Root Page Directory Base.
207 // RPDS = Root Page Directory Size right shifted by 3.
208 // Thus, Root page directory size = RPDS << 3.
209 // Note: RPDS >= 5.
210 //
211 // PRTE1 Layout
212 // -----------------------------------------------
213 // | /// |
214 // -----------------------------------------------
215 // 0 63
216 // All bits are reserved.
217
218
219 """
220
221 testmem = {
222
223 0x10000: # PARTITION_TABLE_2 (not implemented yet)
224 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
225 0x800000000100000b,
226
227 0x30000: # RADIX_ROOT_PTE
228 # V = 1 L = 0 NLB = 0x400 NLS = 9
229 0x8000000000040009,
230 0x40000: # RADIX_SECOND_LEVEL
231 # V = 1 L = 1 SW = 0 RPN = 0
232 # R = 1 C = 1 ATT = 0 EAA 0x7
233 0xc000000000000187,
234
235 0x1000000: # PROCESS_TABLE_3
236 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
237 0x40000000000300ad,
238 }
239
240 # this one has a 2nd level RADIX with a RPN of 0x5000
241 testmem2 = {
242
243 0x10000: # PARTITION_TABLE_2 (not implemented yet)
244 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
245 0x800000000100000b,
246
247 0x30000: # RADIX_ROOT_PTE
248 # V = 1 L = 0 NLB = 0x400 NLS = 9
249 0x8000000000040009,
250 0x40000: # RADIX_SECOND_LEVEL
251 # V = 1 L = 1 SW = 0 RPN = 0x5000
252 # R = 1 C = 1 ATT = 0 EAA 0x7
253 0xc000000005000187,
254
255 0x1000000: # PROCESS_TABLE_3
256 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
257 0x40000000000300ad,
258 }
259
260 testresult = """
261 prtbl = 1000000
262 DCACHE GET 1000000 PROCESS_TABLE_3
263 DCACHE GET 30000 RADIX_ROOT_PTE V = 1 L = 0
264 DCACHE GET 40000 RADIX_SECOND_LEVEL V = 1 L = 1
265 DCACHE GET 10000 PARTITION_TABLE_2
266 translated done 1 err 0 badtree 0 addr 40000 pte 0
267 """
268
269 # see qemu/target/ppc/mmu-radix64.c for reference
270 class RADIX:
271 def __init__(self, mem, caller):
272 self.mem = mem
273 self.caller = caller
274 if caller is not None:
275 print("caller")
276 print(caller)
277 self.dsisr = self.caller.spr["DSISR"]
278 self.dar = self.caller.spr["DAR"]
279 self.pidr = self.caller.spr["PIDR"]
280 self.prtbl = self.caller.spr["PRTBL"]
281 self.msr = self.caller.msr
282
283 # cached page table stuff
284 self.pgtbl0 = 0
285 self.pt0_valid = False
286 self.pgtbl3 = 0
287 self.pt3_valid = False
288
289 def __call__(self, addr, sz):
290 val = self.ld(addr.value, sz, swap=False)
291 print("RADIX memread", addr, sz, val)
292 return SelectableInt(val, sz*8)
293
294 def ld(self, address, width=8, swap=True, check_in_mem=False,
295 instr_fetch=False):
296 print("RADIX: ld from addr 0x%x width %d" % (address, width))
297
298 priv = ~(self.msr[MSRb.PR].value) # problem-state ==> privileged
299 if instr_fetch:
300 mode = 'EXECUTE'
301 else:
302 mode = 'LOAD'
303 addr = SelectableInt(address, 64)
304 pte = self._walk_tree(addr, mode, priv)
305
306 if type(pte)==str:
307 print("error on load",pte)
308 return 0
309
310 # use pte to load from phys address
311 return self.mem.ld(pte.value, width, swap, check_in_mem)
312
313 # XXX set SPRs on error
314
315 # TODO implement
316 def st(self, address, v, width=8, swap=True):
317 print("RADIX: st to addr 0x%x width %d data %x" % (address, width, v))
318
319 priv = ~(self.msr[MSRb.PR].value) # problem-state ==> privileged
320 mode = 'STORE'
321 addr = SelectableInt(address, 64)
322 pte = self._walk_tree(addr, mode, priv)
323
324 # use pte to store at phys address
325 return self.mem.st(pte.value, v, width, swap)
326
327 # XXX set SPRs on error
328
329 def memassign(self, addr, sz, val):
330 print("memassign", addr, sz, val)
331 self.st(addr.value, val.value, sz, swap=False)
332
333 def _next_level(self, addr, check_in_mem):
334 # implement read access to mmu mem here
335
336 # DO NOT perform byte-swapping: load 8 bytes (that's the entry size)
337 value = self.mem.ld(addr.value, 8, False, check_in_mem)
338 if value is None:
339 return "address lookup %x not found" % addr.value
340 # assert(value is not None, "address lookup %x not found" % addr.value)
341
342 data = SelectableInt(value, 64) # convert to SelectableInt
343 print("addr", hex(addr.value))
344 print("value", hex(value))
345 return data;
346
347 def _walk_tree(self, addr, mode, priv=1):
348 """walk tree
349
350 // vaddr 64 Bit
351 // vaddr |-----------------------------------------------------|
352 // | Unused | Used |
353 // |-----------|-----------------------------------------|
354 // | 0000000 | usefulBits = X bits (typically 52) |
355 // |-----------|-----------------------------------------|
356 // | |<--Cursize---->| |
357 // | | Index | |
358 // | | into Page | |
359 // | | Directory | |
360 // |-----------------------------------------------------|
361 // | |
362 // V |
363 // PDE |---------------------------| |
364 // |V|L|//| NLB |///|NLS| |
365 // |---------------------------| |
366 // PDE = Page Directory Entry |
367 // [0] = V = Valid Bit |
368 // [1] = L = Leaf bit. If 0, then |
369 // [4:55] = NLB = Next Level Base |
370 // right shifted by 8 |
371 // [59:63] = NLS = Next Level Size |
372 // | NLS >= 5 |
373 // | V
374 // | |--------------------------|
375 // | | usfulBits = X-Cursize |
376 // | |--------------------------|
377 // |---------------------><--NLS-->| |
378 // | Index | |
379 // | into | |
380 // | PDE | |
381 // |--------------------------|
382 // |
383 // If the next PDE obtained by |
384 // (NLB << 8 + 8 * index) is a |
385 // nonleaf, then repeat the above. |
386 // |
387 // If the next PDE is a leaf, |
388 // then Leaf PDE structure is as |
389 // follows |
390 // |
391 // |
392 // Leaf PDE |
393 // |------------------------------| |----------------|
394 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
395 // |------------------------------| |----------------|
396 // [0] = V = Valid Bit |
397 // [1] = L = Leaf Bit = 1 if leaf |
398 // PDE |
399 // [2] = Sw = Sw bit 0. |
400 // [7:51] = RPN = Real Page Number, V
401 // real_page = RPN << 12 -------------> Logical OR
402 // [52:54] = Sw Bits 1:3 |
403 // [55] = R = Reference |
404 // [56] = C = Change V
405 // [58:59] = Att = Physical Address
406 // 0b00 = Normal Memory
407 // 0b01 = SAO
408 // 0b10 = Non Idenmpotent
409 // 0b11 = Tolerant I/O
410 // [60:63] = Encoded Access
411 // Authority
412 //
413 """
414 # get sprs
415 print("_walk_tree")
416 pidr = self.caller.spr["PIDR"]
417 prtbl = self.caller.spr["PRTBL"]
418 print("PIDR", pidr)
419 print("PRTBL", prtbl)
420 p = addr[55:63]
421 print("last 8 bits ----------")
422 print
423
424 # get address of root entry
425 # need to fetch process table entry
426 # v.shift := unsigned('0' & r.prtbl(4 downto 0));
427 shift = selectconcat(SelectableInt(0, 1), NLS(prtbl))
428 addr_next = self._get_prtable_addr(shift, prtbl, addr, pidr)
429 print("starting with prtable, addr_next", addr_next)
430
431 assert(addr_next.bits == 64)
432 #only for first unit tests assert(addr_next.value == 0x1000000)
433
434 # read an entry from prtable, decode PTRE
435 data = self._next_level(addr_next, check_in_mem=False)
436 print("pr_table", data)
437 pgtbl = data # this is cached in microwatt (as v.pgtbl3 / v.pgtbl0)
438 (rts, mbits, pgbase) = self._decode_prte(pgtbl)
439 print("pgbase", pgbase)
440
441 # WIP
442 if mbits == 0:
443 return "invalid"
444
445 # mask_size := mbits(4 downto 0);
446 mask_size = mbits[0:5]
447 assert(mask_size.bits == 5)
448 print("before segment check ==========")
449 print("mask_size:", bin(mask_size.value))
450 print("mbits:", bin(mbits.value))
451
452 print("calling segment_check")
453
454 shift = self._segment_check(addr, mask_size, shift)
455 print("shift", shift)
456
457 if isinstance(addr, str):
458 return addr
459 if isinstance(shift, str):
460 return shift
461
462 old_shift = shift
463
464 mask = mask_size
465
466 # walk tree
467 while True:
468 addrsh = addrshift(addr, shift)
469 print("addrsh",addrsh)
470
471 print("calling _get_pgtable_addr")
472 print(mask) #SelectableInt(value=0x9, bits=4)
473 print(pgbase) #SelectableInt(value=0x40000, bits=56)
474 print(shift) #SelectableInt(value=0x4, bits=16) #FIXME
475 addr_next = self._get_pgtable_addr(mask, pgbase, addrsh)
476 print("DONE addr_next", addr_next)
477
478 print("nextlevel----------------------------")
479 # read an entry
480 data = self._next_level(addr_next, check_in_mem=False)
481 valid = rpte_valid(data)
482 leaf = rpte_leaf(data)
483
484 print(" valid, leaf", valid, leaf)
485 if not valid:
486 return "invalid" # TODO: return error
487 if leaf:
488 print ("is leaf, checking perms")
489 ok = self._check_perms(data, priv, mode)
490 if ok == True: # data was ok, found phys address, return it?
491 paddr = self._get_pte(addrsh, addr, data)
492 print (" phys addr", hex(paddr.value))
493 return paddr
494 return ok # return the error code
495 else:
496 newlookup = self._new_lookup(data, shift, old_shift)
497 if isinstance(newlookup, str):
498 return newlookup
499 old_shift = shift # store old_shift before updating shift
500 shift, mask, pgbase = newlookup
501 print (" next level", shift, mask, pgbase)
502
503 def _get_pgbase(self, data):
504 """
505 v.pgbase := data(55 downto 8) & x"00"; NLB?
506 """
507 zero8 = SelectableInt(0, 8)
508 ret = selectconcat(data[8:56], zero8)
509 assert(ret.bits==56)
510 return ret
511
512 def _new_lookup(self, data, shift, old_shift):
513 """
514 mbits := unsigned('0' & data(4 downto 0));
515 if mbits < 5 or mbits > 16 or mbits > r.shift then
516 v.state := RADIX_FINISH;
517 v.badtree := '1'; -- throw error
518 else
519 v.shift := v.shift - mbits;
520 v.mask_size := mbits(4 downto 0);
521 v.pgbase := data(55 downto 8) & x"00"; NLB?
522 v.state := RADIX_LOOKUP; --> next level
523 end if;
524 """
525 mbits = selectconcat(SelectableInt(0, 1), NLS(data))
526 print("mbits=", mbits)
527 if mbits < 5 or mbits > 16 or mbits > old_shift:
528 print("badtree")
529 return "badtree"
530 # reduce shift (has to be done at same bitwidth)
531 shift = shift - mbits
532 assert mbits.bits == 6
533 mask_size = mbits[2:6] # get 4 LSBs from 6-bit (using MSB0 numbering)
534 pgbase = self._get_pgbase(data)
535 return shift, mask_size, pgbase
536
537 def _decode_prte(self, data):
538 """PRTE0 Layout
539 -----------------------------------------------
540 |/|RTS1|/| RPDB | RTS2 | RPDS |
541 -----------------------------------------------
542 0 1 2 3 4 55 56 58 59 63
543 """
544 # note that SelectableInt does big-endian! so the indices
545 # below *directly* match the spec, unlike microwatt which
546 # has to turn them around (to LE)
547 rts, mbits = self._get_rts_nls(data)
548 pgbase = self._get_pgbase(data)
549
550 return (rts, mbits, pgbase)
551
552 def _get_rts_nls(self, data):
553 # rts = shift = unsigned('0' & data(62 downto 61) & data(7 downto 5));
554 # RTS1 RTS2
555 rts = RTS(data)
556 assert(rts.bits == 6) # variable rts : unsigned(5 downto 0);
557 print("shift", rts)
558
559 # mbits := unsigned('0' & data(4 downto 0));
560 mbits = selectconcat(SelectableInt(0, 1), NLS(data))
561 assert(mbits.bits == 6) #variable mbits : unsigned(5 downto 0);
562
563 return rts, mbits
564
565 def _segment_check(self, addr, mask_size, shift):
566 """checks segment valid
567 mbits := '0' & r.mask_size;
568 v.shift := r.shift + (31 - 12) - mbits;
569 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
570 if r.addr(63) /= r.addr(62) or nonzero = '1' then
571 v.state := RADIX_FINISH;
572 v.segerror := '1';
573 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
574 v.state := RADIX_FINISH;
575 v.badtree := '1';
576 else
577 v.state := RADIX_LOOKUP;
578 """
579 # note that SelectableInt does big-endian! so the indices
580 # below *directly* match the spec, unlike microwatt which
581 # has to turn them around (to LE)
582 mbits = selectconcat(SelectableInt(0,1), mask_size)
583 mask = genmask(shift, 44)
584 nonzero = addr[2:33] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
585 print ("RADIX _segment_check nonzero", bin(nonzero.value))
586 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
587 if addr[0] != addr[1] or nonzero != 0:
588 return "segerror"
589 limit = shift + (31 - 12)
590 if mbits.value < 5 or mbits.value > 16 or mbits.value > limit.value:
591 return "badtree"
592 new_shift = SelectableInt(limit.value - mbits.value, shift.bits)
593 # TODO verify that returned result is correct
594 return new_shift
595
596 def _check_perms(self, data, priv, mode):
597 """check page permissions
598 // Leaf PDE |
599 // |------------------------------| |----------------|
600 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
601 // |------------------------------| |----------------|
602 // [0] = V = Valid Bit |
603 // [1] = L = Leaf Bit = 1 if leaf |
604 // PDE |
605 // [2] = Sw = Sw bit 0. |
606 // [7:51] = RPN = Real Page Number, V
607 // real_page = RPN << 12 -------------> Logical OR
608 // [52:54] = Sw Bits 1:3 |
609 // [55] = R = Reference |
610 // [56] = C = Change V
611 // [58:59] = Att = Physical Address
612 // 0b00 = Normal Memory
613 // 0b01 = SAO
614 // 0b10 = Non Idenmpotent
615 // 0b11 = Tolerant I/O
616 // [60:63] = Encoded Access
617 // Authority
618 //
619 -- test leaf bit
620 -- check permissions and RC bits
621 perm_ok := '0';
622 if r.priv = '1' or data(3) = '0' then
623 if r.iside = '0' then
624 perm_ok := data(1) or (data(2) and not r.store);
625 else
626 -- no IAMR, so no KUEP support for now
627 -- deny execute permission if cache inhibited
628 perm_ok := data(0) and not data(5);
629 end if;
630 end if;
631 rc_ok := data(8) and (data(7) or not r.store);
632 if perm_ok = '1' and rc_ok = '1' then
633 v.state := RADIX_LOAD_TLB;
634 else
635 v.state := RADIX_FINISH;
636 v.perm_err := not perm_ok;
637 -- permission error takes precedence over RC error
638 v.rc_error := perm_ok;
639 end if;
640 """
641 # decode mode into something that matches microwatt equivalent code
642 instr_fetch, store = 0, 0
643 if mode == 'STORE':
644 store = 1
645 if mode == 'EXECUTE':
646 inst_fetch = 1
647
648 # check permissions and RC bits
649 perm_ok = 0
650 if priv == 1 or data[60] == 0:
651 if instr_fetch == 0:
652 perm_ok = data[62] | (data[61] & (store == 0))
653 # no IAMR, so no KUEP support for now
654 # deny execute permission if cache inhibited
655 perm_ok = data[63] & ~data[58]
656 rc_ok = data[55] & (data[56] | (store == 0))
657 if perm_ok == 1 and rc_ok == 1:
658 return True
659
660 return "perm_err" if perm_ok == 0 else "rc_err"
661
662 def _get_prtable_addr(self, shift, prtbl, addr, pid):
663 """
664 if r.addr(63) = '1' then
665 effpid := x"00000000";
666 else
667 effpid := r.pid;
668 end if;
669 x"00" & r.prtbl(55 downto 36) &
670 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
671 (effpid(31 downto 8) and finalmask(23 downto 0))) &
672 effpid(7 downto 0) & "0000";
673 """
674 finalmask = genmask(shift, 44)
675 finalmask24 = finalmask[20:44]
676 print ("_get_prtable_addr", shift, prtbl, addr, pid,
677 bin(finalmask24.value))
678 if addr[0].value == 1:
679 effpid = SelectableInt(0, 32)
680 else:
681 effpid = pid #self.pid # TODO, check on this
682 zero8 = SelectableInt(0, 8)
683 zero4 = SelectableInt(0, 4)
684 res = selectconcat(zero8,
685 prtbl[8:28], #
686 (prtbl[28:52] & ~finalmask24) | #
687 (effpid[0:24] & finalmask24), #
688 effpid[24:32],
689 zero4
690 )
691 return res
692
693 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
694 """
695 x"00" & r.pgbase(55 downto 19) &
696 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
697 "000";
698 """
699 print("pgbase",pgbase)
700 assert(pgbase.bits==56)
701 mask16 = genmask(mask_size+5, 16)
702 zero8 = SelectableInt(0, 8)
703 zero3 = SelectableInt(0, 3)
704 res = selectconcat(zero8,
705 pgbase[0:37],
706 (pgbase[37:53] & ~mask16) |
707 (addrsh & mask16),
708 zero3
709 )
710 return res
711
712 def _get_pte(self, shift, addr, pde):
713 """
714 x"00" &
715 ((r.pde(55 downto 12) and not finalmask) or
716 (r.addr(55 downto 12) and finalmask))
717 & r.pde(11 downto 0);
718 """
719 shift.value = 12
720 finalmask = genmask(shift, 44)
721 zero8 = SelectableInt(0, 8)
722 rpn = pde[8:52] # RPN = Real Page Number
723 abits = addr[8:52] # non-masked address bits
724 print(" get_pte RPN", hex(rpn.value))
725 print(" abits", hex(abits.value))
726 print(" shift", shift.value)
727 print(" finalmask", bin(finalmask.value))
728 res = selectconcat(zero8,
729 (rpn & ~finalmask) | #
730 (abits & finalmask), #
731 addr[52:64],
732 )
733 return res
734
735
736 class TestRadixMMU(unittest.TestCase):
737
738 def test_genmask(self):
739 shift = SelectableInt(5, 6)
740 mask = genmask(shift, 43)
741 print (" mask", bin(mask.value))
742
743 self.assertEqual(mask.value, 0b11111, "mask should be 5 1s")
744
745 def test_RPDB(self):
746 inp = SelectableInt(0x40000000000300ad, 64)
747
748 rtdb = RPDB(inp)
749 print("rtdb",rtdb,bin(rtdb.value))
750 self.assertEqual(rtdb.value,0x300,"rtdb should be 0x300")
751
752 result = selectconcat(rtdb,SelectableInt(0,8))
753 print("result",result)
754
755 def test_get_pgtable_addr(self):
756
757 mem = None
758 caller = None
759 dut = RADIX(mem, caller)
760
761 mask_size=4
762 pgbase = SelectableInt(0,56)
763 addrsh = SelectableInt(0,16)
764 ret = dut._get_pgtable_addr(mask_size, pgbase, addrsh)
765 print("ret=", ret)
766 self.assertEqual(ret, 0, "pgtbl_addr should be 0")
767
768 def test_walk_tree_1(self):
769
770 # test address as in
771 # https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/radix_walk_example.txt#L65
772 testaddr = 0x1000
773 expected = 0x1000
774
775 # starting prtbl
776 prtbl = 0x1000000
777
778 # set up dummy minimal ISACaller
779 spr = {'DSISR': SelectableInt(0, 64),
780 'DAR': SelectableInt(0, 64),
781 'PIDR': SelectableInt(0, 64),
782 'PRTBL': SelectableInt(prtbl, 64)
783 }
784 # set problem state == 0 (other unit tests, set to 1)
785 msr = SelectableInt(0, 64)
786 msr[MSRb.PR] = 0
787 class ISACaller: pass
788 caller = ISACaller()
789 caller.spr = spr
790 caller.msr = msr
791
792 shift = SelectableInt(5, 6)
793 mask = genmask(shift, 43)
794 print (" mask", bin(mask.value))
795
796 mem = Mem(row_bytes=8, initial_mem=testmem)
797 mem = RADIX(mem, caller)
798 # -----------------------------------------------
799 # |/|RTS1|/| RPDB | RTS2 | RPDS |
800 # -----------------------------------------------
801 # |0|1 2|3|4 55|56 58|59 63|
802 data = SelectableInt(0, 64)
803 data[1:3] = 0b01
804 data[56:59] = 0b11
805 data[59:64] = 0b01101 # mask
806 data[55] = 1
807 (rts, mbits, pgbase) = mem._decode_prte(data)
808 print (" rts", bin(rts.value), rts.bits)
809 print (" mbits", bin(mbits.value), mbits.bits)
810 print (" pgbase", hex(pgbase.value), pgbase.bits)
811 addr = SelectableInt(0x1000, 64)
812 check = mem._segment_check(addr, mbits, shift)
813 print (" segment check", check)
814
815 print("walking tree")
816 addr = SelectableInt(testaddr,64)
817 # pgbase = None
818 mode = None
819 #mbits = None
820 shift = rts
821 result = mem._walk_tree(addr, mode)
822 print(" walking tree result", result)
823 print("should be", testresult)
824 self.assertEqual(result.value, expected,
825 "expected 0x%x got 0x%x" % (expected,
826 result.value))
827
828 def test_walk_tree_2(self):
829
830 # test address slightly different
831 testaddr = 0x1101
832 expected = 0x5001101
833
834 # starting prtbl
835 prtbl = 0x1000000
836
837 # set up dummy minimal ISACaller
838 spr = {'DSISR': SelectableInt(0, 64),
839 'DAR': SelectableInt(0, 64),
840 'PIDR': SelectableInt(0, 64),
841 'PRTBL': SelectableInt(prtbl, 64)
842 }
843 # set problem state == 0 (other unit tests, set to 1)
844 msr = SelectableInt(0, 64)
845 msr[MSRb.PR] = 0
846 class ISACaller: pass
847 caller = ISACaller()
848 caller.spr = spr
849 caller.msr = msr
850
851 shift = SelectableInt(5, 6)
852 mask = genmask(shift, 43)
853 print (" mask", bin(mask.value))
854
855 mem = Mem(row_bytes=8, initial_mem=testmem2)
856 mem = RADIX(mem, caller)
857 # -----------------------------------------------
858 # |/|RTS1|/| RPDB | RTS2 | RPDS |
859 # -----------------------------------------------
860 # |0|1 2|3|4 55|56 58|59 63|
861 data = SelectableInt(0, 64)
862 data[1:3] = 0b01
863 data[56:59] = 0b11
864 data[59:64] = 0b01101 # mask
865 data[55] = 1
866 (rts, mbits, pgbase) = mem._decode_prte(data)
867 print (" rts", bin(rts.value), rts.bits)
868 print (" mbits", bin(mbits.value), mbits.bits)
869 print (" pgbase", hex(pgbase.value), pgbase.bits)
870 addr = SelectableInt(0x1000, 64)
871 check = mem._segment_check(addr, mbits, shift)
872 print (" segment check", check)
873
874 print("walking tree")
875 addr = SelectableInt(testaddr,64)
876 # pgbase = None
877 mode = None
878 #mbits = None
879 shift = rts
880 result = mem._walk_tree(addr, mode)
881 print(" walking tree result", result)
882 print("should be", testresult)
883 self.assertEqual(result.value, expected,
884 "expected 0x%x got 0x%x" % (expected,
885 result.value))
886
887
888 if __name__ == '__main__':
889 unittest.main()