1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
16 from nmigen
.back
.pysim
import Settle
18 from soc
.decoder
.selectable_int
import (FieldSelectableInt
, SelectableInt
,
20 from soc
.decoder
.helpers
import exts
, gtu
, ltu
, undefined
21 from soc
.decoder
.isa
.mem
import Mem
22 from soc
.consts
import MSRb
# big-endian (PowerISA versions)
28 # very quick, TODO move to SelectableInt utils later
29 def genmask(shift
, size
):
30 res
= SelectableInt(0, size
)
33 res
[size
-1-i
] = SelectableInt(1, 1)
36 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
37 # MSB is indexed **LOWEST** (sigh)
38 # from gem5 radixwalk.hh
39 # Bitfield<63> valid; 64 - (63 + 1) = 0
40 # Bitfield<62> leaf; 64 - (62 + 1) = 1
48 ## Shift address bits 61--12 right by 0--47 bits and
49 ## supply the least significant 16 bits of the result.
50 def addrshift(addr
,shift
):
51 x
= addr
.value
>> shift
.value
52 return SelectableInt(x
,16)
71 //Accessing 2nd double word of partition table (pate1)
72 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
74 // ====================================================
75 // -----------------------------------------------
76 // | /// | PATB | /// | PATS |
77 // -----------------------------------------------
79 // PATB[4:51] holds the base address of the Partition Table,
80 // right shifted by 12 bits.
81 // This is because the address of the Partition base is
82 // 4k aligned. Hence, the lower 12bits, which are always
83 // 0 are ommitted from the PTCR.
85 // Thus, The Partition Table Base is obtained by (PATB << 12)
87 // PATS represents the partition table size right-shifted by 12 bits.
88 // The minimal size of the partition table is 4k.
89 // Thus partition table size = (1 << PATS + 12).
92 // ====================================================
93 // 0 PATE0 63 PATE1 127
94 // |----------------------|----------------------|
96 // |----------------------|----------------------|
98 // |----------------------|----------------------|
100 // |----------------------|----------------------|
104 // |----------------------|----------------------|
106 // |----------------------|----------------------|
108 // The effective LPID forms the index into the Partition Table.
110 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
111 // corresponding to that partition.
113 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
116 // -----------------------------------------------
117 // |1|RTS1|/| RPDB | RTS2 | RPDS |
118 // -----------------------------------------------
119 // 0 1 2 3 4 55 56 58 59 63
121 // HR[0] : For Radix Page table, first bit should be 1.
122 // RTS1[1:2] : Gives one fragment of the Radix treesize
123 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
124 // RTS = (RTS1 << 3 + RTS2) + 31.
126 // RPDB[4:55] = Root Page Directory Base.
127 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
128 // Thus, Root page directory size = 1 << (RPDS + 3).
132 // -----------------------------------------------
133 // |///| PRTB | // | PRTS |
134 // -----------------------------------------------
135 // 0 3 4 51 52 58 59 63
137 // PRTB[4:51] = Process Table Base. This is aligned to size.
138 // PRTS[59: 63] = Process Table Size right shifted by 12.
139 // Minimal size of the process table is 4k.
140 // Process Table Size = (1 << PRTS + 12).
143 // Computing the size aligned Process Table Base:
144 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
145 // Thus, the lower 12+PRTS bits of table_base will
149 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
152 // ==========================
153 // 0 PRTE0 63 PRTE1 127
154 // |----------------------|----------------------|
156 // |----------------------|----------------------|
158 // |----------------------|----------------------|
160 // |----------------------|----------------------|
164 // |----------------------|----------------------|
166 // |----------------------|----------------------|
168 // The effective Process id (PID) forms the index into the Process Table.
170 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
171 // corresponding to that process
173 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
176 // -----------------------------------------------
177 // |/|RTS1|/| RPDB | RTS2 | RPDS |
178 // -----------------------------------------------
179 // 0 1 2 3 4 55 56 58 59 63
181 // RTS1[1:2] : Gives one fragment of the Radix treesize
182 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
183 // RTS = (RTS1 << 3 + RTS2) << 31,
184 // since minimal Radix Tree size is 4G.
186 // RPDB = Root Page Directory Base.
187 // RPDS = Root Page Directory Size right shifted by 3.
188 // Thus, Root page directory size = RPDS << 3.
192 // -----------------------------------------------
194 // -----------------------------------------------
196 // All bits are reserved.
203 0x10000: # PARTITION_TABLE_2 (not implemented yet)
204 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
207 0x30000: # RADIX_ROOT_PTE
208 # V = 1 L = 0 NLB = 0x400 NLS = 9
210 0x40000: # RADIX_SECOND_LEVEL
211 # V = 1 L = 1 SW = 0 RPN = 0
212 # R = 1 C = 1 ATT = 0 EAA 0x7
215 0x1000000: # PROCESS_TABLE_3
216 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
220 # this one has a 2nd level RADIX with a RPN of 0x5000
223 0x10000: # PARTITION_TABLE_2 (not implemented yet)
224 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
227 0x30000: # RADIX_ROOT_PTE
228 # V = 1 L = 0 NLB = 0x400 NLS = 9
230 0x40000: # RADIX_SECOND_LEVEL
231 # V = 1 L = 1 SW = 0 RPN = 0x5000
232 # R = 1 C = 1 ATT = 0 EAA 0x7
235 0x1000000: # PROCESS_TABLE_3
236 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
243 DCACHE GET 1000000 PROCESS_TABLE_3
244 DCACHE GET 30000 RADIX_ROOT_PTE V = 1 L = 0
245 DCACHE GET 40000 RADIX_SECOND_LEVEL V = 1 L = 1
246 DCACHE GET 10000 PARTITION_TABLE_2
247 translated done 1 err 0 badtree 0 addr 40000 pte 0
250 # see qemu/target/ppc/mmu-radix64.c for reference
252 def __init__(self
, mem
, caller
):
255 if caller
is not None:
256 self
.dsisr
= self
.caller
.spr
["DSISR"]
257 self
.dar
= self
.caller
.spr
["DAR"]
258 self
.pidr
= self
.caller
.spr
["PIDR"]
259 self
.prtbl
= self
.caller
.spr
["PRTBL"]
260 self
.msr
= self
.caller
.msr
262 # cached page table stuff
264 self
.pt0_valid
= False
266 self
.pt3_valid
= False
268 def __call__(self
, addr
, sz
):
269 val
= self
.ld(addr
.value
, sz
, swap
=False)
270 print("RADIX memread", addr
, sz
, val
)
271 return SelectableInt(val
, sz
*8)
273 def ld(self
, address
, width
=8, swap
=True, check_in_mem
=False,
275 print("RADIX: ld from addr 0x%x width %d" % (address
, width
))
277 priv
= ~
(self
.msr(MSR_PR
).value
) # problem-state ==> privileged
282 addr
= SelectableInt(address
, 64)
283 (shift
, mbits
, pgbase
) = self
._decode
_prte
(addr
)
284 #shift = SelectableInt(0, 32)
286 pte
= self
._walk
_tree
(addr
, pgbase
, mode
, mbits
, shift
, priv
)
288 # use pte to load from phys address
289 return self
.mem
.ld(pte
.value
, width
, swap
, check_in_mem
)
291 # XXX set SPRs on error
294 def st(self
, address
, v
, width
=8, swap
=True):
295 print("RADIX: st to addr 0x%x width %d data %x" % (address
, width
, v
))
297 priv
= ~
(self
.msr(MSR_PR
).value
) # problem-state ==> privileged
299 addr
= SelectableInt(address
, 64)
300 (shift
, mbits
, pgbase
) = self
._decode
_prte
(addr
)
301 pte
= self
._walk
_tree
(addr
, pgbase
, mode
, mbits
, shift
, priv
)
303 # use pte to store at phys address
304 return self
.mem
.st(pte
.value
, v
, width
, swap
)
306 # XXX set SPRs on error
308 def memassign(self
, addr
, sz
, val
):
309 print("memassign", addr
, sz
, val
)
310 self
.st(addr
.value
, val
.value
, sz
, swap
=False)
312 def _next_level(self
, addr
, entry_width
, swap
, check_in_mem
):
313 # implement read access to mmu mem here
315 # DO NOT perform byte-swapping: load 8 bytes (that's the entry size)
316 value
= self
.mem
.ld(addr
.value
, 8, False, check_in_mem
)
317 assert(value
is not None, "address lookup %x not found" % addr
.value
)
319 print("addr", hex(addr
.value
))
320 data
= SelectableInt(value
, 64) # convert to SelectableInt
321 print("value", hex(value
))
325 def _walk_tree(self
, addr
, pgbase
, mode
, mbits
, shift
, priv
=1):
329 // vaddr |-----------------------------------------------------|
331 // |-----------|-----------------------------------------|
332 // | 0000000 | usefulBits = X bits (typically 52) |
333 // |-----------|-----------------------------------------|
334 // | |<--Cursize---->| |
338 // |-----------------------------------------------------|
341 // PDE |---------------------------| |
342 // |V|L|//| NLB |///|NLS| |
343 // |---------------------------| |
344 // PDE = Page Directory Entry |
345 // [0] = V = Valid Bit |
346 // [1] = L = Leaf bit. If 0, then |
347 // [4:55] = NLB = Next Level Base |
348 // right shifted by 8 |
349 // [59:63] = NLS = Next Level Size |
352 // | |--------------------------|
353 // | | usfulBits = X-Cursize |
354 // | |--------------------------|
355 // |---------------------><--NLS-->| |
359 // |--------------------------|
361 // If the next PDE obtained by |
362 // (NLB << 8 + 8 * index) is a |
363 // nonleaf, then repeat the above. |
365 // If the next PDE is a leaf, |
366 // then Leaf PDE structure is as |
371 // |------------------------------| |----------------|
372 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
373 // |------------------------------| |----------------|
374 // [0] = V = Valid Bit |
375 // [1] = L = Leaf Bit = 1 if leaf |
377 // [2] = Sw = Sw bit 0. |
378 // [7:51] = RPN = Real Page Number, V
379 // real_page = RPN << 12 -------------> Logical OR
380 // [52:54] = Sw Bits 1:3 |
381 // [55] = R = Reference |
382 // [56] = C = Change V
383 // [58:59] = Att = Physical Address
384 // 0b00 = Normal Memory
386 // 0b10 = Non Idenmpotent
387 // 0b11 = Tolerant I/O
388 // [60:63] = Encoded Access
394 pidr
= self
.caller
.spr
["PIDR"]
395 prtbl
= self
.caller
.spr
["PRTBL"]
399 print("last 8 bits ----------")
402 # get address of root entry
403 shift
= selectconcat(SelectableInt(0,1), prtbl
[58:63]) # TODO verify
404 addr_next
= self
._get
_prtable
_addr
(shift
, prtbl
, addr
, pidr
)
405 print("starting with prtable, addr_next",addr_next
)
407 assert(addr_next
.bits
== 64)
408 assert(addr_next
.value
== 0x1000000) #TODO
410 # read an entry from prtable
414 data
= self
._next
_level
(addr_next
, entry_width
, swap
, check_in_mem
)
415 print("pr_table",data
)
417 # rts = shift = unsigned('0' & data(62 downto 61) & data(7 downto 5));
418 shift
= selectconcat(SelectableInt(0,1), data
[1:3], data
[55:58])
419 assert(shift
.bits
==6) # variable rts : unsigned(5 downto 0);
422 # mbits := unsigned('0' & data(4 downto 0));
423 mbits
= selectconcat(SelectableInt(0,1), data
[58:63])
424 assert(mbits
.bits
==6) #variable mbits : unsigned(5 downto 0);
430 # mask_size := mbits(4 downto 0);
431 mask_size
= mbits
[0:5];
432 assert(mask_size
.bits
==5)
433 print("before segment check ==========")
434 print("mask_size:",bin(mask_size
.value
))
435 print("mbits:",bin(mbits
.value
))
437 print("calling segment_check")
439 mbits
= selectconcat(SelectableInt(0,1), mask_size
)
440 new_shift
= self
._segment
_check
(addr
, mbits
, shift
)
441 print("new_shift",new_shift
)
446 #addr_next = SelectableInt(0x30000,64) # radix root for testing
447 # this needs to be calculated using the code above
449 # walk tree starts on prtbl
451 print("nextlevel----------------------------")
457 data
= self
._next
_level
(addr_next
, entry_width
, swap
, check_in_mem
)
458 valid
= rpte_valid(data
)
459 leaf
= rpte_leaf(data
)
461 print(" valid, leaf", valid
, leaf
)
463 return "invalid" # TODO: return error
465 print ("is leaf, checking perms")
466 ok
= self
._check
_perms
(data
, priv
, mode
)
467 if ok
== True: # data was ok, found phys address, return it?
468 paddr
= self
._get
_pte
(addrsh
, addr
, data
)
469 print (" phys addr", hex(paddr
.value
))
471 return ok
# return the error code
473 newlookup
= self
._new
_lookup
(data
, shift
)
474 if newlookup
== 'badtree':
476 shift
, mask
, pgbase
= newlookup
477 print (" next level", shift
, mask
, pgbase
)
478 shift
= SelectableInt(shift
.value
,16) #THIS is wrong !!!
479 print("calling _get_pgtable_addr")
480 print(mask
) #SelectableInt(value=0x9, bits=4)
481 print(pgbase
) #SelectableInt(value=0x40000, bits=56)
482 print(shift
) #SelectableInt(value=0x4, bits=16) #FIXME
483 pgbase
= SelectableInt(pgbase
.value
, 64)
484 addrsh
= addrshift(addr
,shift
)
485 addr_next
= self
._get
_pgtable
_addr
(mask
, pgbase
, addrsh
)
486 print("addr_next",addr_next
)
487 print("addrsh",addrsh
)
489 def _new_lookup(self
, data
, shift
):
491 mbits := unsigned('0' & data(4 downto 0));
492 if mbits < 5 or mbits > 16 or mbits > r.shift then
493 v.state := RADIX_FINISH;
494 v.badtree := '1'; -- throw error
496 v.shift := v.shift - mbits;
497 v.mask_size := mbits(4 downto 0);
498 v.pgbase := data(55 downto 8) & x"00"; NLB?
499 v.state := RADIX_LOOKUP; --> next level
503 print("mbits=", mbits
)
504 if mbits
< 5 or mbits
> 16: #fixme compare with r.shift
507 # reduce shift (has to be done at same bitwidth)
508 shift
= shift
- selectconcat(SelectableInt(0, 1), mbits
)
509 mask_size
= mbits
[1:5] # get 4 LSBs
510 pgbase
= selectconcat(data
[8:56], SelectableInt(0, 8)) # shift up 8
511 return shift
, mask_size
, pgbase
513 def _decode_prte(self
, data
):
515 -----------------------------------------------
516 |/|RTS1|/| RPDB | RTS2 | RPDS |
517 -----------------------------------------------
518 0 1 2 3 4 55 56 58 59 63
520 # note that SelectableInt does big-endian! so the indices
521 # below *directly* match the spec, unlike microwatt which
522 # has to turn them around (to LE)
523 zero
= SelectableInt(0, 1)
524 rts
= selectconcat(zero
,
528 masksize
= data
[59:64] # RPDS
529 mbits
= selectconcat(zero
, masksize
)
530 pgbase
= selectconcat(data
[8:56], # part of RPDB
531 SelectableInt(0, 16),)
533 return (rts
, mbits
, pgbase
)
535 def _segment_check(self
, addr
, mbits
, shift
):
536 """checks segment valid
537 mbits := '0' & r.mask_size;
538 v.shift := r.shift + (31 - 12) - mbits;
539 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
540 if r.addr(63) /= r.addr(62) or nonzero = '1' then
541 v.state := RADIX_FINISH;
543 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
544 v.state := RADIX_FINISH;
547 v.state := RADIX_LOOKUP;
549 # note that SelectableInt does big-endian! so the indices
550 # below *directly* match the spec, unlike microwatt which
551 # has to turn them around (to LE)
552 mask
= genmask(shift
, 44)
553 nonzero
= addr
[2:33] & mask
[13:44] # mask 31 LSBs (BE numbered 13:44)
554 print ("RADIX _segment_check nonzero", bin(nonzero
.value
))
555 print ("RADIX _segment_check addr[0-1]", addr
[0].value
, addr
[1].value
)
556 if addr
[0] != addr
[1] or nonzero
!= 0:
558 limit
= shift
+ (31 - 12)
559 if mbits
.value
< 5 or mbits
.value
> 16 or mbits
.value
> limit
.value
:
560 return "badtree mbits="+str(mbits
.value
)+" limit="+str(limit
.value
)
561 new_shift
= shift
+ (31 - 12) - mbits
562 # TODO verify that returned result is correct
565 def _check_perms(self
, data
, priv
, mode
):
566 """check page permissions
568 // |------------------------------| |----------------|
569 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
570 // |------------------------------| |----------------|
571 // [0] = V = Valid Bit |
572 // [1] = L = Leaf Bit = 1 if leaf |
574 // [2] = Sw = Sw bit 0. |
575 // [7:51] = RPN = Real Page Number, V
576 // real_page = RPN << 12 -------------> Logical OR
577 // [52:54] = Sw Bits 1:3 |
578 // [55] = R = Reference |
579 // [56] = C = Change V
580 // [58:59] = Att = Physical Address
581 // 0b00 = Normal Memory
583 // 0b10 = Non Idenmpotent
584 // 0b11 = Tolerant I/O
585 // [60:63] = Encoded Access
589 -- check permissions and RC bits
591 if r.priv = '1' or data(3) = '0' then
592 if r.iside = '0' then
593 perm_ok := data(1) or (data(2) and not r.store);
595 -- no IAMR, so no KUEP support for now
596 -- deny execute permission if cache inhibited
597 perm_ok := data(0) and not data(5);
600 rc_ok := data(8) and (data(7) or not r.store);
601 if perm_ok = '1' and rc_ok = '1' then
602 v.state := RADIX_LOAD_TLB;
604 v.state := RADIX_FINISH;
605 v.perm_err := not perm_ok;
606 -- permission error takes precedence over RC error
607 v.rc_error := perm_ok;
610 # decode mode into something that matches microwatt equivalent code
611 instr_fetch
, store
= 0, 0
614 if mode
== 'EXECUTE':
617 # check permissions and RC bits
619 if priv
== 1 or data
[60] == 0:
621 perm_ok
= data
[62] |
(data
[61] & (store
== 0))
622 # no IAMR, so no KUEP support for now
623 # deny execute permission if cache inhibited
624 perm_ok
= data
[63] & ~data
[58]
625 rc_ok
= data
[55] & (data
[56] |
(store
== 0))
626 if perm_ok
== 1 and rc_ok
== 1:
629 return "perm_err" if perm_ok
== 0 else "rc_err"
631 def _get_prtable_addr(self
, shift
, prtbl
, addr
, pid
):
633 if r.addr(63) = '1' then
634 effpid := x"00000000";
638 x"00" & r.prtbl(55 downto 36) &
639 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
640 (effpid(31 downto 8) and finalmask(23 downto 0))) &
641 effpid(7 downto 0) & "0000";
643 print ("_get_prtable_addr", shift
, prtbl
, addr
, pid
)
644 finalmask
= genmask(shift
, 44)
645 finalmask24
= finalmask
[20:44]
646 if addr
[0].value
== 1:
647 effpid
= SelectableInt(0, 32)
649 effpid
= pid
#self.pid # TODO, check on this
650 zero8
= SelectableInt(0, 8)
651 zero4
= SelectableInt(0, 4)
652 res
= selectconcat(zero8
,
654 (prtbl
[28:52] & ~finalmask24
) |
#
655 (effpid
[0:24] & finalmask24
), #
661 def _get_pgtable_addr(self
, mask_size
, pgbase
, addrsh
):
663 x"00" & r.pgbase(55 downto 19) &
664 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
667 mask16
= genmask(mask_size
+5, 16)
668 zero8
= SelectableInt(0, 8)
669 zero3
= SelectableInt(0, 3)
670 res
= selectconcat(zero8
,
672 (pgbase
[45:61] & ~mask16
) |
#
678 def _get_pte(self
, shift
, addr
, pde
):
681 ((r.pde(55 downto 12) and not finalmask) or
682 (r.addr(55 downto 12) and finalmask))
683 & r.pde(11 downto 0);
686 finalmask
= genmask(shift
, 44)
687 zero8
= SelectableInt(0, 8)
688 rpn
= pde
[8:52] # RPN = Real Page Number
689 abits
= addr
[8:52] # non-masked address bits
690 print(" get_pte RPN", hex(rpn
.value
))
691 print(" abits", hex(abits
.value
))
692 print(" shift", shift
.value
)
693 print(" finalmask", bin(finalmask
.value
))
694 res
= selectconcat(zero8
,
695 (rpn
& ~finalmask
) |
#
696 (abits
& finalmask
), #
701 class TestRadixMMU(unittest
.TestCase
):
703 def tst_genmask(self
):
704 shift
= SelectableInt(5, 6)
705 mask
= genmask(shift
, 43)
706 print (" mask", bin(mask
.value
))
708 self
.assertEqual(mask
.value
, 0b11111, "mask should be 5 1s")
710 def tst_get_pgtable_addr(self
):
714 dut
= RADIX(mem
, caller
)
717 pgbase
= SelectableInt(0,64)
718 addrsh
= SelectableInt(0,16)
719 ret
= dut
._get
_pgtable
_addr
(mask_size
, pgbase
, addrsh
)
721 self
.assertEqual(ret
, 0, "pgtbl_addr should be 0")
723 def test_walk_tree_1(self
):
726 # https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/radix_walk_example.txt#L65
733 # set up dummy minimal ISACaller
734 spr
= {'DSISR': SelectableInt(0, 64),
735 'DAR': SelectableInt(0, 64),
736 'PIDR': SelectableInt(0, 64),
737 'PRTBL': SelectableInt(prtbl
, 64)
739 # set problem state == 0 (other unit tests, set to 1)
740 msr
= SelectableInt(0, 64)
742 class ISACaller
: pass
747 shift
= SelectableInt(5, 6)
748 mask
= genmask(shift
, 43)
749 print (" mask", bin(mask
.value
))
751 mem
= Mem(row_bytes
=8, initial_mem
=testmem
)
752 mem
= RADIX(mem
, caller
)
753 # -----------------------------------------------
754 # |/|RTS1|/| RPDB | RTS2 | RPDS |
755 # -----------------------------------------------
756 # |0|1 2|3|4 55|56 58|59 63|
757 data
= SelectableInt(0, 64)
760 data
[59:64] = 0b01101 # mask
762 (rts
, mbits
, pgbase
) = mem
._decode
_prte
(data
)
763 print (" rts", bin(rts
.value
), rts
.bits
)
764 print (" mbits", bin(mbits
.value
), mbits
.bits
)
765 print (" pgbase", hex(pgbase
.value
), pgbase
.bits
)
766 addr
= SelectableInt(0x1000, 64)
767 check
= mem
._segment
_check
(addr
, mbits
, shift
)
768 print (" segment check", check
)
770 print("walking tree")
771 addr
= SelectableInt(testaddr
,64)
776 result
= mem
._walk
_tree
(addr
, pgbase
, mode
, mbits
, shift
)
777 print(" walking tree result", result
)
778 print("should be", testresult
)
779 self
.assertEqual(result
.value
, expected
,
780 "expected 0x%x got 0x%x" % (expected
,
784 def tst_walk_tree_2(self
):
786 # test address slightly different
793 # set up dummy minimal ISACaller
794 spr
= {'DSISR': SelectableInt(0, 64),
795 'DAR': SelectableInt(0, 64),
796 'PIDR': SelectableInt(0, 64),
797 'PRTBL': SelectableInt(prtbl
, 64)
799 # set problem state == 0 (other unit tests, set to 1)
800 msr
= SelectableInt(0, 64)
802 class ISACaller
: pass
807 shift
= SelectableInt(5, 6)
808 mask
= genmask(shift
, 43)
809 print (" mask", bin(mask
.value
))
811 mem
= Mem(row_bytes
=8, initial_mem
=testmem2
)
812 mem
= RADIX(mem
, caller
)
813 # -----------------------------------------------
814 # |/|RTS1|/| RPDB | RTS2 | RPDS |
815 # -----------------------------------------------
816 # |0|1 2|3|4 55|56 58|59 63|
817 data
= SelectableInt(0, 64)
820 data
[59:64] = 0b01101 # mask
822 (rts
, mbits
, pgbase
) = mem
._decode
_prte
(data
)
823 print (" rts", bin(rts
.value
), rts
.bits
)
824 print (" mbits", bin(mbits
.value
), mbits
.bits
)
825 print (" pgbase", hex(pgbase
.value
), pgbase
.bits
)
826 addr
= SelectableInt(0x1000, 64)
827 check
= mem
._segment
_check
(addr
, mbits
, shift
)
828 print (" segment check", check
)
830 print("walking tree")
831 addr
= SelectableInt(testaddr
,64)
836 result
= mem
._walk
_tree
(addr
, pgbase
, mode
, mbits
, shift
)
837 print(" walking tree result", result
)
838 print("should be", testresult
)
839 self
.assertEqual(result
.value
, expected
,
840 "expected 0x%x got 0x%x" % (expected
,
844 if __name__
== '__main__':