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move ISACaller RADIX MMU class to separate module
[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 from nmigen.back.pysim import Settle
17 from functools import wraps
18 from copy import copy
19 from soc.decoder.orderedset import OrderedSet
20 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
21 selectconcat)
22 from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
23 insns, MicrOp, In1Sel, In2Sel, In3Sel,
24 OutSel, CROutSel)
25
26 from soc.decoder.power_enums import SPR as DEC_SPR
27
28 from soc.decoder.helpers import exts, gtu, ltu, undefined
29 from soc.consts import PIb, MSRb # big-endian (PowerISA versions)
30 from soc.decoder.power_svp64 import SVP64RM, decode_extra
31
32 from collections import namedtuple
33 import math
34 import sys
35
36 instruction_info = namedtuple('instruction_info',
37 'func read_regs uninit_regs write_regs ' +
38 'special_regs op_fields form asmregs')
39
40 special_sprs = {
41 'LR': 8,
42 'CTR': 9,
43 'TAR': 815,
44 'XER': 1,
45 'VRSAVE': 256}
46
47
48 def swap_order(x, nbytes):
49 x = x.to_bytes(nbytes, byteorder='little')
50 x = int.from_bytes(x, byteorder='big', signed=False)
51 return x
52
53
54 REG_SORT_ORDER = {
55 # TODO (lkcl): adjust other registers that should be in a particular order
56 # probably CA, CA32, and CR
57 "RT": 0,
58 "RA": 0,
59 "RB": 0,
60 "RS": 0,
61 "CR": 0,
62 "LR": 0,
63 "CTR": 0,
64 "TAR": 0,
65 "CA": 0,
66 "CA32": 0,
67 "MSR": 0,
68
69 "overflow": 1,
70 }
71
72
73 # very quick, TODO move to SelectableInt utils later
74 def genmask(shift, size):
75 res = SelectableInt(0, size)
76 for i in range(size):
77 if i < shift:
78 res[size-1-i] = SelectableInt(1, 1)
79 return res
80
81 """
82 Get Root Page
83
84 //Accessing 2nd double word of partition table (pate1)
85 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
86 // PTCR Layout
87 // ====================================================
88 // -----------------------------------------------
89 // | /// | PATB | /// | PATS |
90 // -----------------------------------------------
91 // 0 4 51 52 58 59 63
92 // PATB[4:51] holds the base address of the Partition Table,
93 // right shifted by 12 bits.
94 // This is because the address of the Partition base is
95 // 4k aligned. Hence, the lower 12bits, which are always
96 // 0 are ommitted from the PTCR.
97 //
98 // Thus, The Partition Table Base is obtained by (PATB << 12)
99 //
100 // PATS represents the partition table size right-shifted by 12 bits.
101 // The minimal size of the partition table is 4k.
102 // Thus partition table size = (1 << PATS + 12).
103 //
104 // Partition Table
105 // ====================================================
106 // 0 PATE0 63 PATE1 127
107 // |----------------------|----------------------|
108 // | | |
109 // |----------------------|----------------------|
110 // | | |
111 // |----------------------|----------------------|
112 // | | | <-- effLPID
113 // |----------------------|----------------------|
114 // .
115 // .
116 // .
117 // |----------------------|----------------------|
118 // | | |
119 // |----------------------|----------------------|
120 //
121 // The effective LPID forms the index into the Partition Table.
122 //
123 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
124 // corresponding to that partition.
125 //
126 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
127 //
128 // PATE0 Layout
129 // -----------------------------------------------
130 // |1|RTS1|/| RPDB | RTS2 | RPDS |
131 // -----------------------------------------------
132 // 0 1 2 3 4 55 56 58 59 63
133 //
134 // HR[0] : For Radix Page table, first bit should be 1.
135 // RTS1[1:2] : Gives one fragment of the Radix treesize
136 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
137 // RTS = (RTS1 << 3 + RTS2) + 31.
138 //
139 // RPDB[4:55] = Root Page Directory Base.
140 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
141 // Thus, Root page directory size = 1 << (RPDS + 3).
142 // Note: RPDS >= 5.
143 //
144 // PATE1 Layout
145 // -----------------------------------------------
146 // |///| PRTB | // | PRTS |
147 // -----------------------------------------------
148 // 0 3 4 51 52 58 59 63
149 //
150 // PRTB[4:51] = Process Table Base. This is aligned to size.
151 // PRTS[59: 63] = Process Table Size right shifted by 12.
152 // Minimal size of the process table is 4k.
153 // Process Table Size = (1 << PRTS + 12).
154 // Note: PRTS <= 24.
155 //
156 // Computing the size aligned Process Table Base:
157 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
158 // Thus, the lower 12+PRTS bits of table_base will
159 // be zero.
160
161
162 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
163 //
164 // Process Table
165 // ==========================
166 // 0 PRTE0 63 PRTE1 127
167 // |----------------------|----------------------|
168 // | | |
169 // |----------------------|----------------------|
170 // | | |
171 // |----------------------|----------------------|
172 // | | | <-- effPID
173 // |----------------------|----------------------|
174 // .
175 // .
176 // .
177 // |----------------------|----------------------|
178 // | | |
179 // |----------------------|----------------------|
180 //
181 // The effective Process id (PID) forms the index into the Process Table.
182 //
183 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
184 // corresponding to that process
185 //
186 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
187 //
188 // PRTE0 Layout
189 // -----------------------------------------------
190 // |/|RTS1|/| RPDB | RTS2 | RPDS |
191 // -----------------------------------------------
192 // 0 1 2 3 4 55 56 58 59 63
193 //
194 // RTS1[1:2] : Gives one fragment of the Radix treesize
195 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
196 // RTS = (RTS1 << 3 + RTS2) << 31,
197 // since minimal Radix Tree size is 4G.
198 //
199 // RPDB = Root Page Directory Base.
200 // RPDS = Root Page Directory Size right shifted by 3.
201 // Thus, Root page directory size = RPDS << 3.
202 // Note: RPDS >= 5.
203 //
204 // PRTE1 Layout
205 // -----------------------------------------------
206 // | /// |
207 // -----------------------------------------------
208 // 0 63
209 // All bits are reserved.
210
211
212 """
213
214 # see qemu/target/ppc/mmu-radix64.c for reference
215 class RADIX:
216 def __init__(self, mem, caller):
217 self.mem = mem
218 self.caller = caller
219
220 # cached page table stuff
221 self.pgtbl0 = 0
222 self.pt0_valid = False
223 self.pgtbl3 = 0
224 self.pt3_valid = False
225
226 def __call__(self,*args, **kwargs):
227 print("TODO: implement RADIX.__call__()")
228 print(args)
229 print(kwargs)
230 return None
231
232 def ld(self, address, width=8, swap=True, check_in_mem=False):
233 print("RADIX: ld from addr 0x%x width %d" % (address, width))
234 dsisr = self.caller.spr[DEC_SPR.DSISR.value]
235 dar = self.caller.spr[DEC_SPR.DAR.value]
236 pidr = self.caller.spr[DEC_SPR.PIDR.value]
237 prtbl = self.caller.spr[DEC_SPR.PRTBL.value]
238
239 pte = self._walk_tree()
240 # use pte to caclculate phys address
241 return self.mem.ld(address, width, swap, check_in_mem)
242
243 # XXX set SPRs on error
244
245 # TODO implement
246 def st(self, addr, v, width=8, swap=True):
247 print("RADIX: st to addr 0x%x width %d data %x" % (addr, width, v))
248 dsisr = self.caller.spr[DEC_SPR.DSISR.value]
249 dar = self.caller.spr[DEC_SPR.DAR.value]
250 pidr = self.caller.spr[DEC_SPR.PIDR.value]
251 prtbl = self.caller.spr[DEC_SPR.PRTBL.value]
252
253 # use pte to caclculate phys address (addr)
254 return self.mem.st(addr, v, width, swap)
255
256 # XXX set SPRs on error
257
258 def memassign(self, addr, sz, val):
259 print("memassign", addr, sz, val)
260 self.st(addr.value, val.value, sz, swap=False)
261
262 def _next_level(self):
263 return True
264 ## DSISR_R_BADCONFIG
265 ## read_entry
266 ## DSISR_NOPTE
267 ## Prepare for next iteration
268
269 def _walk_tree(self):
270 """walk tree
271
272 // vaddr 64 Bit
273 // vaddr |-----------------------------------------------------|
274 // | Unused | Used |
275 // |-----------|-----------------------------------------|
276 // | 0000000 | usefulBits = X bits (typically 52) |
277 // |-----------|-----------------------------------------|
278 // | |<--Cursize---->| |
279 // | | Index | |
280 // | | into Page | |
281 // | | Directory | |
282 // |-----------------------------------------------------|
283 // | |
284 // V |
285 // PDE |---------------------------| |
286 // |V|L|//| NLB |///|NLS| |
287 // |---------------------------| |
288 // PDE = Page Directory Entry |
289 // [0] = V = Valid Bit |
290 // [1] = L = Leaf bit. If 0, then |
291 // [4:55] = NLB = Next Level Base |
292 // right shifted by 8 |
293 // [59:63] = NLS = Next Level Size |
294 // | NLS >= 5 |
295 // | V
296 // | |--------------------------|
297 // | | usfulBits = X-Cursize |
298 // | |--------------------------|
299 // |---------------------><--NLS-->| |
300 // | Index | |
301 // | into | |
302 // | PDE | |
303 // |--------------------------|
304 // |
305 // If the next PDE obtained by |
306 // (NLB << 8 + 8 * index) is a |
307 // nonleaf, then repeat the above. |
308 // |
309 // If the next PDE is a leaf, |
310 // then Leaf PDE structure is as |
311 // follows |
312 // |
313 // |
314 // Leaf PDE |
315 // |------------------------------| |----------------|
316 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
317 // |------------------------------| |----------------|
318 // [0] = V = Valid Bit |
319 // [1] = L = Leaf Bit = 1 if leaf |
320 // PDE |
321 // [2] = Sw = Sw bit 0. |
322 // [7:51] = RPN = Real Page Number, V
323 // real_page = RPN << 12 -------------> Logical OR
324 // [52:54] = Sw Bits 1:3 |
325 // [55] = R = Reference |
326 // [56] = C = Change V
327 // [58:59] = Att = Physical Address
328 // 0b00 = Normal Memory
329 // 0b01 = SAO
330 // 0b10 = Non Idenmpotent
331 // 0b11 = Tolerant I/O
332 // [60:63] = Encoded Access
333 // Authority
334 //
335 """
336 # walk tree starts on prtbl
337 while True:
338 ret = self._next_level()
339 if ret: return ret
340
341 def _decode_prte(self, data):
342 """PRTE0 Layout
343 -----------------------------------------------
344 |/|RTS1|/| RPDB | RTS2 | RPDS |
345 -----------------------------------------------
346 0 1 2 3 4 55 56 58 59 63
347 """
348 # note that SelectableInt does big-endian! so the indices
349 # below *directly* match the spec, unlike microwatt which
350 # has to turn them around (to LE)
351 zero = SelectableInt(0, 1)
352 rts = selectconcat(zero,
353 data[56:59], # RTS2
354 data[1:3], # RTS1
355 )
356 masksize = data[59:64] # RPDS
357 mbits = selectconcat(zero, masksize)
358 pgbase = selectconcat(data[8:56], # part of RPDB
359 SelectableInt(0, 16),)
360
361 return (rts, mbits, pgbase)
362
363 def _segment_check(self, addr, mbits, shift):
364 """checks segment valid
365 mbits := '0' & r.mask_size;
366 v.shift := r.shift + (31 - 12) - mbits;
367 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
368 if r.addr(63) /= r.addr(62) or nonzero = '1' then
369 v.state := RADIX_FINISH;
370 v.segerror := '1';
371 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
372 v.state := RADIX_FINISH;
373 v.badtree := '1';
374 else
375 v.state := RADIX_LOOKUP;
376 """
377 # note that SelectableInt does big-endian! so the indices
378 # below *directly* match the spec, unlike microwatt which
379 # has to turn them around (to LE)
380 mask = genmask(shift, 44)
381 nonzero = addr[1:32] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
382 print ("RADIX _segment_check nonzero", bin(nonzero.value))
383 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
384 if addr[0] != addr[1] or nonzero == 1:
385 return "segerror"
386 limit = shift + (31 - 12)
387 if mbits < 5 or mbits > 16 or mbits > limit:
388 return "badtree"
389 new_shift = shift + (31 - 12) - mbits
390 return new_shift
391
392 def _check_perms(self):
393 """check page permissions
394 -- test leaf bit
395 if data(62) = '1' then
396 -- check permissions and RC bits
397 perm_ok := '0';
398 if r.priv = '1' or data(3) = '0' then
399 if r.iside = '0' then
400 perm_ok := data(1) or (data(2) and not r.store);
401 else
402 -- no IAMR, so no KUEP support for now
403 -- deny execute permission if cache inhibited
404 perm_ok := data(0) and not data(5);
405 end if;
406 end if;
407 rc_ok := data(8) and (data(7) or not r.store);
408 if perm_ok = '1' and rc_ok = '1' then
409 v.state := RADIX_LOAD_TLB;
410 else
411 v.state := RADIX_FINISH;
412 v.perm_err := not perm_ok;
413 -- permission error takes precedence over RC error
414 v.rc_error := perm_ok;
415 end if;
416 """
417
418 def _get_prtable_addr(self, shift, prtbl, addr, pid):
419 """
420 if r.addr(63) = '1' then
421 effpid := x"00000000";
422 else
423 effpid := r.pid;
424 end if;
425 x"00" & r.prtbl(55 downto 36) &
426 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
427 (effpid(31 downto 8) and finalmask(23 downto 0))) &
428 effpid(7 downto 0) & "0000";
429 """
430 finalmask = genmask(shift, 44)
431 finalmask24 = finalmask[20:44]
432 if addr[0].value == 1:
433 effpid = SelectableInt(0, 32)
434 else:
435 effpid = self.pid[32:64] # TODO, check on this
436 zero16 = SelectableInt(0, 16)
437 zero4 = SelectableInt(0, 4)
438 res = selectconcat(zero16,
439 prtbl[8:28], #
440 (prtbl[28:52] & ~finalmask24) | #
441 (effpid[0:24] & finalmask24), #
442 effpid[24:32],
443 zero4
444 )
445 return res
446
447 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
448 """
449 x"00" & r.pgbase(55 downto 19) &
450 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
451 "000";
452 """
453 mask16 = genmask(mask_size+5, 16)
454 zero8 = SelectableInt(0, 8)
455 zero3 = SelectableInt(0, 3)
456 res = selectconcat(zero8,
457 pgbase[8:45], #
458 (prtbl[45:61] & ~mask16) | #
459 (addrsh & mask16), #
460 zero3
461 )
462 return res
463
464 def _get_pte(self, shift, addr, pde):
465 """
466 x"00" &
467 ((r.pde(55 downto 12) and not finalmask) or
468 (r.addr(55 downto 12) and finalmask))
469 & r.pde(11 downto 0);
470 """
471 finalmask = genmask(shift, 44)
472 zero8 = SelectableInt(0, 8)
473 res = selectconcat(zero8,
474 (pde[8:52] & ~finalmask) | #
475 (addr[8:52] & finalmask), #
476 pde[52:64],
477 )
478 return res
479
480
481 # very quick test of maskgen function (TODO, move to util later)
482 if __name__ == '__main__':
483 shift = SelectableInt(5, 6)
484 mask = genmask(shift, 43)
485 print (" mask", bin(mask.value))
486
487 mem = Mem(row_bytes=8)
488 mem = RADIX(mem, None)
489 # -----------------------------------------------
490 # |/|RTS1|/| RPDB | RTS2 | RPDS |
491 # -----------------------------------------------
492 # |0|1 2|3|4 55|56 58|59 63|
493 data = SelectableInt(0, 64)
494 data[1:3] = 0b01
495 data[56:59] = 0b11
496 data[59:64] = 0b01101 # mask
497 data[55] = 1
498 (rts, mbits, pgbase) = mem._decode_prte(data)
499 print (" rts", bin(rts.value), rts.bits)
500 print (" mbits", bin(mbits.value), mbits.bits)
501 print (" pgbase", hex(pgbase.value), pgbase.bits)
502 addr = SelectableInt(0x1000, 64)
503 check = mem._segment_check(addr, mbits, shift)
504 print (" segment check", check)