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make svp64 isa caller unit tests more obvious
[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 from nmigen.back.pysim import Settle
17 from copy import copy
18 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from soc.decoder.helpers import exts, gtu, ltu, undefined
21 from soc.decoder.isa.mem import Mem
22 from soc.consts import MSRb # big-endian (PowerISA versions)
23
24 import math
25 import sys
26 import unittest
27
28 # very quick, TODO move to SelectableInt utils later
29 def genmask(shift, size):
30 res = SelectableInt(0, size)
31 for i in range(size):
32 if i < shift:
33 res[size-1-i] = SelectableInt(1, 1)
34 return res
35
36 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
37 # MSB is indexed **LOWEST** (sigh)
38 # from gem5 radixwalk.hh
39 # Bitfield<63> valid; 64 - (63 + 1) = 0
40 # Bitfield<62> leaf; 64 - (62 + 1) = 1
41
42 def rpte_valid(r):
43 return bool(r[0])
44
45 def rpte_leaf(r):
46 return bool(r[1])
47
48 ## Shift address bits 61--12 right by 0--47 bits and
49 ## supply the least significant 16 bits of the result.
50 def addrshift(addr,shift):
51 x = addr.value >> shift.value
52 return SelectableInt(x,16)
53
54 def NLB(x):
55 """
56 Next Level Base
57 right shifted by 8
58 """
59 return x[4:55]
60
61 def NLS(x):
62 """
63 Next Level Size
64 NLS >= 5
65 """
66 return x[59:63]
67
68 """
69 Get Root Page
70
71 //Accessing 2nd double word of partition table (pate1)
72 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
73 // PTCR Layout
74 // ====================================================
75 // -----------------------------------------------
76 // | /// | PATB | /// | PATS |
77 // -----------------------------------------------
78 // 0 4 51 52 58 59 63
79 // PATB[4:51] holds the base address of the Partition Table,
80 // right shifted by 12 bits.
81 // This is because the address of the Partition base is
82 // 4k aligned. Hence, the lower 12bits, which are always
83 // 0 are ommitted from the PTCR.
84 //
85 // Thus, The Partition Table Base is obtained by (PATB << 12)
86 //
87 // PATS represents the partition table size right-shifted by 12 bits.
88 // The minimal size of the partition table is 4k.
89 // Thus partition table size = (1 << PATS + 12).
90 //
91 // Partition Table
92 // ====================================================
93 // 0 PATE0 63 PATE1 127
94 // |----------------------|----------------------|
95 // | | |
96 // |----------------------|----------------------|
97 // | | |
98 // |----------------------|----------------------|
99 // | | | <-- effLPID
100 // |----------------------|----------------------|
101 // .
102 // .
103 // .
104 // |----------------------|----------------------|
105 // | | |
106 // |----------------------|----------------------|
107 //
108 // The effective LPID forms the index into the Partition Table.
109 //
110 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
111 // corresponding to that partition.
112 //
113 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
114 //
115 // PATE0 Layout
116 // -----------------------------------------------
117 // |1|RTS1|/| RPDB | RTS2 | RPDS |
118 // -----------------------------------------------
119 // 0 1 2 3 4 55 56 58 59 63
120 //
121 // HR[0] : For Radix Page table, first bit should be 1.
122 // RTS1[1:2] : Gives one fragment of the Radix treesize
123 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
124 // RTS = (RTS1 << 3 + RTS2) + 31.
125 //
126 // RPDB[4:55] = Root Page Directory Base.
127 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
128 // Thus, Root page directory size = 1 << (RPDS + 3).
129 // Note: RPDS >= 5.
130 //
131 // PATE1 Layout
132 // -----------------------------------------------
133 // |///| PRTB | // | PRTS |
134 // -----------------------------------------------
135 // 0 3 4 51 52 58 59 63
136 //
137 // PRTB[4:51] = Process Table Base. This is aligned to size.
138 // PRTS[59: 63] = Process Table Size right shifted by 12.
139 // Minimal size of the process table is 4k.
140 // Process Table Size = (1 << PRTS + 12).
141 // Note: PRTS <= 24.
142 //
143 // Computing the size aligned Process Table Base:
144 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
145 // Thus, the lower 12+PRTS bits of table_base will
146 // be zero.
147
148
149 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
150 //
151 // Process Table
152 // ==========================
153 // 0 PRTE0 63 PRTE1 127
154 // |----------------------|----------------------|
155 // | | |
156 // |----------------------|----------------------|
157 // | | |
158 // |----------------------|----------------------|
159 // | | | <-- effPID
160 // |----------------------|----------------------|
161 // .
162 // .
163 // .
164 // |----------------------|----------------------|
165 // | | |
166 // |----------------------|----------------------|
167 //
168 // The effective Process id (PID) forms the index into the Process Table.
169 //
170 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
171 // corresponding to that process
172 //
173 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
174 //
175 // PRTE0 Layout
176 // -----------------------------------------------
177 // |/|RTS1|/| RPDB | RTS2 | RPDS |
178 // -----------------------------------------------
179 // 0 1 2 3 4 55 56 58 59 63
180 //
181 // RTS1[1:2] : Gives one fragment of the Radix treesize
182 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
183 // RTS = (RTS1 << 3 + RTS2) << 31,
184 // since minimal Radix Tree size is 4G.
185 //
186 // RPDB = Root Page Directory Base.
187 // RPDS = Root Page Directory Size right shifted by 3.
188 // Thus, Root page directory size = RPDS << 3.
189 // Note: RPDS >= 5.
190 //
191 // PRTE1 Layout
192 // -----------------------------------------------
193 // | /// |
194 // -----------------------------------------------
195 // 0 63
196 // All bits are reserved.
197
198
199 """
200
201 testaddr = 0x10000
202 testmem = {
203
204 0x10000: # PARTITION_TABLE_2 (not implemented yet)
205 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
206 0x800000000100000b,
207
208 0x30000: # RADIX_ROOT_PTE
209 # V = 1 L = 0 NLB = 0x400 NLS = 9
210 0x8000000000040009,
211 ######## 0x4000000 #### wrong address calculated by _get_pgtable_addr
212 0x40000: # RADIX_SECOND_LEVEL
213 # V = 1 L = 1 SW = 0 RPN = 0
214 # R = 1 C = 1 ATT = 0 EAA 0x7
215 0xc000000000000187,
216
217 0x1000000: # PROCESS_TABLE_3
218 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
219 0x40000000000300ad,
220 }
221
222
223
224 # see qemu/target/ppc/mmu-radix64.c for reference
225 class RADIX:
226 def __init__(self, mem, caller):
227 self.mem = mem
228 self.caller = caller
229 if caller is not None:
230 self.dsisr = self.caller.spr["DSISR"]
231 self.dar = self.caller.spr["DAR"]
232 self.pidr = self.caller.spr["PIDR"]
233 self.prtbl = self.caller.spr["PRTBL"]
234 self.msr = self.caller.msr
235
236 # cached page table stuff
237 self.pgtbl0 = 0
238 self.pt0_valid = False
239 self.pgtbl3 = 0
240 self.pt3_valid = False
241
242 def __call__(self, addr, sz):
243 val = self.ld(addr.value, sz, swap=False)
244 print("RADIX memread", addr, sz, val)
245 return SelectableInt(val, sz*8)
246
247 def ld(self, address, width=8, swap=True, check_in_mem=False,
248 instr_fetch=False):
249 print("RADIX: ld from addr 0x%x width %d" % (address, width))
250
251 priv = ~(self.msr(MSR_PR).value) # problem-state ==> privileged
252 if instr_fetch:
253 mode = 'EXECUTE'
254 else:
255 mode = 'LOAD'
256 addr = SelectableInt(address, 64)
257 (shift, mbits, pgbase) = self._decode_prte(addr)
258 #shift = SelectableInt(0, 32)
259
260 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
261 # use pte to caclculate phys address
262 return self.mem.ld(address, width, swap, check_in_mem)
263
264 # XXX set SPRs on error
265
266 # TODO implement
267 def st(self, address, v, width=8, swap=True):
268 print("RADIX: st to addr 0x%x width %d data %x" % (address, width, v))
269
270 priv = ~(self.msr(MSR_PR).value) # problem-state ==> privileged
271 mode = 'STORE'
272 addr = SelectableInt(address, 64)
273 (shift, mbits, pgbase) = self._decode_prte(addr)
274 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
275
276 # use pte to caclculate phys address (addr)
277 return self.mem.st(addr.value, v, width, swap)
278
279 # XXX set SPRs on error
280
281 def memassign(self, addr, sz, val):
282 print("memassign", addr, sz, val)
283 self.st(addr.value, val.value, sz, swap=False)
284
285 def _next_level(self, addr, entry_width, swap, check_in_mem):
286 # implement read access to mmu mem here
287
288 value = 0
289 if addr.value in testmem:
290 value = testmem[addr.value]
291 else:
292 print("not found")
293
294 ##value = self.mem.ld(addr.value, entry_width, swap, check_in_mem)
295 print("addr", hex(addr.value))
296 data = SelectableInt(value, 64) # convert to SelectableInt
297 print("value", hex(value))
298 # index += 1
299 return data;
300
301 def _walk_tree(self, addr, pgbase, mode, mbits, shift, priv=1):
302 """walk tree
303
304 // vaddr 64 Bit
305 // vaddr |-----------------------------------------------------|
306 // | Unused | Used |
307 // |-----------|-----------------------------------------|
308 // | 0000000 | usefulBits = X bits (typically 52) |
309 // |-----------|-----------------------------------------|
310 // | |<--Cursize---->| |
311 // | | Index | |
312 // | | into Page | |
313 // | | Directory | |
314 // |-----------------------------------------------------|
315 // | |
316 // V |
317 // PDE |---------------------------| |
318 // |V|L|//| NLB |///|NLS| |
319 // |---------------------------| |
320 // PDE = Page Directory Entry |
321 // [0] = V = Valid Bit |
322 // [1] = L = Leaf bit. If 0, then |
323 // [4:55] = NLB = Next Level Base |
324 // right shifted by 8 |
325 // [59:63] = NLS = Next Level Size |
326 // | NLS >= 5 |
327 // | V
328 // | |--------------------------|
329 // | | usfulBits = X-Cursize |
330 // | |--------------------------|
331 // |---------------------><--NLS-->| |
332 // | Index | |
333 // | into | |
334 // | PDE | |
335 // |--------------------------|
336 // |
337 // If the next PDE obtained by |
338 // (NLB << 8 + 8 * index) is a |
339 // nonleaf, then repeat the above. |
340 // |
341 // If the next PDE is a leaf, |
342 // then Leaf PDE structure is as |
343 // follows |
344 // |
345 // |
346 // Leaf PDE |
347 // |------------------------------| |----------------|
348 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
349 // |------------------------------| |----------------|
350 // [0] = V = Valid Bit |
351 // [1] = L = Leaf Bit = 1 if leaf |
352 // PDE |
353 // [2] = Sw = Sw bit 0. |
354 // [7:51] = RPN = Real Page Number, V
355 // real_page = RPN << 12 -------------> Logical OR
356 // [52:54] = Sw Bits 1:3 |
357 // [55] = R = Reference |
358 // [56] = C = Change V
359 // [58:59] = Att = Physical Address
360 // 0b00 = Normal Memory
361 // 0b01 = SAO
362 // 0b10 = Non Idenmpotent
363 // 0b11 = Tolerant I/O
364 // [60:63] = Encoded Access
365 // Authority
366 //
367 """
368 # get sprs
369 print("_walk_tree")
370 pidr = self.caller.spr["PIDR"]
371 prtbl = self.caller.spr["PRTBL"]
372 print(pidr)
373 print(prtbl)
374 p = addr[55:63]
375 print("last 8 bits ----------")
376 print
377
378 # get address of root entry
379 addr_next = self._get_prtable_addr(shift, prtbl, addr, pidr)
380
381 addr_next = SelectableInt(0x30000,64) # radix root for testing
382
383 # walk tree starts on prtbl
384 while True:
385 print("nextlevel----------------------------")
386 # read an entry
387 swap = False
388 check_in_mem = False
389 entry_width = 8
390
391 data = self._next_level(addr_next, entry_width, swap, check_in_mem)
392 valid = rpte_valid(data)
393 leaf = rpte_leaf(data)
394
395 print(" valid, leaf", valid, leaf)
396 if not valid:
397 return "invalid" # TODO: return error
398 if leaf:
399 ok = self._check_perms(data, priv, mode)
400 if ok == True: # data was ok, found phys address, return it?
401 return addr_next
402 return ok # return the error code
403 else:
404 newlookup = self._new_lookup(data, mbits, shift)
405 if newlookup == 'badtree':
406 return newlookup
407 shift, mask, pgbase = newlookup
408 print (" next level", shift, mask, pgbase)
409 shift = SelectableInt(shift.value,16) #THIS is wrong !!!
410 print("calling _get_pgtable_addr")
411 print(mask) #SelectableInt(value=0x9, bits=4)
412 print(pgbase) #SelectableInt(value=0x40000, bits=56)
413 print(shift) #SelectableInt(value=0x4, bits=16) #FIXME
414 pgbase = SelectableInt(pgbase.value,64)
415 addrsh = addrshift(addr,shift)
416 addr_next = self._get_pgtable_addr(mask, pgbase, addrsh)
417 print("addr_next",addr_next)
418 print("addrsh",addrsh)
419 assert(addr_next == 0x40000)
420 return "TODO verify next level"
421
422 def _new_lookup(self, data, mbits, shift):
423 """
424 mbits := unsigned('0' & data(4 downto 0));
425 if mbits < 5 or mbits > 16 or mbits > r.shift then
426 v.state := RADIX_FINISH;
427 v.badtree := '1'; -- throw error
428 else
429 v.shift := v.shift - mbits;
430 v.mask_size := mbits(4 downto 0);
431 v.pgbase := data(55 downto 8) & x"00"; NLB?
432 v.state := RADIX_LOOKUP; --> next level
433 end if;
434 """
435 mbits = data[59:64]
436 print("mbits=", mbits)
437 if mbits < 5 or mbits > 16: #fixme compare with r.shift
438 print("badtree")
439 return "badtree"
440 # reduce shift (has to be done at same bitwidth)
441 shift = shift - selectconcat(SelectableInt(0, 1), mbits)
442 mask_size = mbits[1:5] # get 4 LSBs
443 pgbase = selectconcat(data[8:56], SelectableInt(0, 8)) # shift up 8
444 return shift, mask_size, pgbase
445
446 def _decode_prte(self, data):
447 """PRTE0 Layout
448 -----------------------------------------------
449 |/|RTS1|/| RPDB | RTS2 | RPDS |
450 -----------------------------------------------
451 0 1 2 3 4 55 56 58 59 63
452 """
453 # note that SelectableInt does big-endian! so the indices
454 # below *directly* match the spec, unlike microwatt which
455 # has to turn them around (to LE)
456 zero = SelectableInt(0, 1)
457 rts = selectconcat(zero,
458 data[56:59], # RTS2
459 data[1:3], # RTS1
460 )
461 masksize = data[59:64] # RPDS
462 mbits = selectconcat(zero, masksize)
463 pgbase = selectconcat(data[8:56], # part of RPDB
464 SelectableInt(0, 16),)
465
466 return (rts, mbits, pgbase)
467
468 def _segment_check(self, addr, mbits, shift):
469 """checks segment valid
470 mbits := '0' & r.mask_size;
471 v.shift := r.shift + (31 - 12) - mbits;
472 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
473 if r.addr(63) /= r.addr(62) or nonzero = '1' then
474 v.state := RADIX_FINISH;
475 v.segerror := '1';
476 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
477 v.state := RADIX_FINISH;
478 v.badtree := '1';
479 else
480 v.state := RADIX_LOOKUP;
481 """
482 # note that SelectableInt does big-endian! so the indices
483 # below *directly* match the spec, unlike microwatt which
484 # has to turn them around (to LE)
485 mask = genmask(shift, 44)
486 nonzero = addr[1:32] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
487 print ("RADIX _segment_check nonzero", bin(nonzero.value))
488 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
489 if addr[0] != addr[1] or nonzero != 0:
490 return "segerror"
491 limit = shift + (31 - 12)
492 if mbits < 5 or mbits > 16 or mbits > limit:
493 return "badtree"
494 new_shift = shift + (31 - 12) - mbits
495 return new_shift
496
497 def _check_perms(self, data, priv, mode):
498 """check page permissions
499 // Leaf PDE |
500 // |------------------------------| |----------------|
501 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
502 // |------------------------------| |----------------|
503 // [0] = V = Valid Bit |
504 // [1] = L = Leaf Bit = 1 if leaf |
505 // PDE |
506 // [2] = Sw = Sw bit 0. |
507 // [7:51] = RPN = Real Page Number, V
508 // real_page = RPN << 12 -------------> Logical OR
509 // [52:54] = Sw Bits 1:3 |
510 // [55] = R = Reference |
511 // [56] = C = Change V
512 // [58:59] = Att = Physical Address
513 // 0b00 = Normal Memory
514 // 0b01 = SAO
515 // 0b10 = Non Idenmpotent
516 // 0b11 = Tolerant I/O
517 // [60:63] = Encoded Access
518 // Authority
519 //
520 -- test leaf bit
521 -- check permissions and RC bits
522 perm_ok := '0';
523 if r.priv = '1' or data(3) = '0' then
524 if r.iside = '0' then
525 perm_ok := data(1) or (data(2) and not r.store);
526 else
527 -- no IAMR, so no KUEP support for now
528 -- deny execute permission if cache inhibited
529 perm_ok := data(0) and not data(5);
530 end if;
531 end if;
532 rc_ok := data(8) and (data(7) or not r.store);
533 if perm_ok = '1' and rc_ok = '1' then
534 v.state := RADIX_LOAD_TLB;
535 else
536 v.state := RADIX_FINISH;
537 v.perm_err := not perm_ok;
538 -- permission error takes precedence over RC error
539 v.rc_error := perm_ok;
540 end if;
541 """
542 # decode mode into something that matches microwatt equivalent code
543 instr_fetch, store = 0, 0
544 if mode == 'STORE':
545 store = 1
546 if mode == 'EXECUTE':
547 inst_fetch = 1
548
549 # check permissions and RC bits
550 perm_ok = 0
551 if priv == 1 or data[60] == 0:
552 if instr_fetch == 0:
553 perm_ok = data[62] | (data[61] & (store == 0))
554 # no IAMR, so no KUEP support for now
555 # deny execute permission if cache inhibited
556 perm_ok = data[63] & ~data[58]
557 rc_ok = data[55] & (data[56] | (store == 0))
558 if perm_ok == 1 and rc_ok == 1:
559 return True
560
561 return "perm_err" if perm_ok == 0 else "rc_err"
562
563 def _get_prtable_addr(self, shift, prtbl, addr, pid):
564 """
565 if r.addr(63) = '1' then
566 effpid := x"00000000";
567 else
568 effpid := r.pid;
569 end if;
570 x"00" & r.prtbl(55 downto 36) &
571 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
572 (effpid(31 downto 8) and finalmask(23 downto 0))) &
573 effpid(7 downto 0) & "0000";
574 """
575 print ("_get_prtable_addr_", shift, prtbl, addr, pid)
576 finalmask = genmask(shift, 44)
577 finalmask24 = finalmask[20:44]
578 if addr[0].value == 1:
579 effpid = SelectableInt(0, 32)
580 else:
581 effpid = pid #self.pid # TODO, check on this
582 zero16 = SelectableInt(0, 16)
583 zero4 = SelectableInt(0, 4)
584 res = selectconcat(zero16,
585 prtbl[8:28], #
586 (prtbl[28:52] & ~finalmask24) | #
587 (effpid[0:24] & finalmask24), #
588 effpid[24:32],
589 zero4
590 )
591 return res
592
593 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
594 """
595 x"00" & r.pgbase(55 downto 19) &
596 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
597 "000";
598 """
599 mask16 = genmask(mask_size+5, 16)
600 zero8 = SelectableInt(0, 8)
601 zero3 = SelectableInt(0, 3)
602 res = selectconcat(zero8,
603 pgbase[8:45], #
604 (pgbase[45:61] & ~mask16) | #
605 (addrsh & mask16), #
606 zero3
607 )
608 return res
609
610 def _get_pte(self, shift, addr, pde):
611 """
612 x"00" &
613 ((r.pde(55 downto 12) and not finalmask) or
614 (r.addr(55 downto 12) and finalmask))
615 & r.pde(11 downto 0);
616 """
617 finalmask = genmask(shift, 44)
618 zero8 = SelectableInt(0, 8)
619 res = selectconcat(zero8,
620 (pde[8:52] & ~finalmask) | #
621 (addr[8:52] & finalmask), #
622 pde[52:64],
623 )
624 return res
625
626
627 class TestRadixMMU(unittest.TestCase):
628
629 def test_genmask(self):
630 shift = SelectableInt(5, 6)
631 mask = genmask(shift, 43)
632 print (" mask", bin(mask.value))
633
634 self.assertEqual(sum([1, 2, 3]), 6, "Should be 6")
635
636 def test_get_pgtable_addr(self):
637
638 mem = None
639 caller = None
640 dut = RADIX(mem, caller)
641
642 mask_size=4
643 pgbase = SelectableInt(0,64)
644 addrsh = SelectableInt(0,16)
645 ret = dut._get_pgtable_addr(mask_size, pgbase, addrsh)
646 print("ret=",ret)
647 assert(ret==0)
648
649 def test_walk_tree(self):
650 # set up dummy minimal ISACaller
651 spr = {'DSISR': SelectableInt(0, 64),
652 'DAR': SelectableInt(0, 64),
653 'PIDR': SelectableInt(0, 64),
654 'PRTBL': SelectableInt(0, 64)
655 }
656 # set problem state == 0 (other unit tests, set to 1)
657 msr = SelectableInt(0, 64)
658 msr[MSRb.PR] = 0
659 class ISACaller: pass
660 caller = ISACaller()
661 caller.spr = spr
662 caller.msr = msr
663
664 shift = SelectableInt(5, 6)
665 mask = genmask(shift, 43)
666 print (" mask", bin(mask.value))
667
668 mem = Mem(row_bytes=8)
669 mem = RADIX(mem, caller)
670 # -----------------------------------------------
671 # |/|RTS1|/| RPDB | RTS2 | RPDS |
672 # -----------------------------------------------
673 # |0|1 2|3|4 55|56 58|59 63|
674 data = SelectableInt(0, 64)
675 data[1:3] = 0b01
676 data[56:59] = 0b11
677 data[59:64] = 0b01101 # mask
678 data[55] = 1
679 (rts, mbits, pgbase) = mem._decode_prte(data)
680 print (" rts", bin(rts.value), rts.bits)
681 print (" mbits", bin(mbits.value), mbits.bits)
682 print (" pgbase", hex(pgbase.value), pgbase.bits)
683 addr = SelectableInt(0x1000, 64)
684 check = mem._segment_check(addr, mbits, shift)
685 print (" segment check", check)
686
687 print("walking tree")
688 addr = SelectableInt(testaddr,64)
689 # pgbase = None
690 mode = None
691 #mbits = None
692 shift = rts
693 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
694 print(" walking tree result", result)
695
696
697 if __name__ == '__main__':
698 unittest.main()