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Add test cases for 1<<r3 predication
[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 from nmigen.back.pysim import Settle
17 from copy import copy
18 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from soc.decoder.helpers import exts, gtu, ltu, undefined
21 from soc.decoder.isa.mem import Mem
22 from soc.consts import MSRb # big-endian (PowerISA versions)
23
24 import math
25 import sys
26 import unittest
27
28 # very quick, TODO move to SelectableInt utils later
29 def genmask(shift, size):
30 res = SelectableInt(0, size)
31 for i in range(size):
32 if i < shift:
33 res[size-1-i] = SelectableInt(1, 1)
34 return res
35
36 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
37 # MSB is indexed **LOWEST** (sigh)
38 # from gem5 radixwalk.hh
39 # Bitfield<63> valid; 64 - (63 + 1) = 0
40 # Bitfield<62> leaf; 64 - (62 + 1) = 1
41
42 def rpte_valid(r):
43 return bool(r[0])
44
45 def rpte_leaf(r):
46 return bool(r[1])
47
48 ## Shift address bits 61--12 right by 0--47 bits and
49 ## supply the least significant 16 bits of the result.
50 def addrshift(addr,shift):
51 x = addr.value >> shift.value
52 return SelectableInt(x,16)
53
54 def NLB(x):
55 """
56 Next Level Base
57 right shifted by 8
58 """
59 return x[4:55]
60
61 def NLS(x):
62 """
63 Next Level Size
64 NLS >= 5
65 """
66 return x[59:63]
67
68 """
69 Get Root Page
70
71 //Accessing 2nd double word of partition table (pate1)
72 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
73 // PTCR Layout
74 // ====================================================
75 // -----------------------------------------------
76 // | /// | PATB | /// | PATS |
77 // -----------------------------------------------
78 // 0 4 51 52 58 59 63
79 // PATB[4:51] holds the base address of the Partition Table,
80 // right shifted by 12 bits.
81 // This is because the address of the Partition base is
82 // 4k aligned. Hence, the lower 12bits, which are always
83 // 0 are ommitted from the PTCR.
84 //
85 // Thus, The Partition Table Base is obtained by (PATB << 12)
86 //
87 // PATS represents the partition table size right-shifted by 12 bits.
88 // The minimal size of the partition table is 4k.
89 // Thus partition table size = (1 << PATS + 12).
90 //
91 // Partition Table
92 // ====================================================
93 // 0 PATE0 63 PATE1 127
94 // |----------------------|----------------------|
95 // | | |
96 // |----------------------|----------------------|
97 // | | |
98 // |----------------------|----------------------|
99 // | | | <-- effLPID
100 // |----------------------|----------------------|
101 // .
102 // .
103 // .
104 // |----------------------|----------------------|
105 // | | |
106 // |----------------------|----------------------|
107 //
108 // The effective LPID forms the index into the Partition Table.
109 //
110 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
111 // corresponding to that partition.
112 //
113 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
114 //
115 // PATE0 Layout
116 // -----------------------------------------------
117 // |1|RTS1|/| RPDB | RTS2 | RPDS |
118 // -----------------------------------------------
119 // 0 1 2 3 4 55 56 58 59 63
120 //
121 // HR[0] : For Radix Page table, first bit should be 1.
122 // RTS1[1:2] : Gives one fragment of the Radix treesize
123 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
124 // RTS = (RTS1 << 3 + RTS2) + 31.
125 //
126 // RPDB[4:55] = Root Page Directory Base.
127 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
128 // Thus, Root page directory size = 1 << (RPDS + 3).
129 // Note: RPDS >= 5.
130 //
131 // PATE1 Layout
132 // -----------------------------------------------
133 // |///| PRTB | // | PRTS |
134 // -----------------------------------------------
135 // 0 3 4 51 52 58 59 63
136 //
137 // PRTB[4:51] = Process Table Base. This is aligned to size.
138 // PRTS[59: 63] = Process Table Size right shifted by 12.
139 // Minimal size of the process table is 4k.
140 // Process Table Size = (1 << PRTS + 12).
141 // Note: PRTS <= 24.
142 //
143 // Computing the size aligned Process Table Base:
144 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
145 // Thus, the lower 12+PRTS bits of table_base will
146 // be zero.
147
148
149 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
150 //
151 // Process Table
152 // ==========================
153 // 0 PRTE0 63 PRTE1 127
154 // |----------------------|----------------------|
155 // | | |
156 // |----------------------|----------------------|
157 // | | |
158 // |----------------------|----------------------|
159 // | | | <-- effPID
160 // |----------------------|----------------------|
161 // .
162 // .
163 // .
164 // |----------------------|----------------------|
165 // | | |
166 // |----------------------|----------------------|
167 //
168 // The effective Process id (PID) forms the index into the Process Table.
169 //
170 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
171 // corresponding to that process
172 //
173 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
174 //
175 // PRTE0 Layout
176 // -----------------------------------------------
177 // |/|RTS1|/| RPDB | RTS2 | RPDS |
178 // -----------------------------------------------
179 // 0 1 2 3 4 55 56 58 59 63
180 //
181 // RTS1[1:2] : Gives one fragment of the Radix treesize
182 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
183 // RTS = (RTS1 << 3 + RTS2) << 31,
184 // since minimal Radix Tree size is 4G.
185 //
186 // RPDB = Root Page Directory Base.
187 // RPDS = Root Page Directory Size right shifted by 3.
188 // Thus, Root page directory size = RPDS << 3.
189 // Note: RPDS >= 5.
190 //
191 // PRTE1 Layout
192 // -----------------------------------------------
193 // | /// |
194 // -----------------------------------------------
195 // 0 63
196 // All bits are reserved.
197
198
199 """
200
201 testmem = {
202
203 0x10000: # PARTITION_TABLE_2 (not implemented yet)
204 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
205 0x800000000100000b,
206
207 0x30000: # RADIX_ROOT_PTE
208 # V = 1 L = 0 NLB = 0x400 NLS = 9
209 0x8000000000040009,
210 0x40000: # RADIX_SECOND_LEVEL
211 # V = 1 L = 1 SW = 0 RPN = 0
212 # R = 1 C = 1 ATT = 0 EAA 0x7
213 0xc000000000000187,
214
215 0x1000000: # PROCESS_TABLE_3
216 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
217 0x40000000000300ad,
218 }
219
220 # this one has a 2nd level RADIX with a RPN of 0x5000
221 testmem2 = {
222
223 0x10000: # PARTITION_TABLE_2 (not implemented yet)
224 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
225 0x800000000100000b,
226
227 0x30000: # RADIX_ROOT_PTE
228 # V = 1 L = 0 NLB = 0x400 NLS = 9
229 0x8000000000040009,
230 0x40000: # RADIX_SECOND_LEVEL
231 # V = 1 L = 1 SW = 0 RPN = 0x5000
232 # R = 1 C = 1 ATT = 0 EAA 0x7
233 0xc000000005000187,
234
235 0x1000000: # PROCESS_TABLE_3
236 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
237 0x40000000000300ad,
238 }
239
240
241 testresult = """
242 prtbl = 1000000
243 DCACHE GET 1000000 PROCESS_TABLE_3
244 DCACHE GET 30000 RADIX_ROOT_PTE V = 1 L = 0
245 DCACHE GET 40000 RADIX_SECOND_LEVEL V = 1 L = 1
246 DCACHE GET 10000 PARTITION_TABLE_2
247 translated done 1 err 0 badtree 0 addr 40000 pte 0
248 """
249
250 # see qemu/target/ppc/mmu-radix64.c for reference
251 class RADIX:
252 def __init__(self, mem, caller):
253 self.mem = mem
254 self.caller = caller
255 if caller is not None:
256 self.dsisr = self.caller.spr["DSISR"]
257 self.dar = self.caller.spr["DAR"]
258 self.pidr = self.caller.spr["PIDR"]
259 self.prtbl = self.caller.spr["PRTBL"]
260 self.msr = self.caller.msr
261
262 # cached page table stuff
263 self.pgtbl0 = 0
264 self.pt0_valid = False
265 self.pgtbl3 = 0
266 self.pt3_valid = False
267
268 def __call__(self, addr, sz):
269 val = self.ld(addr.value, sz, swap=False)
270 print("RADIX memread", addr, sz, val)
271 return SelectableInt(val, sz*8)
272
273 def ld(self, address, width=8, swap=True, check_in_mem=False,
274 instr_fetch=False):
275 print("RADIX: ld from addr 0x%x width %d" % (address, width))
276
277 priv = ~(self.msr(MSR_PR).value) # problem-state ==> privileged
278 if instr_fetch:
279 mode = 'EXECUTE'
280 else:
281 mode = 'LOAD'
282 addr = SelectableInt(address, 64)
283 (shift, mbits, pgbase) = self._decode_prte(addr)
284 #shift = SelectableInt(0, 32)
285
286 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
287
288 # use pte to load from phys address
289 return self.mem.ld(pte.value, width, swap, check_in_mem)
290
291 # XXX set SPRs on error
292
293 # TODO implement
294 def st(self, address, v, width=8, swap=True):
295 print("RADIX: st to addr 0x%x width %d data %x" % (address, width, v))
296
297 priv = ~(self.msr(MSR_PR).value) # problem-state ==> privileged
298 mode = 'STORE'
299 addr = SelectableInt(address, 64)
300 (shift, mbits, pgbase) = self._decode_prte(addr)
301 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
302
303 # use pte to store at phys address
304 return self.mem.st(pte.value, v, width, swap)
305
306 # XXX set SPRs on error
307
308 def memassign(self, addr, sz, val):
309 print("memassign", addr, sz, val)
310 self.st(addr.value, val.value, sz, swap=False)
311
312 def _next_level(self, addr, entry_width, swap, check_in_mem):
313 # implement read access to mmu mem here
314
315 # DO NOT perform byte-swapping: load 8 bytes (that's the entry size)
316 value = self.mem.ld(addr.value, 8, False, check_in_mem)
317 assert(value is not None, "address lookup %x not found" % addr.value)
318
319 print("addr", hex(addr.value))
320 data = SelectableInt(value, 64) # convert to SelectableInt
321 print("value", hex(value))
322 # index += 1
323 return data;
324
325 def _walk_tree(self, addr, pgbase, mode, mbits, shift, priv=1):
326 """walk tree
327
328 // vaddr 64 Bit
329 // vaddr |-----------------------------------------------------|
330 // | Unused | Used |
331 // |-----------|-----------------------------------------|
332 // | 0000000 | usefulBits = X bits (typically 52) |
333 // |-----------|-----------------------------------------|
334 // | |<--Cursize---->| |
335 // | | Index | |
336 // | | into Page | |
337 // | | Directory | |
338 // |-----------------------------------------------------|
339 // | |
340 // V |
341 // PDE |---------------------------| |
342 // |V|L|//| NLB |///|NLS| |
343 // |---------------------------| |
344 // PDE = Page Directory Entry |
345 // [0] = V = Valid Bit |
346 // [1] = L = Leaf bit. If 0, then |
347 // [4:55] = NLB = Next Level Base |
348 // right shifted by 8 |
349 // [59:63] = NLS = Next Level Size |
350 // | NLS >= 5 |
351 // | V
352 // | |--------------------------|
353 // | | usfulBits = X-Cursize |
354 // | |--------------------------|
355 // |---------------------><--NLS-->| |
356 // | Index | |
357 // | into | |
358 // | PDE | |
359 // |--------------------------|
360 // |
361 // If the next PDE obtained by |
362 // (NLB << 8 + 8 * index) is a |
363 // nonleaf, then repeat the above. |
364 // |
365 // If the next PDE is a leaf, |
366 // then Leaf PDE structure is as |
367 // follows |
368 // |
369 // |
370 // Leaf PDE |
371 // |------------------------------| |----------------|
372 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
373 // |------------------------------| |----------------|
374 // [0] = V = Valid Bit |
375 // [1] = L = Leaf Bit = 1 if leaf |
376 // PDE |
377 // [2] = Sw = Sw bit 0. |
378 // [7:51] = RPN = Real Page Number, V
379 // real_page = RPN << 12 -------------> Logical OR
380 // [52:54] = Sw Bits 1:3 |
381 // [55] = R = Reference |
382 // [56] = C = Change V
383 // [58:59] = Att = Physical Address
384 // 0b00 = Normal Memory
385 // 0b01 = SAO
386 // 0b10 = Non Idenmpotent
387 // 0b11 = Tolerant I/O
388 // [60:63] = Encoded Access
389 // Authority
390 //
391 """
392 # get sprs
393 print("_walk_tree")
394 pidr = self.caller.spr["PIDR"]
395 prtbl = self.caller.spr["PRTBL"]
396 print(pidr)
397 print(prtbl)
398 p = addr[55:63]
399 print("last 8 bits ----------")
400 print
401
402 # get address of root entry
403 shift = selectconcat(SelectableInt(0,1), prtbl[58:63]) # TODO verify
404 addr_next = self._get_prtable_addr(shift, prtbl, addr, pidr)
405 print("starting with prtable, addr_next",addr_next)
406
407 assert(addr_next.bits == 64)
408 assert(addr_next.value == 0x1000000) #TODO
409
410 # read an entry from prtable
411 swap = False
412 check_in_mem = False
413 entry_width = 8
414 data = self._next_level(addr_next, entry_width, swap, check_in_mem)
415 print("pr_table",data)
416 pgtbl = data # this is cached in microwatt (as v.pgtbl3 / v.pgtbl0)
417
418 # rts = shift = unsigned('0' & data(62 downto 61) & data(7 downto 5));
419 shift = selectconcat(SelectableInt(0,1), data[1:3], data[55:58])
420 assert(shift.bits==6) # variable rts : unsigned(5 downto 0);
421 print("shift",shift)
422
423 # mbits := unsigned('0' & data(4 downto 0));
424 mbits = selectconcat(SelectableInt(0,1), data[58:63])
425 assert(mbits.bits==6) #variable mbits : unsigned(5 downto 0);
426
427 # WIP
428 if mbits==0:
429 return "invalid"
430
431 # mask_size := mbits(4 downto 0);
432 mask_size = mbits[0:5];
433 assert(mask_size.bits==5)
434 print("before segment check ==========")
435 print("mask_size:",bin(mask_size.value))
436 print("mbits:",bin(mbits.value))
437
438 print("calling segment_check")
439
440 mbits = selectconcat(SelectableInt(0,1), mask_size)
441 new_shift = self._segment_check(addr, mbits, shift)
442 print("new_shift",new_shift)
443
444 # v.pgbase := pgtbl(55 downto 8) & x"00";
445 leftzeros = SelectableInt(0,15)
446 pgbase = selectconcat(leftzeros,pgtbl[8:55],SelectableInt(0,2))
447 # FIXME number of bits is wrong, assertion fails
448 print("pgbase",pgbase)
449 print("pgbase[8:45]",pgbase[8:45])
450 print("pgbase[45:61]",pgbase[45:61])
451 #addr_next = self._get_pgtable_addr(mask_size, pgbase, new_shift)
452 #print("DONE ",addr_next)
453 return None
454
455 #addr_next = SelectableInt(0x30000,64) # radix root for testing
456 # this needs to be calculated using the code above
457
458 # walk tree starts on prtbl
459 while True:
460 print("nextlevel----------------------------")
461 # read an entry
462 swap = False
463 check_in_mem = False
464 entry_width = 8
465
466 data = self._next_level(addr_next, entry_width, swap, check_in_mem)
467 valid = rpte_valid(data)
468 leaf = rpte_leaf(data)
469
470 print(" valid, leaf", valid, leaf)
471 if not valid:
472 return "invalid" # TODO: return error
473 if leaf:
474 print ("is leaf, checking perms")
475 ok = self._check_perms(data, priv, mode)
476 if ok == True: # data was ok, found phys address, return it?
477 paddr = self._get_pte(addrsh, addr, data)
478 print (" phys addr", hex(paddr.value))
479 return paddr
480 return ok # return the error code
481 else:
482 newlookup = self._new_lookup(data, shift)
483 if newlookup == 'badtree':
484 return newlookup
485 shift, mask, pgbase = newlookup
486 print (" next level", shift, mask, pgbase)
487 shift = SelectableInt(shift.value,16) #THIS is wrong !!!
488 print("calling _get_pgtable_addr")
489 print(mask) #SelectableInt(value=0x9, bits=4)
490 print(pgbase) #SelectableInt(value=0x40000, bits=56)
491 print(shift) #SelectableInt(value=0x4, bits=16) #FIXME
492 pgbase = SelectableInt(pgbase.value, 64)
493 addrsh = addrshift(addr,shift)
494 addr_next = self._get_pgtable_addr(mask, pgbase, addrsh)
495 print("addr_next",addr_next)
496 print("addrsh",addrsh)
497
498 def _new_lookup(self, data, shift):
499 """
500 mbits := unsigned('0' & data(4 downto 0));
501 if mbits < 5 or mbits > 16 or mbits > r.shift then
502 v.state := RADIX_FINISH;
503 v.badtree := '1'; -- throw error
504 else
505 v.shift := v.shift - mbits;
506 v.mask_size := mbits(4 downto 0);
507 v.pgbase := data(55 downto 8) & x"00"; NLB?
508 v.state := RADIX_LOOKUP; --> next level
509 end if;
510 """
511 mbits = data[59:64]
512 print("mbits=", mbits)
513 if mbits < 5 or mbits > 16: #fixme compare with r.shift
514 print("badtree")
515 return "badtree"
516 # reduce shift (has to be done at same bitwidth)
517 shift = shift - selectconcat(SelectableInt(0, 1), mbits)
518 mask_size = mbits[1:5] # get 4 LSBs
519 pgbase = selectconcat(data[8:56], SelectableInt(0, 8)) # shift up 8
520 return shift, mask_size, pgbase
521
522 def _decode_prte(self, data):
523 """PRTE0 Layout
524 -----------------------------------------------
525 |/|RTS1|/| RPDB | RTS2 | RPDS |
526 -----------------------------------------------
527 0 1 2 3 4 55 56 58 59 63
528 """
529 # note that SelectableInt does big-endian! so the indices
530 # below *directly* match the spec, unlike microwatt which
531 # has to turn them around (to LE)
532 zero = SelectableInt(0, 1)
533 rts = selectconcat(zero,
534 data[56:59], # RTS2
535 data[1:3], # RTS1
536 )
537 masksize = data[59:64] # RPDS
538 mbits = selectconcat(zero, masksize)
539 pgbase = selectconcat(data[8:56], # part of RPDB
540 SelectableInt(0, 16),)
541
542 return (rts, mbits, pgbase)
543
544 def _segment_check(self, addr, mbits, shift):
545 """checks segment valid
546 mbits := '0' & r.mask_size;
547 v.shift := r.shift + (31 - 12) - mbits;
548 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
549 if r.addr(63) /= r.addr(62) or nonzero = '1' then
550 v.state := RADIX_FINISH;
551 v.segerror := '1';
552 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
553 v.state := RADIX_FINISH;
554 v.badtree := '1';
555 else
556 v.state := RADIX_LOOKUP;
557 """
558 # note that SelectableInt does big-endian! so the indices
559 # below *directly* match the spec, unlike microwatt which
560 # has to turn them around (to LE)
561 mask = genmask(shift, 44)
562 nonzero = addr[2:33] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
563 print ("RADIX _segment_check nonzero", bin(nonzero.value))
564 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
565 if addr[0] != addr[1] or nonzero != 0:
566 return "segerror"
567 limit = shift + (31 - 12)
568 if mbits.value < 5 or mbits.value > 16 or mbits.value > limit.value:
569 return "badtree mbits="+str(mbits.value)+" limit="+str(limit.value)
570 new_shift = shift + (31 - 12) - mbits
571 # TODO verify that returned result is correct
572 return new_shift
573
574 def _check_perms(self, data, priv, mode):
575 """check page permissions
576 // Leaf PDE |
577 // |------------------------------| |----------------|
578 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
579 // |------------------------------| |----------------|
580 // [0] = V = Valid Bit |
581 // [1] = L = Leaf Bit = 1 if leaf |
582 // PDE |
583 // [2] = Sw = Sw bit 0. |
584 // [7:51] = RPN = Real Page Number, V
585 // real_page = RPN << 12 -------------> Logical OR
586 // [52:54] = Sw Bits 1:3 |
587 // [55] = R = Reference |
588 // [56] = C = Change V
589 // [58:59] = Att = Physical Address
590 // 0b00 = Normal Memory
591 // 0b01 = SAO
592 // 0b10 = Non Idenmpotent
593 // 0b11 = Tolerant I/O
594 // [60:63] = Encoded Access
595 // Authority
596 //
597 -- test leaf bit
598 -- check permissions and RC bits
599 perm_ok := '0';
600 if r.priv = '1' or data(3) = '0' then
601 if r.iside = '0' then
602 perm_ok := data(1) or (data(2) and not r.store);
603 else
604 -- no IAMR, so no KUEP support for now
605 -- deny execute permission if cache inhibited
606 perm_ok := data(0) and not data(5);
607 end if;
608 end if;
609 rc_ok := data(8) and (data(7) or not r.store);
610 if perm_ok = '1' and rc_ok = '1' then
611 v.state := RADIX_LOAD_TLB;
612 else
613 v.state := RADIX_FINISH;
614 v.perm_err := not perm_ok;
615 -- permission error takes precedence over RC error
616 v.rc_error := perm_ok;
617 end if;
618 """
619 # decode mode into something that matches microwatt equivalent code
620 instr_fetch, store = 0, 0
621 if mode == 'STORE':
622 store = 1
623 if mode == 'EXECUTE':
624 inst_fetch = 1
625
626 # check permissions and RC bits
627 perm_ok = 0
628 if priv == 1 or data[60] == 0:
629 if instr_fetch == 0:
630 perm_ok = data[62] | (data[61] & (store == 0))
631 # no IAMR, so no KUEP support for now
632 # deny execute permission if cache inhibited
633 perm_ok = data[63] & ~data[58]
634 rc_ok = data[55] & (data[56] | (store == 0))
635 if perm_ok == 1 and rc_ok == 1:
636 return True
637
638 return "perm_err" if perm_ok == 0 else "rc_err"
639
640 def _get_prtable_addr(self, shift, prtbl, addr, pid):
641 """
642 if r.addr(63) = '1' then
643 effpid := x"00000000";
644 else
645 effpid := r.pid;
646 end if;
647 x"00" & r.prtbl(55 downto 36) &
648 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
649 (effpid(31 downto 8) and finalmask(23 downto 0))) &
650 effpid(7 downto 0) & "0000";
651 """
652 print ("_get_prtable_addr", shift, prtbl, addr, pid)
653 finalmask = genmask(shift, 44)
654 finalmask24 = finalmask[20:44]
655 if addr[0].value == 1:
656 effpid = SelectableInt(0, 32)
657 else:
658 effpid = pid #self.pid # TODO, check on this
659 zero8 = SelectableInt(0, 8)
660 zero4 = SelectableInt(0, 4)
661 res = selectconcat(zero8,
662 prtbl[8:28], #
663 (prtbl[28:52] & ~finalmask24) | #
664 (effpid[0:24] & finalmask24), #
665 effpid[24:32],
666 zero4
667 )
668 return res
669
670 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
671 """
672 x"00" & r.pgbase(55 downto 19) &
673 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
674 "000";
675 """
676 mask16 = genmask(mask_size+5, 16)
677 zero8 = SelectableInt(0, 8)
678 zero3 = SelectableInt(0, 3)
679 res = selectconcat(zero8,
680 pgbase[8:45], #
681 (pgbase[45:61] & ~mask16) | #
682 (addrsh & mask16), #
683 zero3
684 )
685 return res
686
687 def _get_pte(self, shift, addr, pde):
688 """
689 x"00" &
690 ((r.pde(55 downto 12) and not finalmask) or
691 (r.addr(55 downto 12) and finalmask))
692 & r.pde(11 downto 0);
693 """
694 shift.value = 12
695 finalmask = genmask(shift, 44)
696 zero8 = SelectableInt(0, 8)
697 rpn = pde[8:52] # RPN = Real Page Number
698 abits = addr[8:52] # non-masked address bits
699 print(" get_pte RPN", hex(rpn.value))
700 print(" abits", hex(abits.value))
701 print(" shift", shift.value)
702 print(" finalmask", bin(finalmask.value))
703 res = selectconcat(zero8,
704 (rpn & ~finalmask) | #
705 (abits & finalmask), #
706 addr[52:64],
707 )
708 return res
709
710 class TestRadixMMU(unittest.TestCase):
711
712 def test_genmask(self):
713 shift = SelectableInt(5, 6)
714 mask = genmask(shift, 43)
715 print (" mask", bin(mask.value))
716
717 self.assertEqual(mask.value, 0b11111, "mask should be 5 1s")
718
719 def test_get_pgtable_addr(self):
720
721 mem = None
722 caller = None
723 dut = RADIX(mem, caller)
724
725 mask_size=4
726 pgbase = SelectableInt(0,64)
727 addrsh = SelectableInt(0,16)
728 ret = dut._get_pgtable_addr(mask_size, pgbase, addrsh)
729 print("ret=", ret)
730 self.assertEqual(ret, 0, "pgtbl_addr should be 0")
731
732 def test_walk_tree_1(self):
733
734 # test address as in
735 # https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/radix_walk_example.txt#L65
736 testaddr = 0x1000
737 expected = 0x1000
738
739 # starting prtbl
740 prtbl = 0x1000000
741
742 # set up dummy minimal ISACaller
743 spr = {'DSISR': SelectableInt(0, 64),
744 'DAR': SelectableInt(0, 64),
745 'PIDR': SelectableInt(0, 64),
746 'PRTBL': SelectableInt(prtbl, 64)
747 }
748 # set problem state == 0 (other unit tests, set to 1)
749 msr = SelectableInt(0, 64)
750 msr[MSRb.PR] = 0
751 class ISACaller: pass
752 caller = ISACaller()
753 caller.spr = spr
754 caller.msr = msr
755
756 shift = SelectableInt(5, 6)
757 mask = genmask(shift, 43)
758 print (" mask", bin(mask.value))
759
760 mem = Mem(row_bytes=8, initial_mem=testmem)
761 mem = RADIX(mem, caller)
762 # -----------------------------------------------
763 # |/|RTS1|/| RPDB | RTS2 | RPDS |
764 # -----------------------------------------------
765 # |0|1 2|3|4 55|56 58|59 63|
766 data = SelectableInt(0, 64)
767 data[1:3] = 0b01
768 data[56:59] = 0b11
769 data[59:64] = 0b01101 # mask
770 data[55] = 1
771 (rts, mbits, pgbase) = mem._decode_prte(data)
772 print (" rts", bin(rts.value), rts.bits)
773 print (" mbits", bin(mbits.value), mbits.bits)
774 print (" pgbase", hex(pgbase.value), pgbase.bits)
775 addr = SelectableInt(0x1000, 64)
776 check = mem._segment_check(addr, mbits, shift)
777 print (" segment check", check)
778
779 print("walking tree")
780 addr = SelectableInt(testaddr,64)
781 # pgbase = None
782 mode = None
783 #mbits = None
784 shift = rts
785 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
786 print(" walking tree result", result)
787 print("should be", testresult)
788 self.assertEqual(result.value, expected,
789 "expected 0x%x got 0x%x" % (expected,
790 result.value))
791
792
793 def test_walk_tree_2(self):
794
795 # test address slightly different
796 testaddr = 0x1101
797 expected = 0x5001101
798
799 # starting prtbl
800 prtbl = 0x1000000
801
802 # set up dummy minimal ISACaller
803 spr = {'DSISR': SelectableInt(0, 64),
804 'DAR': SelectableInt(0, 64),
805 'PIDR': SelectableInt(0, 64),
806 'PRTBL': SelectableInt(prtbl, 64)
807 }
808 # set problem state == 0 (other unit tests, set to 1)
809 msr = SelectableInt(0, 64)
810 msr[MSRb.PR] = 0
811 class ISACaller: pass
812 caller = ISACaller()
813 caller.spr = spr
814 caller.msr = msr
815
816 shift = SelectableInt(5, 6)
817 mask = genmask(shift, 43)
818 print (" mask", bin(mask.value))
819
820 mem = Mem(row_bytes=8, initial_mem=testmem2)
821 mem = RADIX(mem, caller)
822 # -----------------------------------------------
823 # |/|RTS1|/| RPDB | RTS2 | RPDS |
824 # -----------------------------------------------
825 # |0|1 2|3|4 55|56 58|59 63|
826 data = SelectableInt(0, 64)
827 data[1:3] = 0b01
828 data[56:59] = 0b11
829 data[59:64] = 0b01101 # mask
830 data[55] = 1
831 (rts, mbits, pgbase) = mem._decode_prte(data)
832 print (" rts", bin(rts.value), rts.bits)
833 print (" mbits", bin(mbits.value), mbits.bits)
834 print (" pgbase", hex(pgbase.value), pgbase.bits)
835 addr = SelectableInt(0x1000, 64)
836 check = mem._segment_check(addr, mbits, shift)
837 print (" segment check", check)
838
839 print("walking tree")
840 addr = SelectableInt(testaddr,64)
841 # pgbase = None
842 mode = None
843 #mbits = None
844 shift = rts
845 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
846 print(" walking tree result", result)
847 print("should be", testresult)
848 self.assertEqual(result.value, expected,
849 "expected 0x%x got 0x%x" % (expected,
850 result.value))
851
852
853 if __name__ == '__main__':
854 unittest.main()