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radixmmu.py: cleanup
[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 #from nmigen.back.pysim import Settle
17 from copy import copy
18 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from soc.decoder.helpers import exts, gtu, ltu, undefined
21 from soc.decoder.isa.mem import Mem
22 from soc.consts import MSRb # big-endian (PowerISA versions)
23
24 import math
25 import sys
26 import unittest
27
28 # very quick, TODO move to SelectableInt utils later
29 def genmask(shift, size):
30 res = SelectableInt(0, size)
31 for i in range(size):
32 if i < shift:
33 res[size-1-i] = SelectableInt(1, 1)
34 return res
35
36 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
37 # MSB is indexed **LOWEST** (sigh)
38 # from gem5 radixwalk.hh
39 # Bitfield<63> valid; 64 - (63 + 1) = 0
40 # Bitfield<62> leaf; 64 - (62 + 1) = 1
41
42 def rpte_valid(r):
43 return bool(r[0])
44
45 def rpte_leaf(r):
46 return bool(r[1])
47
48 ## Shift address bits 61--12 right by 0--47 bits and
49 ## supply the least significant 16 bits of the result.
50 def addrshift(addr,shift):
51 x = addr.value >> shift.value
52 return SelectableInt(x,16)
53
54 def NLB(x):
55 """
56 Next Level Base
57 right shifted by 8
58 """
59 return x[4:55]
60
61 def NLS(x):
62 """
63 Next Level Size
64 NLS >= 5
65 """
66 return x[59:63]
67
68 def RPDB(x):
69 """
70 Root Page Directory Base
71 power isa docs says 4:55 investigate
72 """
73 return x[8:56]
74
75 """
76 Get Root Page
77
78 //Accessing 2nd double word of partition table (pate1)
79 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
80 // PTCR Layout
81 // ====================================================
82 // -----------------------------------------------
83 // | /// | PATB | /// | PATS |
84 // -----------------------------------------------
85 // 0 4 51 52 58 59 63
86 // PATB[4:51] holds the base address of the Partition Table,
87 // right shifted by 12 bits.
88 // This is because the address of the Partition base is
89 // 4k aligned. Hence, the lower 12bits, which are always
90 // 0 are ommitted from the PTCR.
91 //
92 // Thus, The Partition Table Base is obtained by (PATB << 12)
93 //
94 // PATS represents the partition table size right-shifted by 12 bits.
95 // The minimal size of the partition table is 4k.
96 // Thus partition table size = (1 << PATS + 12).
97 //
98 // Partition Table
99 // ====================================================
100 // 0 PATE0 63 PATE1 127
101 // |----------------------|----------------------|
102 // | | |
103 // |----------------------|----------------------|
104 // | | |
105 // |----------------------|----------------------|
106 // | | | <-- effLPID
107 // |----------------------|----------------------|
108 // .
109 // .
110 // .
111 // |----------------------|----------------------|
112 // | | |
113 // |----------------------|----------------------|
114 //
115 // The effective LPID forms the index into the Partition Table.
116 //
117 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
118 // corresponding to that partition.
119 //
120 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
121 //
122 // PATE0 Layout
123 // -----------------------------------------------
124 // |1|RTS1|/| RPDB | RTS2 | RPDS |
125 // -----------------------------------------------
126 // 0 1 2 3 4 55 56 58 59 63
127 //
128 // HR[0] : For Radix Page table, first bit should be 1.
129 // RTS1[1:2] : Gives one fragment of the Radix treesize
130 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
131 // RTS = (RTS1 << 3 + RTS2) + 31.
132 //
133 // RPDB[4:55] = Root Page Directory Base.
134 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
135 // Thus, Root page directory size = 1 << (RPDS + 3).
136 // Note: RPDS >= 5.
137 //
138 // PATE1 Layout
139 // -----------------------------------------------
140 // |///| PRTB | // | PRTS |
141 // -----------------------------------------------
142 // 0 3 4 51 52 58 59 63
143 //
144 // PRTB[4:51] = Process Table Base. This is aligned to size.
145 // PRTS[59: 63] = Process Table Size right shifted by 12.
146 // Minimal size of the process table is 4k.
147 // Process Table Size = (1 << PRTS + 12).
148 // Note: PRTS <= 24.
149 //
150 // Computing the size aligned Process Table Base:
151 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
152 // Thus, the lower 12+PRTS bits of table_base will
153 // be zero.
154
155
156 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
157 //
158 // Process Table
159 // ==========================
160 // 0 PRTE0 63 PRTE1 127
161 // |----------------------|----------------------|
162 // | | |
163 // |----------------------|----------------------|
164 // | | |
165 // |----------------------|----------------------|
166 // | | | <-- effPID
167 // |----------------------|----------------------|
168 // .
169 // .
170 // .
171 // |----------------------|----------------------|
172 // | | |
173 // |----------------------|----------------------|
174 //
175 // The effective Process id (PID) forms the index into the Process Table.
176 //
177 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
178 // corresponding to that process
179 //
180 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
181 //
182 // PRTE0 Layout
183 // -----------------------------------------------
184 // |/|RTS1|/| RPDB | RTS2 | RPDS |
185 // -----------------------------------------------
186 // 0 1 2 3 4 55 56 58 59 63
187 //
188 // RTS1[1:2] : Gives one fragment of the Radix treesize
189 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
190 // RTS = (RTS1 << 3 + RTS2) << 31,
191 // since minimal Radix Tree size is 4G.
192 //
193 // RPDB = Root Page Directory Base.
194 // RPDS = Root Page Directory Size right shifted by 3.
195 // Thus, Root page directory size = RPDS << 3.
196 // Note: RPDS >= 5.
197 //
198 // PRTE1 Layout
199 // -----------------------------------------------
200 // | /// |
201 // -----------------------------------------------
202 // 0 63
203 // All bits are reserved.
204
205
206 """
207
208 testmem = {
209
210 0x10000: # PARTITION_TABLE_2 (not implemented yet)
211 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
212 0x800000000100000b,
213
214 0x30000: # RADIX_ROOT_PTE
215 # V = 1 L = 0 NLB = 0x400 NLS = 9
216 0x8000000000040009,
217 0x40000: # RADIX_SECOND_LEVEL
218 # V = 1 L = 1 SW = 0 RPN = 0
219 # R = 1 C = 1 ATT = 0 EAA 0x7
220 0xc000000000000187,
221
222 0x1000000: # PROCESS_TABLE_3
223 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
224 0x40000000000300ad,
225 }
226
227 # this one has a 2nd level RADIX with a RPN of 0x5000
228 testmem2 = {
229
230 0x10000: # PARTITION_TABLE_2 (not implemented yet)
231 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
232 0x800000000100000b,
233
234 0x30000: # RADIX_ROOT_PTE
235 # V = 1 L = 0 NLB = 0x400 NLS = 9
236 0x8000000000040009,
237 0x40000: # RADIX_SECOND_LEVEL
238 # V = 1 L = 1 SW = 0 RPN = 0x5000
239 # R = 1 C = 1 ATT = 0 EAA 0x7
240 0xc000000005000187,
241
242 0x1000000: # PROCESS_TABLE_3
243 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
244 0x40000000000300ad,
245 }
246
247 testresult = """
248 prtbl = 1000000
249 DCACHE GET 1000000 PROCESS_TABLE_3
250 DCACHE GET 30000 RADIX_ROOT_PTE V = 1 L = 0
251 DCACHE GET 40000 RADIX_SECOND_LEVEL V = 1 L = 1
252 DCACHE GET 10000 PARTITION_TABLE_2
253 translated done 1 err 0 badtree 0 addr 40000 pte 0
254 """
255
256 # see qemu/target/ppc/mmu-radix64.c for reference
257 class RADIX:
258 def __init__(self, mem, caller):
259 self.mem = mem
260 self.caller = caller
261 if caller is not None:
262 self.dsisr = self.caller.spr["DSISR"]
263 self.dar = self.caller.spr["DAR"]
264 self.pidr = self.caller.spr["PIDR"]
265 self.prtbl = self.caller.spr["PRTBL"]
266 self.msr = self.caller.msr
267
268 # cached page table stuff
269 self.pgtbl0 = 0
270 self.pt0_valid = False
271 self.pgtbl3 = 0
272 self.pt3_valid = False
273
274 def __call__(self, addr, sz):
275 val = self.ld(addr.value, sz, swap=False)
276 print("RADIX memread", addr, sz, val)
277 return SelectableInt(val, sz*8)
278
279 def ld(self, address, width=8, swap=True, check_in_mem=False,
280 instr_fetch=False):
281 print("RADIX: ld from addr 0x%x width %d" % (address, width))
282
283 priv = ~(self.msr(MSR_PR).value) # problem-state ==> privileged
284 if instr_fetch:
285 mode = 'EXECUTE'
286 else:
287 mode = 'LOAD'
288 addr = SelectableInt(address, 64)
289 (shift, mbits, pgbase) = self._decode_prte(addr)
290 #shift = SelectableInt(0, 32)
291
292 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
293
294 # use pte to load from phys address
295 return self.mem.ld(pte.value, width, swap, check_in_mem)
296
297 # XXX set SPRs on error
298
299 # TODO implement
300 def st(self, address, v, width=8, swap=True):
301 print("RADIX: st to addr 0x%x width %d data %x" % (address, width, v))
302
303 priv = ~(self.msr(MSR_PR).value) # problem-state ==> privileged
304 mode = 'STORE'
305 addr = SelectableInt(address, 64)
306 (shift, mbits, pgbase) = self._decode_prte(addr)
307 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
308
309 # use pte to store at phys address
310 return self.mem.st(pte.value, v, width, swap)
311
312 # XXX set SPRs on error
313
314 def memassign(self, addr, sz, val):
315 print("memassign", addr, sz, val)
316 self.st(addr.value, val.value, sz, swap=False)
317
318 def _next_level(self, addr, entry_width, swap, check_in_mem):
319 # implement read access to mmu mem here
320
321 # DO NOT perform byte-swapping: load 8 bytes (that's the entry size)
322 value = self.mem.ld(addr.value, 8, False, check_in_mem)
323 if value is None:
324 return "address lookup %x not found" % addr.value
325 # assert(value is not None, "address lookup %x not found" % addr.value)
326
327 print("addr", hex(addr.value))
328 data = SelectableInt(value, 64) # convert to SelectableInt
329 print("value", hex(value))
330 # index += 1
331 return data;
332
333 def _walk_tree(self, addr, pgbase, mode, mbits, shift, priv=1):
334 """walk tree
335
336 // vaddr 64 Bit
337 // vaddr |-----------------------------------------------------|
338 // | Unused | Used |
339 // |-----------|-----------------------------------------|
340 // | 0000000 | usefulBits = X bits (typically 52) |
341 // |-----------|-----------------------------------------|
342 // | |<--Cursize---->| |
343 // | | Index | |
344 // | | into Page | |
345 // | | Directory | |
346 // |-----------------------------------------------------|
347 // | |
348 // V |
349 // PDE |---------------------------| |
350 // |V|L|//| NLB |///|NLS| |
351 // |---------------------------| |
352 // PDE = Page Directory Entry |
353 // [0] = V = Valid Bit |
354 // [1] = L = Leaf bit. If 0, then |
355 // [4:55] = NLB = Next Level Base |
356 // right shifted by 8 |
357 // [59:63] = NLS = Next Level Size |
358 // | NLS >= 5 |
359 // | V
360 // | |--------------------------|
361 // | | usfulBits = X-Cursize |
362 // | |--------------------------|
363 // |---------------------><--NLS-->| |
364 // | Index | |
365 // | into | |
366 // | PDE | |
367 // |--------------------------|
368 // |
369 // If the next PDE obtained by |
370 // (NLB << 8 + 8 * index) is a |
371 // nonleaf, then repeat the above. |
372 // |
373 // If the next PDE is a leaf, |
374 // then Leaf PDE structure is as |
375 // follows |
376 // |
377 // |
378 // Leaf PDE |
379 // |------------------------------| |----------------|
380 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
381 // |------------------------------| |----------------|
382 // [0] = V = Valid Bit |
383 // [1] = L = Leaf Bit = 1 if leaf |
384 // PDE |
385 // [2] = Sw = Sw bit 0. |
386 // [7:51] = RPN = Real Page Number, V
387 // real_page = RPN << 12 -------------> Logical OR
388 // [52:54] = Sw Bits 1:3 |
389 // [55] = R = Reference |
390 // [56] = C = Change V
391 // [58:59] = Att = Physical Address
392 // 0b00 = Normal Memory
393 // 0b01 = SAO
394 // 0b10 = Non Idenmpotent
395 // 0b11 = Tolerant I/O
396 // [60:63] = Encoded Access
397 // Authority
398 //
399 """
400 # get sprs
401 print("_walk_tree")
402 pidr = self.caller.spr["PIDR"]
403 prtbl = self.caller.spr["PRTBL"]
404 print(pidr)
405 print(prtbl)
406 p = addr[55:63]
407 print("last 8 bits ----------")
408 print
409
410 # get address of root entry
411 shift = selectconcat(SelectableInt(0,1), prtbl[58:63]) # TODO verify
412 addr_next = self._get_prtable_addr(shift, prtbl, addr, pidr)
413 print("starting with prtable, addr_next",addr_next)
414
415 assert(addr_next.bits == 64)
416 assert(addr_next.value == 0x1000000) #TODO
417
418 # read an entry from prtable
419 swap = False
420 check_in_mem = False
421 entry_width = 8
422 data = self._next_level(addr_next, entry_width, swap, check_in_mem)
423 print("pr_table",data)
424 pgtbl = data # this is cached in microwatt (as v.pgtbl3 / v.pgtbl0)
425
426 # rts = shift = unsigned('0' & data(62 downto 61) & data(7 downto 5));
427 shift = selectconcat(SelectableInt(0,1), data[1:3], data[55:58])
428 assert(shift.bits==6) # variable rts : unsigned(5 downto 0);
429 print("shift",shift)
430
431 # mbits := unsigned('0' & data(4 downto 0));
432 mbits = selectconcat(SelectableInt(0,1), data[58:63])
433 assert(mbits.bits==6) #variable mbits : unsigned(5 downto 0);
434
435 # WIP
436 if mbits==0:
437 return "invalid"
438
439 # mask_size := mbits(4 downto 0);
440 mask_size = mbits[0:5];
441 assert(mask_size.bits==5)
442 print("before segment check ==========")
443 print("mask_size:",bin(mask_size.value))
444 print("mbits:",bin(mbits.value))
445
446 print("calling segment_check")
447
448 mbits = selectconcat(SelectableInt(0,1), mask_size)
449 shift = self._segment_check(addr, mbits, shift)
450 print("shift",shift)
451
452 # v.pgbase := pgtbl(55 downto 8) & x"00";
453 # see test_RPDB for reference
454 zero8 = SelectableInt(0,8)
455
456 pgbase = selectconcat(zero8,RPDB(pgtbl),zero8)
457 print("pgbase",pgbase)
458 assert(pgbase.value==0x30000)
459
460 addrsh = addrshift(addr,shift)
461 print("addrsh",addrsh)
462
463 addr_next = self._get_pgtable_addr(mask_size, pgbase, addrsh)
464 print("DONE addr_next",addr_next)
465
466 # walk tree
467 while True:
468 print("nextlevel----------------------------")
469 # read an entry
470 swap = False
471 check_in_mem = False
472 entry_width = 8
473
474 data = self._next_level(addr_next, entry_width, swap, check_in_mem)
475 valid = rpte_valid(data)
476 leaf = rpte_leaf(data)
477
478 print(" valid, leaf", valid, leaf)
479 if not valid:
480 return "invalid" # TODO: return error
481 if leaf:
482 print ("is leaf, checking perms")
483 ok = self._check_perms(data, priv, mode)
484 if ok == True: # data was ok, found phys address, return it?
485 paddr = self._get_pte(addrsh, addr, data)
486 print (" phys addr", hex(paddr.value))
487 return paddr
488 return ok # return the error code
489 else:
490 newlookup = self._new_lookup(data, shift)
491 if newlookup == 'badtree':
492 return newlookup
493 shift, mask, pgbase = newlookup
494 print (" next level", shift, mask, pgbase)
495 shift = SelectableInt(shift.value,16) #THIS is wrong !!!
496 print("calling _get_pgtable_addr")
497 print(mask) #SelectableInt(value=0x9, bits=4)
498 print(pgbase) #SelectableInt(value=0x40000, bits=56)
499 print(shift) #SelectableInt(value=0x4, bits=16) #FIXME
500 pgbase = SelectableInt(pgbase.value, 64)
501 addrsh = addrshift(addr,shift)
502 addr_next = self._get_pgtable_addr(mask, pgbase, addrsh)
503 print("addr_next",addr_next)
504 print("addrsh",addrsh)
505
506 def _new_lookup(self, data, shift):
507 """
508 mbits := unsigned('0' & data(4 downto 0));
509 if mbits < 5 or mbits > 16 or mbits > r.shift then
510 v.state := RADIX_FINISH;
511 v.badtree := '1'; -- throw error
512 else
513 v.shift := v.shift - mbits;
514 v.mask_size := mbits(4 downto 0);
515 v.pgbase := data(55 downto 8) & x"00"; NLB?
516 v.state := RADIX_LOOKUP; --> next level
517 end if;
518 """
519 mbits = data[59:64]
520 print("mbits=", mbits)
521 if mbits < 5 or mbits > 16: #fixme compare with r.shift
522 print("badtree")
523 return "badtree"
524 # reduce shift (has to be done at same bitwidth)
525 shift = shift - selectconcat(SelectableInt(0, 1), mbits)
526 mask_size = mbits[1:5] # get 4 LSBs
527 pgbase = selectconcat(data[8:56], SelectableInt(0, 8)) # shift up 8
528 return shift, mask_size, pgbase
529
530 def _decode_prte(self, data):
531 """PRTE0 Layout
532 -----------------------------------------------
533 |/|RTS1|/| RPDB | RTS2 | RPDS |
534 -----------------------------------------------
535 0 1 2 3 4 55 56 58 59 63
536 """
537 # note that SelectableInt does big-endian! so the indices
538 # below *directly* match the spec, unlike microwatt which
539 # has to turn them around (to LE)
540 zero = SelectableInt(0, 1)
541 rts = selectconcat(zero,
542 data[56:59], # RTS2
543 data[1:3], # RTS1
544 )
545 masksize = data[59:64] # RPDS
546 mbits = selectconcat(zero, masksize)
547 pgbase = selectconcat(data[8:56], # part of RPDB
548 SelectableInt(0, 16),)
549
550 return (rts, mbits, pgbase)
551
552 def _segment_check(self, addr, mbits, shift):
553 """checks segment valid
554 mbits := '0' & r.mask_size;
555 v.shift := r.shift + (31 - 12) - mbits;
556 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
557 if r.addr(63) /= r.addr(62) or nonzero = '1' then
558 v.state := RADIX_FINISH;
559 v.segerror := '1';
560 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
561 v.state := RADIX_FINISH;
562 v.badtree := '1';
563 else
564 v.state := RADIX_LOOKUP;
565 """
566 # note that SelectableInt does big-endian! so the indices
567 # below *directly* match the spec, unlike microwatt which
568 # has to turn them around (to LE)
569 mask = genmask(shift, 44)
570 nonzero = addr[2:33] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
571 print ("RADIX _segment_check nonzero", bin(nonzero.value))
572 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
573 if addr[0] != addr[1] or nonzero != 0:
574 return "segerror"
575 limit = shift + (31 - 12)
576 if mbits.value < 5 or mbits.value > 16 or mbits.value > limit.value:
577 return "badtree mbits="+str(mbits.value)+" limit="+str(limit.value)
578 new_shift = shift + (31 - 12) - mbits
579 # TODO verify that returned result is correct
580 return new_shift
581
582 def _check_perms(self, data, priv, mode):
583 """check page permissions
584 // Leaf PDE |
585 // |------------------------------| |----------------|
586 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
587 // |------------------------------| |----------------|
588 // [0] = V = Valid Bit |
589 // [1] = L = Leaf Bit = 1 if leaf |
590 // PDE |
591 // [2] = Sw = Sw bit 0. |
592 // [7:51] = RPN = Real Page Number, V
593 // real_page = RPN << 12 -------------> Logical OR
594 // [52:54] = Sw Bits 1:3 |
595 // [55] = R = Reference |
596 // [56] = C = Change V
597 // [58:59] = Att = Physical Address
598 // 0b00 = Normal Memory
599 // 0b01 = SAO
600 // 0b10 = Non Idenmpotent
601 // 0b11 = Tolerant I/O
602 // [60:63] = Encoded Access
603 // Authority
604 //
605 -- test leaf bit
606 -- check permissions and RC bits
607 perm_ok := '0';
608 if r.priv = '1' or data(3) = '0' then
609 if r.iside = '0' then
610 perm_ok := data(1) or (data(2) and not r.store);
611 else
612 -- no IAMR, so no KUEP support for now
613 -- deny execute permission if cache inhibited
614 perm_ok := data(0) and not data(5);
615 end if;
616 end if;
617 rc_ok := data(8) and (data(7) or not r.store);
618 if perm_ok = '1' and rc_ok = '1' then
619 v.state := RADIX_LOAD_TLB;
620 else
621 v.state := RADIX_FINISH;
622 v.perm_err := not perm_ok;
623 -- permission error takes precedence over RC error
624 v.rc_error := perm_ok;
625 end if;
626 """
627 # decode mode into something that matches microwatt equivalent code
628 instr_fetch, store = 0, 0
629 if mode == 'STORE':
630 store = 1
631 if mode == 'EXECUTE':
632 inst_fetch = 1
633
634 # check permissions and RC bits
635 perm_ok = 0
636 if priv == 1 or data[60] == 0:
637 if instr_fetch == 0:
638 perm_ok = data[62] | (data[61] & (store == 0))
639 # no IAMR, so no KUEP support for now
640 # deny execute permission if cache inhibited
641 perm_ok = data[63] & ~data[58]
642 rc_ok = data[55] & (data[56] | (store == 0))
643 if perm_ok == 1 and rc_ok == 1:
644 return True
645
646 return "perm_err" if perm_ok == 0 else "rc_err"
647
648 def _get_prtable_addr(self, shift, prtbl, addr, pid):
649 """
650 if r.addr(63) = '1' then
651 effpid := x"00000000";
652 else
653 effpid := r.pid;
654 end if;
655 x"00" & r.prtbl(55 downto 36) &
656 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
657 (effpid(31 downto 8) and finalmask(23 downto 0))) &
658 effpid(7 downto 0) & "0000";
659 """
660 print ("_get_prtable_addr", shift, prtbl, addr, pid)
661 finalmask = genmask(shift, 44)
662 finalmask24 = finalmask[20:44]
663 if addr[0].value == 1:
664 effpid = SelectableInt(0, 32)
665 else:
666 effpid = pid #self.pid # TODO, check on this
667 zero8 = SelectableInt(0, 8)
668 zero4 = SelectableInt(0, 4)
669 res = selectconcat(zero8,
670 prtbl[8:28], #
671 (prtbl[28:52] & ~finalmask24) | #
672 (effpid[0:24] & finalmask24), #
673 effpid[24:32],
674 zero4
675 )
676 return res
677
678 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
679 """
680 x"00" & r.pgbase(55 downto 19) &
681 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
682 "000";
683 """
684 mask16 = genmask(mask_size+5, 16)
685 zero8 = SelectableInt(0, 8)
686 zero3 = SelectableInt(0, 3)
687 res = selectconcat(zero8,
688 pgbase[8:45], #
689 (pgbase[45:61] & ~mask16) | #
690 (addrsh & mask16), #
691 zero3
692 )
693 return res
694
695 def _get_pte(self, shift, addr, pde):
696 """
697 x"00" &
698 ((r.pde(55 downto 12) and not finalmask) or
699 (r.addr(55 downto 12) and finalmask))
700 & r.pde(11 downto 0);
701 """
702 shift.value = 12
703 finalmask = genmask(shift, 44)
704 zero8 = SelectableInt(0, 8)
705 rpn = pde[8:52] # RPN = Real Page Number
706 abits = addr[8:52] # non-masked address bits
707 print(" get_pte RPN", hex(rpn.value))
708 print(" abits", hex(abits.value))
709 print(" shift", shift.value)
710 print(" finalmask", bin(finalmask.value))
711 res = selectconcat(zero8,
712 (rpn & ~finalmask) | #
713 (abits & finalmask), #
714 addr[52:64],
715 )
716 return res
717
718 class TestRadixMMU(unittest.TestCase):
719
720 def test_genmask(self):
721 shift = SelectableInt(5, 6)
722 mask = genmask(shift, 43)
723 print (" mask", bin(mask.value))
724
725 self.assertEqual(mask.value, 0b11111, "mask should be 5 1s")
726
727 def test_RPDB(self):
728 inp = SelectableInt(0x40000000000300ad, 64)
729
730 rtdb = RPDB(inp)
731 print("rtdb",rtdb,bin(rtdb.value))
732 self.assertEqual(rtdb.value,0x300,"rtdb should be 0x300")
733
734 result = selectconcat(rtdb,SelectableInt(0,8))
735 print("result",result)
736
737
738 def test_get_pgtable_addr(self):
739
740 mem = None
741 caller = None
742 dut = RADIX(mem, caller)
743
744 mask_size=4
745 pgbase = SelectableInt(0,64)
746 addrsh = SelectableInt(0,16)
747 ret = dut._get_pgtable_addr(mask_size, pgbase, addrsh)
748 print("ret=", ret)
749 self.assertEqual(ret, 0, "pgtbl_addr should be 0")
750
751 def test_walk_tree_1(self):
752
753 # test address as in
754 # https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/radix_walk_example.txt#L65
755 testaddr = 0x1000
756 expected = 0x1000
757
758 # starting prtbl
759 prtbl = 0x1000000
760
761 # set up dummy minimal ISACaller
762 spr = {'DSISR': SelectableInt(0, 64),
763 'DAR': SelectableInt(0, 64),
764 'PIDR': SelectableInt(0, 64),
765 'PRTBL': SelectableInt(prtbl, 64)
766 }
767 # set problem state == 0 (other unit tests, set to 1)
768 msr = SelectableInt(0, 64)
769 msr[MSRb.PR] = 0
770 class ISACaller: pass
771 caller = ISACaller()
772 caller.spr = spr
773 caller.msr = msr
774
775 shift = SelectableInt(5, 6)
776 mask = genmask(shift, 43)
777 print (" mask", bin(mask.value))
778
779 mem = Mem(row_bytes=8, initial_mem=testmem)
780 mem = RADIX(mem, caller)
781 # -----------------------------------------------
782 # |/|RTS1|/| RPDB | RTS2 | RPDS |
783 # -----------------------------------------------
784 # |0|1 2|3|4 55|56 58|59 63|
785 data = SelectableInt(0, 64)
786 data[1:3] = 0b01
787 data[56:59] = 0b11
788 data[59:64] = 0b01101 # mask
789 data[55] = 1
790 (rts, mbits, pgbase) = mem._decode_prte(data)
791 print (" rts", bin(rts.value), rts.bits)
792 print (" mbits", bin(mbits.value), mbits.bits)
793 print (" pgbase", hex(pgbase.value), pgbase.bits)
794 addr = SelectableInt(0x1000, 64)
795 check = mem._segment_check(addr, mbits, shift)
796 print (" segment check", check)
797
798 print("walking tree")
799 addr = SelectableInt(testaddr,64)
800 # pgbase = None
801 mode = None
802 #mbits = None
803 shift = rts
804 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
805 print(" walking tree result", result)
806 print("should be", testresult)
807 self.assertEqual(result.value, expected,
808 "expected 0x%x got 0x%x" % (expected,
809 result.value))
810
811
812 def test_walk_tree_2(self):
813
814 # test address slightly different
815 testaddr = 0x1101
816 expected = 0x5001101
817
818 # starting prtbl
819 prtbl = 0x1000000
820
821 # set up dummy minimal ISACaller
822 spr = {'DSISR': SelectableInt(0, 64),
823 'DAR': SelectableInt(0, 64),
824 'PIDR': SelectableInt(0, 64),
825 'PRTBL': SelectableInt(prtbl, 64)
826 }
827 # set problem state == 0 (other unit tests, set to 1)
828 msr = SelectableInt(0, 64)
829 msr[MSRb.PR] = 0
830 class ISACaller: pass
831 caller = ISACaller()
832 caller.spr = spr
833 caller.msr = msr
834
835 shift = SelectableInt(5, 6)
836 mask = genmask(shift, 43)
837 print (" mask", bin(mask.value))
838
839 mem = Mem(row_bytes=8, initial_mem=testmem2)
840 mem = RADIX(mem, caller)
841 # -----------------------------------------------
842 # |/|RTS1|/| RPDB | RTS2 | RPDS |
843 # -----------------------------------------------
844 # |0|1 2|3|4 55|56 58|59 63|
845 data = SelectableInt(0, 64)
846 data[1:3] = 0b01
847 data[56:59] = 0b11
848 data[59:64] = 0b01101 # mask
849 data[55] = 1
850 (rts, mbits, pgbase) = mem._decode_prte(data)
851 print (" rts", bin(rts.value), rts.bits)
852 print (" mbits", bin(mbits.value), mbits.bits)
853 print (" pgbase", hex(pgbase.value), pgbase.bits)
854 addr = SelectableInt(0x1000, 64)
855 check = mem._segment_check(addr, mbits, shift)
856 print (" segment check", check)
857
858 print("walking tree")
859 addr = SelectableInt(testaddr,64)
860 # pgbase = None
861 mode = None
862 #mbits = None
863 shift = rts
864 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
865 print(" walking tree result", result)
866 print("should be", testresult)
867 self.assertEqual(result.value, expected,
868 "expected 0x%x got 0x%x" % (expected,
869 result.value))
870
871
872 if __name__ == '__main__':
873 unittest.main()