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add instr_fetch mode to ISACaller Mem and RADIXMMU
[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 from nmigen.back.pysim import Settle
17 from copy import copy
18 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from soc.decoder.helpers import exts, gtu, ltu, undefined
21 from soc.decoder.isa.mem import Mem
22
23 import math
24 import sys
25
26 # very quick, TODO move to SelectableInt utils later
27 def genmask(shift, size):
28 res = SelectableInt(0, size)
29 for i in range(size):
30 if i < shift:
31 res[size-1-i] = SelectableInt(1, 1)
32 return res
33
34 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
35 # MSB is indexed **LOWEST** (sigh)
36 # from gem5 radixwalk.hh
37 # Bitfield<63> valid; 64 - (63 + 1) = 0
38 # Bitfield<62> leaf; 64 - (62 + 1) = 1
39
40 def rpte_valid(r):
41 return bool(r[0])
42
43 def rpte_leaf(r):
44 return bool(r[1])
45
46 def NLB(x):
47 """
48 Next Level Base
49 right shifted by 8
50 """
51 return x[4:55]
52
53 def NLS(x):
54 """
55 Next Level Size
56 NLS >= 5
57 """
58 return x[59:63]
59
60 """
61 Get Root Page
62
63 //Accessing 2nd double word of partition table (pate1)
64 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
65 // PTCR Layout
66 // ====================================================
67 // -----------------------------------------------
68 // | /// | PATB | /// | PATS |
69 // -----------------------------------------------
70 // 0 4 51 52 58 59 63
71 // PATB[4:51] holds the base address of the Partition Table,
72 // right shifted by 12 bits.
73 // This is because the address of the Partition base is
74 // 4k aligned. Hence, the lower 12bits, which are always
75 // 0 are ommitted from the PTCR.
76 //
77 // Thus, The Partition Table Base is obtained by (PATB << 12)
78 //
79 // PATS represents the partition table size right-shifted by 12 bits.
80 // The minimal size of the partition table is 4k.
81 // Thus partition table size = (1 << PATS + 12).
82 //
83 // Partition Table
84 // ====================================================
85 // 0 PATE0 63 PATE1 127
86 // |----------------------|----------------------|
87 // | | |
88 // |----------------------|----------------------|
89 // | | |
90 // |----------------------|----------------------|
91 // | | | <-- effLPID
92 // |----------------------|----------------------|
93 // .
94 // .
95 // .
96 // |----------------------|----------------------|
97 // | | |
98 // |----------------------|----------------------|
99 //
100 // The effective LPID forms the index into the Partition Table.
101 //
102 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
103 // corresponding to that partition.
104 //
105 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
106 //
107 // PATE0 Layout
108 // -----------------------------------------------
109 // |1|RTS1|/| RPDB | RTS2 | RPDS |
110 // -----------------------------------------------
111 // 0 1 2 3 4 55 56 58 59 63
112 //
113 // HR[0] : For Radix Page table, first bit should be 1.
114 // RTS1[1:2] : Gives one fragment of the Radix treesize
115 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
116 // RTS = (RTS1 << 3 + RTS2) + 31.
117 //
118 // RPDB[4:55] = Root Page Directory Base.
119 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
120 // Thus, Root page directory size = 1 << (RPDS + 3).
121 // Note: RPDS >= 5.
122 //
123 // PATE1 Layout
124 // -----------------------------------------------
125 // |///| PRTB | // | PRTS |
126 // -----------------------------------------------
127 // 0 3 4 51 52 58 59 63
128 //
129 // PRTB[4:51] = Process Table Base. This is aligned to size.
130 // PRTS[59: 63] = Process Table Size right shifted by 12.
131 // Minimal size of the process table is 4k.
132 // Process Table Size = (1 << PRTS + 12).
133 // Note: PRTS <= 24.
134 //
135 // Computing the size aligned Process Table Base:
136 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
137 // Thus, the lower 12+PRTS bits of table_base will
138 // be zero.
139
140
141 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
142 //
143 // Process Table
144 // ==========================
145 // 0 PRTE0 63 PRTE1 127
146 // |----------------------|----------------------|
147 // | | |
148 // |----------------------|----------------------|
149 // | | |
150 // |----------------------|----------------------|
151 // | | | <-- effPID
152 // |----------------------|----------------------|
153 // .
154 // .
155 // .
156 // |----------------------|----------------------|
157 // | | |
158 // |----------------------|----------------------|
159 //
160 // The effective Process id (PID) forms the index into the Process Table.
161 //
162 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
163 // corresponding to that process
164 //
165 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
166 //
167 // PRTE0 Layout
168 // -----------------------------------------------
169 // |/|RTS1|/| RPDB | RTS2 | RPDS |
170 // -----------------------------------------------
171 // 0 1 2 3 4 55 56 58 59 63
172 //
173 // RTS1[1:2] : Gives one fragment of the Radix treesize
174 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
175 // RTS = (RTS1 << 3 + RTS2) << 31,
176 // since minimal Radix Tree size is 4G.
177 //
178 // RPDB = Root Page Directory Base.
179 // RPDS = Root Page Directory Size right shifted by 3.
180 // Thus, Root page directory size = RPDS << 3.
181 // Note: RPDS >= 5.
182 //
183 // PRTE1 Layout
184 // -----------------------------------------------
185 // | /// |
186 // -----------------------------------------------
187 // 0 63
188 // All bits are reserved.
189
190
191 """
192
193 # see qemu/target/ppc/mmu-radix64.c for reference
194 class RADIX:
195 def __init__(self, mem, caller):
196 self.mem = mem
197 self.caller = caller
198 #TODO move to lookup
199 self.dsisr = self.caller.spr["DSISR"]
200 self.dar = self.caller.spr["DAR"]
201 self.pidr = self.caller.spr["PIDR"]
202 self.prtbl = self.caller.spr["PRTBL"]
203
204 # cached page table stuff
205 self.pgtbl0 = 0
206 self.pt0_valid = False
207 self.pgtbl3 = 0
208 self.pt3_valid = False
209
210 def __call__(self, addr, sz):
211 val = self.ld(addr.value, sz, swap=False)
212 print("RADIX memread", addr, sz, val)
213 return SelectableInt(val, sz*8)
214
215 def ld(self, address, width=8, swap=True, check_in_mem=False,
216 instr_fetch=False):
217 print("RADIX: ld from addr 0x%x width %d" % (address, width))
218
219 if instr_fetch:
220 mode = 'EXECUTE'
221 else:
222 mode = 'LOAD'
223 addr = SelectableInt(address, 64)
224 (shift, mbits, pgbase) = self._decode_prte(addr)
225 #shift = SelectableInt(0, 32)
226
227 pte = self._walk_tree(addr, pgbase, mode, mbits, shift)
228 # use pte to caclculate phys address
229 return self.mem.ld(address, width, swap, check_in_mem)
230
231 # XXX set SPRs on error
232
233 # TODO implement
234 def st(self, address, v, width=8, swap=True):
235 print("RADIX: st to addr 0x%x width %d data %x" % (address, width, v))
236
237 mode = 'STORE'
238 addr = SelectableInt(address, 64)
239 (shift, mbits, pgbase) = self._decode_prte(addr)
240 pte = self._walk_tree(addr, pgbase, mode, mbits, shift)
241
242 # use pte to caclculate phys address (addr)
243 return self.mem.st(addr.value, v, width, swap)
244
245 # XXX set SPRs on error
246
247 def memassign(self, addr, sz, val):
248 print("memassign", addr, sz, val)
249 self.st(addr.value, val.value, sz, swap=False)
250
251 def _next_level(self,r):
252 return rpte_valid(r), rpte_leaf(r)
253 ## DSISR_R_BADCONFIG
254 ## read_entry
255 ## DSISR_NOPTE
256 ## Prepare for next iteration
257
258 def _walk_tree(self, addr, pgbase, mode, mbits, shift):
259 """walk tree
260
261 // vaddr 64 Bit
262 // vaddr |-----------------------------------------------------|
263 // | Unused | Used |
264 // |-----------|-----------------------------------------|
265 // | 0000000 | usefulBits = X bits (typically 52) |
266 // |-----------|-----------------------------------------|
267 // | |<--Cursize---->| |
268 // | | Index | |
269 // | | into Page | |
270 // | | Directory | |
271 // |-----------------------------------------------------|
272 // | |
273 // V |
274 // PDE |---------------------------| |
275 // |V|L|//| NLB |///|NLS| |
276 // |---------------------------| |
277 // PDE = Page Directory Entry |
278 // [0] = V = Valid Bit |
279 // [1] = L = Leaf bit. If 0, then |
280 // [4:55] = NLB = Next Level Base |
281 // right shifted by 8 |
282 // [59:63] = NLS = Next Level Size |
283 // | NLS >= 5 |
284 // | V
285 // | |--------------------------|
286 // | | usfulBits = X-Cursize |
287 // | |--------------------------|
288 // |---------------------><--NLS-->| |
289 // | Index | |
290 // | into | |
291 // | PDE | |
292 // |--------------------------|
293 // |
294 // If the next PDE obtained by |
295 // (NLB << 8 + 8 * index) is a |
296 // nonleaf, then repeat the above. |
297 // |
298 // If the next PDE is a leaf, |
299 // then Leaf PDE structure is as |
300 // follows |
301 // |
302 // |
303 // Leaf PDE |
304 // |------------------------------| |----------------|
305 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
306 // |------------------------------| |----------------|
307 // [0] = V = Valid Bit |
308 // [1] = L = Leaf Bit = 1 if leaf |
309 // PDE |
310 // [2] = Sw = Sw bit 0. |
311 // [7:51] = RPN = Real Page Number, V
312 // real_page = RPN << 12 -------------> Logical OR
313 // [52:54] = Sw Bits 1:3 |
314 // [55] = R = Reference |
315 // [56] = C = Change V
316 // [58:59] = Att = Physical Address
317 // 0b00 = Normal Memory
318 // 0b01 = SAO
319 // 0b10 = Non Idenmpotent
320 // 0b11 = Tolerant I/O
321 // [60:63] = Encoded Access
322 // Authority
323 //
324 """
325 # get sprs
326 print("_walk_tree")
327 pidr = self.caller.spr["PIDR"]
328 prtbl = self.caller.spr["PRTBL"]
329 print(pidr)
330 print(prtbl)
331 p = addr[55:63]
332 print("last 8 bits ----------")
333 print
334
335 # get address of root entry
336 prtable_addr = self._get_prtable_addr(shift, prtbl, addr, pidr)
337 print("prtable_addr",prtable_addr)
338
339 # read root entry - imcomplete
340 swap = False
341 check_in_mem = False
342 entry_width = 8
343 value = self.mem.ld(prtable_addr.value, entry_width, swap, check_in_mem)
344 print("value",value)
345
346 test_input = [
347 SelectableInt(0x8000000000000007, 64), #valid
348 SelectableInt(0xc000000000000000, 64) #exit
349 ]
350 index = 0
351
352 # walk tree starts on prtbl
353 while True:
354 print("nextlevel----------------------------")
355 l = test_input[index]
356 index += 1
357 valid,leaf = self._next_level(l)
358 if not leaf:
359 mbits = l[59:64]
360 print("mbits=")
361 print(mbits)
362 if mbits < 5 or mbits > 16:
363 print("badtree")
364 return None
365 """
366 mbits := unsigned('0' & data(4 downto 0));
367 if mbits < 5 or mbits > 16 or mbits > r.shift then
368 v.state := RADIX_FINISH;
369 v.badtree := '1'; -- throw error
370 else
371 v.shift := v.shift - mbits;
372 v.mask_size := mbits(4 downto 0);
373 v.pgbase := data(55 downto 8) & x"00"; NLB?
374 v.state := RADIX_LOOKUP; --> next level
375 end if;
376 """
377 print(valid)
378 print(leaf)
379 if not valid: return None
380 if leaf: return None
381
382 def _decode_prte(self, data):
383 """PRTE0 Layout
384 -----------------------------------------------
385 |/|RTS1|/| RPDB | RTS2 | RPDS |
386 -----------------------------------------------
387 0 1 2 3 4 55 56 58 59 63
388 """
389 # note that SelectableInt does big-endian! so the indices
390 # below *directly* match the spec, unlike microwatt which
391 # has to turn them around (to LE)
392 zero = SelectableInt(0, 1)
393 rts = selectconcat(zero,
394 data[56:59], # RTS2
395 data[1:3], # RTS1
396 )
397 masksize = data[59:64] # RPDS
398 mbits = selectconcat(zero, masksize)
399 pgbase = selectconcat(data[8:56], # part of RPDB
400 SelectableInt(0, 16),)
401
402 return (rts, mbits, pgbase)
403
404 def _segment_check(self, addr, mbits, shift):
405 """checks segment valid
406 mbits := '0' & r.mask_size;
407 v.shift := r.shift + (31 - 12) - mbits;
408 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
409 if r.addr(63) /= r.addr(62) or nonzero = '1' then
410 v.state := RADIX_FINISH;
411 v.segerror := '1';
412 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
413 v.state := RADIX_FINISH;
414 v.badtree := '1';
415 else
416 v.state := RADIX_LOOKUP;
417 """
418 # note that SelectableInt does big-endian! so the indices
419 # below *directly* match the spec, unlike microwatt which
420 # has to turn them around (to LE)
421 mask = genmask(shift, 44)
422 nonzero = addr[1:32] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
423 print ("RADIX _segment_check nonzero", bin(nonzero.value))
424 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
425 if addr[0] != addr[1] or nonzero == 1:
426 return "segerror"
427 limit = shift + (31 - 12)
428 if mbits < 5 or mbits > 16 or mbits > limit:
429 return "badtree"
430 new_shift = shift + (31 - 12) - mbits
431 return new_shift
432
433 def _check_perms(self, data, priv, instr_fetch, store):
434 """check page permissions
435 // Leaf PDE |
436 // |------------------------------| |----------------|
437 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
438 // |------------------------------| |----------------|
439 // [0] = V = Valid Bit |
440 // [1] = L = Leaf Bit = 1 if leaf |
441 // PDE |
442 // [2] = Sw = Sw bit 0. |
443 // [7:51] = RPN = Real Page Number, V
444 // real_page = RPN << 12 -------------> Logical OR
445 // [52:54] = Sw Bits 1:3 |
446 // [55] = R = Reference |
447 // [56] = C = Change V
448 // [58:59] = Att = Physical Address
449 // 0b00 = Normal Memory
450 // 0b01 = SAO
451 // 0b10 = Non Idenmpotent
452 // 0b11 = Tolerant I/O
453 // [60:63] = Encoded Access
454 // Authority
455 //
456 -- test leaf bit
457 -- check permissions and RC bits
458 perm_ok := '0';
459 if r.priv = '1' or data(3) = '0' then
460 if r.iside = '0' then
461 perm_ok := data(1) or (data(2) and not r.store);
462 else
463 -- no IAMR, so no KUEP support for now
464 -- deny execute permission if cache inhibited
465 perm_ok := data(0) and not data(5);
466 end if;
467 end if;
468 rc_ok := data(8) and (data(7) or not r.store);
469 if perm_ok = '1' and rc_ok = '1' then
470 v.state := RADIX_LOAD_TLB;
471 else
472 v.state := RADIX_FINISH;
473 v.perm_err := not perm_ok;
474 -- permission error takes precedence over RC error
475 v.rc_error := perm_ok;
476 end if;
477 """
478 # check permissions and RC bits
479 perm_ok = 0
480 if priv == 1 or data[60] == 0:
481 if instr_fetch == 0:
482 perm_ok = data[62] | (data[61] & (store == 0))
483 # no IAMR, so no KUEP support for now
484 # deny execute permission if cache inhibited
485 perm_ok = data[63] & ~data[58]
486 rc_ok = data[55] & (data[56] | (store == 0))
487 if perm_ok == 1 and rc_ok == 1:
488 return True
489 return "perm_err" if perm_ok == 0 else "rc_err"
490
491 def _get_prtable_addr(self, shift, prtbl, addr, pid):
492 """
493 if r.addr(63) = '1' then
494 effpid := x"00000000";
495 else
496 effpid := r.pid;
497 end if;
498 x"00" & r.prtbl(55 downto 36) &
499 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
500 (effpid(31 downto 8) and finalmask(23 downto 0))) &
501 effpid(7 downto 0) & "0000";
502 """
503 print ("_get_prtable_addr_", shift, prtbl, addr, pid)
504 finalmask = genmask(shift, 44)
505 finalmask24 = finalmask[20:44]
506 if addr[0].value == 1:
507 effpid = SelectableInt(0, 32)
508 else:
509 effpid = pid #self.pid # TODO, check on this
510 zero16 = SelectableInt(0, 16)
511 zero4 = SelectableInt(0, 4)
512 res = selectconcat(zero16,
513 prtbl[8:28], #
514 (prtbl[28:52] & ~finalmask24) | #
515 (effpid[0:24] & finalmask24), #
516 effpid[24:32],
517 zero4
518 )
519 return res
520
521 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
522 """
523 x"00" & r.pgbase(55 downto 19) &
524 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
525 "000";
526 """
527 mask16 = genmask(mask_size+5, 16)
528 zero8 = SelectableInt(0, 8)
529 zero3 = SelectableInt(0, 3)
530 res = selectconcat(zero8,
531 pgbase[8:45], #
532 (prtbl[45:61] & ~mask16) | #
533 (addrsh & mask16), #
534 zero3
535 )
536 return res
537
538 def _get_pte(self, shift, addr, pde):
539 """
540 x"00" &
541 ((r.pde(55 downto 12) and not finalmask) or
542 (r.addr(55 downto 12) and finalmask))
543 & r.pde(11 downto 0);
544 """
545 finalmask = genmask(shift, 44)
546 zero8 = SelectableInt(0, 8)
547 res = selectconcat(zero8,
548 (pde[8:52] & ~finalmask) | #
549 (addr[8:52] & finalmask), #
550 pde[52:64],
551 )
552 return res
553
554
555 # very quick test of maskgen function (TODO, move to util later)
556 if __name__ == '__main__':
557 # set up dummy minimal ISACaller
558 spr = {'DSISR': SelectableInt(0, 64),
559 'DAR': SelectableInt(0, 64),
560 'PIDR': SelectableInt(0, 64),
561 'PRTBL': SelectableInt(0, 64)
562 }
563 class ISACaller: pass
564 caller = ISACaller()
565 caller.spr = spr
566
567 shift = SelectableInt(5, 6)
568 mask = genmask(shift, 43)
569 print (" mask", bin(mask.value))
570
571 mem = Mem(row_bytes=8)
572 mem = RADIX(mem, caller)
573 # -----------------------------------------------
574 # |/|RTS1|/| RPDB | RTS2 | RPDS |
575 # -----------------------------------------------
576 # |0|1 2|3|4 55|56 58|59 63|
577 data = SelectableInt(0, 64)
578 data[1:3] = 0b01
579 data[56:59] = 0b11
580 data[59:64] = 0b01101 # mask
581 data[55] = 1
582 (rts, mbits, pgbase) = mem._decode_prte(data)
583 print (" rts", bin(rts.value), rts.bits)
584 print (" mbits", bin(mbits.value), mbits.bits)
585 print (" pgbase", hex(pgbase.value), pgbase.bits)
586 addr = SelectableInt(0x1000, 64)
587 check = mem._segment_check(addr, mbits, shift)
588 print (" segment check", check)
589
590 print("walking tree")
591 # addr = unchanged
592 # pgbase = None
593 mode = None
594 #mbits = None
595 shift = rts
596 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
597 print(result)