1 from nmigen
import Module
, Signal
2 #from nmigen.back.pysim import Simulator, Delay, Settle
3 from nmutil
.formaltest
import FHDLTestCase
5 from soc
.decoder
.isa
.caller
import ISACaller
6 from soc
.decoder
.power_decoder
import (create_pdecode
)
7 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
8 from soc
.simulator
.program
import Program
9 from soc
.decoder
.isa
.caller
import ISACaller
, inject
, RADIX
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.decoder
.orderedset
import OrderedSet
12 from soc
.decoder
.isa
.all
import ISA
13 from soc
.decoder
.isa
.test_caller
import run_tst
17 0x1000: # data to be read
20 0x10000: # PARTITION_TABLE_2 (not implemented yet)
21 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
24 0x30000: # RADIX_ROOT_PTE
25 # V = 1 L = 0 NLB = 0x400 NLS = 9
27 0x40000: # RADIX_SECOND_LEVEL
28 # V = 1 L = 1 SW = 0 RPN = 0
29 # R = 1 C = 1 ATT = 0 EAA 0x7
32 0x1000000: # PROCESS_TABLE_3
33 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
39 class DecoderTestCase(FHDLTestCase
):
41 def test_load_store(self
):
42 lst
= [#"addi 1, 0, 0x1000",
47 with
Program(lst
, bigendian
=False) as program
:
49 initial_regs
[1] = 0x1000
50 initial_regs
[2] = 0x1234
51 sim
= self
.run_tst_program(program
,initial_regs
=initial_regs
)
52 #dump registers into file
53 #f = open("/tmp/debug.txt","w")
54 #for i in range(1,12):
55 # l = "r"+str(i)+" = "+str(sim.gpr(i))+"\n"
57 self
.assertEqual(sim
.gpr(3), SelectableInt(0x1337, 64))
59 def run_tst_program(self
, prog
, initial_regs
=[0] * 32):
60 # set up dummy minimal ISACaller
61 spr
= {'DSISR': SelectableInt(0, 64),
62 'DAR': SelectableInt(0, 64),
63 'PIDR': SelectableInt(0, 64),
64 'PRTBL': SelectableInt(prtbl
, 64)
67 simulator
= run_tst(prog
, initial_regs
, mmu
=True, mem
=testmem
,
73 if __name__
== "__main__":