1 from nmigen
import Module
, Signal
2 #from nmigen.back.pysim import Simulator, Delay, Settle
3 from nmutil
.formaltest
import FHDLTestCase
5 from soc
.decoder
.isa
.caller
import ISACaller
6 from soc
.decoder
.power_decoder
import (create_pdecode
)
7 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
8 from soc
.simulator
.program
import Program
9 from soc
.decoder
.isa
.caller
import ISACaller
, inject
, RADIX
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.decoder
.orderedset
import OrderedSet
12 from soc
.decoder
.isa
.all
import ISA
13 from soc
.decoder
.isa
.test_caller
import run_tst
16 class DecoderTestCase(FHDLTestCase
):
18 def test_load_store(self
):
19 lst
= ["addi 1, 0, 0x0010",
23 with
Program(lst
, bigendian
=False) as program
:
24 sim
= self
.run_tst_program(program
)
26 self
.assertEqual(sim
.gpr(3), SelectableInt(0x1234, 64))
28 def run_tst_program(self
, prog
, initial_regs
=[0] * 32):
29 simulator
= run_tst(prog
, initial_regs
,mmu
=True)
34 if __name__
== "__main__":