src/soc/decoder/isa/test_caller_radix.py

   1 from nmigen import Module, Signal
   2 #from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from soc.decoder.isa.caller import ISACaller
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.simulator.program import Program
   9 from soc.decoder.isa.caller import ISACaller, inject, RADIX
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.decoder.orderedset import OrderedSet
  12 from soc.decoder.isa.all import ISA
  13 from soc.decoder.isa.test_caller import run_tst
  14
  15 testmem = {
  16
  17            0x10000:    # PARTITION_TABLE_2 (not implemented yet)
  18                        # PATB_GR=1 PRTB=0x1000 PRTS=0xb
  19            0x800000000100000b,
  20
  21            0x30000:     # RADIX_ROOT_PTE
  22                         # V = 1 L = 0 NLB = 0x400 NLS = 9
  23            0x8000000000040009,
  24            0x40000:     # RADIX_SECOND_LEVEL
  25                         # V = 1 L = 1 SW = 0 RPN = 0
  26                         # R = 1 C = 1 ATT = 0 EAA 0x7
  27            0xc000000000000187,
  28
  29            0x1000000:   # PROCESS_TABLE_3
  30                         # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
  31            0x40000000000300ad,
  32           }
  33
  34 class DecoderTestCase(FHDLTestCase):
  35
  36     def test_load_store(self):
  37         lst = ["addi 1, 0, 0x0010",
  38                "addi 2, 0, 0x1234",
  39                "stw 2, 0(1)",
  40                "lwz 3, 0(1)"]
  41         with Program(lst, bigendian=False) as program:
  42             sim = self.run_tst_program(program)
  43             print(sim.gpr(1))
  44             self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
  45
  46     def run_tst_program(self, prog, initial_regs=[0] * 32):
  47         simulator = run_tst(prog, initial_regs,mmu=True,mem=testmem)
  48         simulator.gpr.dump()
  49         return simulator
  50
  51
  52 if __name__ == "__main__":
  53     unittest.main()