1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
11 from soc
.regfile
.regfiles
import XERRegs
13 from nmutil
.picker
import PriorityPicker
14 from nmutil
.iocontrol
import RecordObject
15 from nmutil
.extend
import exts
17 from soc
.experiment
.mem_types
import LDSTException
19 from soc
.decoder
.power_regspec_map
import regspec_decode_read
20 from soc
.decoder
.power_regspec_map
import regspec_decode_write
21 from soc
.decoder
.power_decoder
import create_pdecode
22 from soc
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
24 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
25 OutSel
, SPR
, RC
, LDSTMode
,
27 from soc
.decoder
.decode2execute1
import (Decode2ToExecute1Type
, Data
,
29 from soc
.sv
.svp64
import SVP64Rec
30 from soc
.consts
import (MSR
, sel
, SPEC
, EXTRA2
, EXTRA3
, SVP64P
, field
,
31 SPEC_SIZE
, SPECb
, SPEC_AUG_SIZE
)
33 from soc
.regfile
.regfiles
import FastRegs
34 from soc
.consts
import TT
35 from soc
.config
.state
import CoreState
36 from soc
.regfile
.util
import spr_to_fast
39 def decode_spr_num(spr
):
40 return Cat(spr
[5:10], spr
[0:5])
43 def instr_is_priv(m
, op
, insn
):
44 """determines if the instruction is privileged or not
47 is_priv_insn
= Signal(reset_less
=True)
49 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
50 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
51 comb
+= is_priv_insn
.eq(1)
52 with m
.Case(MicrOp
.OP_TLBIE
) : comb
+= is_priv_insn
.eq(1)
53 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
54 with m
.If(insn
[20]): # field XFX.spr[-1] i think
55 comb
+= is_priv_insn
.eq(1)
59 class SPRMap(Elaboratable
):
60 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
64 self
.spr_i
= Signal(10, reset_less
=True)
65 self
.spr_o
= Data(SPR
, name
="spr_o")
66 self
.fast_o
= Data(3, name
="fast_o")
68 def elaborate(self
, platform
):
70 with m
.Switch(self
.spr_i
):
71 for i
, x
in enumerate(SPR
):
73 m
.d
.comb
+= self
.spr_o
.data
.eq(i
)
74 m
.d
.comb
+= self
.spr_o
.ok
.eq(1)
75 for x
, v
in spr_to_fast
.items():
77 m
.d
.comb
+= self
.fast_o
.data
.eq(v
)
78 m
.d
.comb
+= self
.fast_o
.ok
.eq(1)
82 class SVP64ExtraSpec(Elaboratable
):
83 """SVP64ExtraSpec - decodes SVP64 Extra specification.
85 selects the required EXTRA2/3 field.
87 see https://libre-soc.org/openpower/sv/svp64/
90 self
.extra
= Signal(9, reset_less
=True)
91 self
.etype
= Signal(SVEtype
, reset_less
=True) # 2 or 3 bits
92 self
.idx
= Signal(SVEXTRA
, reset_less
=True) # which part of extra
93 self
.spec
= Signal(3) # EXTRA spec for the register
95 def elaborate(self
, platform
):
101 # back in the LDSTRM-* and RM-* files generated by sv_analysis.py
102 # we marked every op with an Etype: EXTRA2 or EXTRA3, and also said
103 # which of the 4 (or 3 for EXTRA3) sub-fields of bits 10:18 contain
104 # the register-extension information. extract those now
105 with m
.Switch(self
.etype
):
106 # 2-bit index selection mode
107 with m
.Case(SVEtype
.EXTRA2
):
108 with m
.Switch(self
.idx
):
109 with m
.Case(SVEXTRA
.Idx0
): # 1st 2 bits [0:1]
110 comb
+= spec
[SPEC
.VEC
].eq(extra
[EXTRA2
.IDX0_VEC
])
111 comb
+= spec
[SPEC
.MSB
].eq(extra
[EXTRA2
.IDX0_MSB
])
112 with m
.Case(SVEXTRA
.Idx1
): # 2nd 2 bits [2:3]
113 comb
+= spec
[SPEC
.VEC
].eq(extra
[EXTRA2
.IDX1_VEC
])
114 comb
+= spec
[SPEC
.MSB
].eq(extra
[EXTRA2
.IDX1_MSB
])
115 with m
.Case(SVEXTRA
.Idx2
): # 3rd 2 bits [4:5]
116 comb
+= spec
[SPEC
.VEC
].eq(extra
[EXTRA2
.IDX2_VEC
])
117 comb
+= spec
[SPEC
.MSB
].eq(extra
[EXTRA2
.IDX2_MSB
])
118 with m
.Case(SVEXTRA
.Idx3
): # 4th 2 bits [6:7]
119 comb
+= spec
[SPEC
.VEC
].eq(extra
[EXTRA2
.IDX3_VEC
])
120 comb
+= spec
[SPEC
.MSB
].eq(extra
[EXTRA2
.IDX3_MSB
])
121 # 3-bit index selection mode
122 with m
.Case(SVEtype
.EXTRA3
):
123 with m
.Switch(self
.idx
):
124 with m
.Case(SVEXTRA
.Idx0
): # 1st 3 bits [0:2]
125 comb
+= spec
.eq(sel(extra
, EXTRA3
.IDX0
))
126 with m
.Case(SVEXTRA
.Idx1
): # 2nd 3 bits [3:5]
127 comb
+= spec
.eq(sel(extra
, EXTRA3
.IDX1
))
128 with m
.Case(SVEXTRA
.Idx2
): # 3rd 3 bits [6:8]
129 comb
+= spec
.eq(sel(extra
, EXTRA3
.IDX2
))
130 # cannot fit more than 9 bits so there is no 4th thing
135 class SVP64RegExtra(SVP64ExtraSpec
):
136 """SVP64RegExtra - decodes SVP64 Extra fields to determine reg extension
138 incoming 5-bit GPR/FP is turned into a 7-bit and marked as scalar/vector
139 depending on info in one of the positions in the EXTRA field.
141 designed so that "no change" to the 5-bit register number occurs if
142 SV either does not apply or the relevant EXTRA2/3 field bits are zero.
144 see https://libre-soc.org/openpower/sv/svp64/
147 SVP64ExtraSpec
.__init
__(self
)
148 self
.reg_in
= Signal(5) # incoming reg number (5 bits, RA, RB)
149 self
.reg_out
= Signal(7) # extra-augmented output (7 bits)
150 self
.isvec
= Signal(1) # reg is marked as vector if true
152 def elaborate(self
, platform
):
153 m
= super().elaborate(platform
) # select required EXTRA2/3
156 # first get the spec. if not changed it's "scalar identity behaviour"
157 # which is zero which is ok.
160 # now decode it. bit 0 is "scalar/vector". note that spec could be zero
161 # from above, which (by design) has the effect of "no change", below.
163 # simple: isvec is top bit of spec
164 comb
+= self
.isvec
.eq(spec
[SPEC
.VEC
])
165 # extra bits for register number augmentation
166 spec_aug
= Signal(SPEC_AUG_SIZE
)
167 comb
+= spec_aug
.eq(field(spec
, SPECb
.MSB
, SPECb
.LSB
, SPEC_SIZE
))
169 # decode vector differently from scalar
170 with m
.If(self
.isvec
):
171 # Vector: shifted up, extra in LSBs (RA << 2) | spec[1:2]
172 comb
+= self
.reg_out
.eq(Cat(spec_aug
, self
.reg_in
))
174 # Scalar: not shifted up, extra in MSBs RA | (spec[1:2] << 5)
175 comb
+= self
.reg_out
.eq(Cat(self
.reg_in
, spec_aug
))
180 class SVP64CRExtra(SVP64ExtraSpec
):
181 """SVP64CRExtra - decodes SVP64 Extra fields to determine CR extension
183 incoming 3-bit CR is turned into a 7-bit and marked as scalar/vector
184 depending on info in one of the positions in the EXTRA field.
186 yes, really, 128 CRs. INT is 128, FP is 128, therefore CRs are 128.
188 designed so that "no change" to the 3-bit CR register number occurs if
189 SV either does not apply or the relevant EXTRA2/3 field bits are zero.
191 see https://libre-soc.org/openpower/sv/svp64/appendix
194 SVP64ExtraSpec
.__init
__(self
)
195 self
.cr_in
= Signal(3) # incoming CR number (3 bits, BA[0:2], BFA)
196 self
.cr_out
= Signal(7) # extra-augmented CR output (7 bits)
197 self
.isvec
= Signal(1) # reg is marked as vector if true
199 def elaborate(self
, platform
):
200 m
= super().elaborate(platform
) # select required EXTRA2/3
203 # first get the spec. if not changed it's "scalar identity behaviour"
204 # which is zero which is ok.
207 # now decode it. bit 0 is "scalar/vector". note that spec could be zero
208 # from above, which (by design) has the effect of "no change", below.
210 # simple: isvec is top bit of spec
211 comb
+= self
.isvec
.eq(spec
[SPEC
.VEC
])
212 # extra bits for register number augmentation
213 spec_aug
= Signal(SPEC_AUG_SIZE
)
214 comb
+= spec_aug
.eq(field(spec
, SPECb
.MSB
, SPECb
.LSB
, SPEC_SIZE
))
216 # decode vector differently from scalar, insert bits 1 and 2 accordingly
217 with m
.If(self
.isvec
):
218 # Vector: shifted up, extra in LSBs (CR << 4) | (spec[1:2] << 2)
219 comb
+= self
.cr_out
.eq(Cat(Const(0, 2), spec_aug
, self
.cr_in
))
221 # Scalar: not shifted up, extra in MSBs CR | (spec[1:2] << 3)
222 comb
+= self
.cr_out
.eq(Cat(self
.cr_in
, spec_aug
))
227 class DecodeA(Elaboratable
):
228 """DecodeA from instruction
230 decodes register RA, implicit and explicit CSRs
233 def __init__(self
, dec
):
235 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
236 self
.insn_in
= Signal(32, reset_less
=True)
237 self
.reg_out
= Data(5, name
="reg_a")
238 self
.spr_out
= Data(SPR
, "spr_a")
239 self
.fast_out
= Data(3, "fast_a")
241 def elaborate(self
, platform
):
246 m
.submodules
.sprmap
= sprmap
= SPRMap()
248 # select Register A field
249 ra
= Signal(5, reset_less
=True)
250 comb
+= ra
.eq(self
.dec
.RA
)
251 with m
.If((self
.sel_in
== In1Sel
.RA
) |
252 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
253 (ra
!= Const(0, 5)))):
254 comb
+= reg
.data
.eq(ra
)
257 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
258 # moved it to 1st position (in1_sel)... because
259 rs
= Signal(5, reset_less
=True)
260 comb
+= rs
.eq(self
.dec
.RS
)
261 with m
.If(self
.sel_in
== In1Sel
.RS
):
262 comb
+= reg
.data
.eq(rs
)
265 # decode Fast-SPR based on instruction type
266 with m
.Switch(op
.internal_op
):
268 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
269 with m
.Case(MicrOp
.OP_BC
):
270 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
272 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
273 comb
+= self
.fast_out
.ok
.eq(1)
274 with m
.Case(MicrOp
.OP_BCREG
):
275 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
276 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
277 with m
.If(xo9
& ~xo5
):
279 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
280 comb
+= self
.fast_out
.ok
.eq(1)
282 # MFSPR move from SPRs
283 with m
.Case(MicrOp
.OP_MFSPR
):
284 spr
= Signal(10, reset_less
=True)
285 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
286 comb
+= sprmap
.spr_i
.eq(spr
)
287 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
288 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
293 class DecodeAImm(Elaboratable
):
294 """DecodeA immediate from instruction
296 decodes register RA, whether immediate-zero, implicit and
300 def __init__(self
, dec
):
302 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
303 self
.immz_out
= Signal(reset_less
=True)
305 def elaborate(self
, platform
):
309 # zero immediate requested
310 ra
= Signal(5, reset_less
=True)
311 comb
+= ra
.eq(self
.dec
.RA
)
312 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) & (ra
== Const(0, 5))):
313 comb
+= self
.immz_out
.eq(1)
318 class DecodeB(Elaboratable
):
319 """DecodeB from instruction
321 decodes register RB, different forms of immediate (signed, unsigned),
322 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
323 by industry-standard convention, "lane 2" is where fully-decoded
324 immediates are muxed in.
327 def __init__(self
, dec
):
329 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
330 self
.insn_in
= Signal(32, reset_less
=True)
331 self
.reg_out
= Data(7, "reg_b")
332 self
.reg_isvec
= Signal(1, name
="reg_b_isvec") # TODO: in reg_out
333 self
.fast_out
= Data(3, "fast_b")
335 def elaborate(self
, platform
):
341 # select Register B field
342 with m
.Switch(self
.sel_in
):
343 with m
.Case(In2Sel
.RB
):
344 comb
+= reg
.data
.eq(self
.dec
.RB
)
346 with m
.Case(In2Sel
.RS
):
347 # for M-Form shiftrot
348 comb
+= reg
.data
.eq(self
.dec
.RS
)
351 # decode SPR2 based on instruction type
352 # BCREG implicitly uses LR or TAR for 2nd reg
353 # CTR however is already in fast_spr1 *not* 2.
354 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
355 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
356 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
358 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
)
359 comb
+= self
.fast_out
.ok
.eq(1)
361 comb
+= self
.fast_out
.data
.eq(FastRegs
.TAR
)
362 comb
+= self
.fast_out
.ok
.eq(1)
367 class DecodeBImm(Elaboratable
):
368 """DecodeB immediate from instruction
370 def __init__(self
, dec
):
372 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
373 self
.imm_out
= Data(64, "imm_b")
375 def elaborate(self
, platform
):
379 # select Register B Immediate
380 with m
.Switch(self
.sel_in
):
381 with m
.Case(In2Sel
.CONST_UI
): # unsigned
382 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
383 comb
+= self
.imm_out
.ok
.eq(1)
384 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
385 si
= Signal(16, reset_less
=True)
386 comb
+= si
.eq(self
.dec
.SI
)
387 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
388 comb
+= self
.imm_out
.ok
.eq(1)
389 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
390 si_hi
= Signal(32, reset_less
=True)
391 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
392 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
393 comb
+= self
.imm_out
.ok
.eq(1)
394 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
395 ui
= Signal(16, reset_less
=True)
396 comb
+= ui
.eq(self
.dec
.UI
)
397 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
398 comb
+= self
.imm_out
.ok
.eq(1)
399 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
400 li
= Signal(26, reset_less
=True)
401 comb
+= li
.eq(self
.dec
.LI
<< 2)
402 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
403 comb
+= self
.imm_out
.ok
.eq(1)
404 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
405 bd
= Signal(16, reset_less
=True)
406 comb
+= bd
.eq(self
.dec
.BD
<< 2)
407 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
408 comb
+= self
.imm_out
.ok
.eq(1)
409 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
410 ds
= Signal(16, reset_less
=True)
411 comb
+= ds
.eq(self
.dec
.DS
<< 2)
412 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
413 comb
+= self
.imm_out
.ok
.eq(1)
414 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
415 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
416 comb
+= self
.imm_out
.ok
.eq(1)
417 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
418 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
419 comb
+= self
.imm_out
.ok
.eq(1)
420 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
421 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
422 comb
+= self
.imm_out
.ok
.eq(1)
427 class DecodeC(Elaboratable
):
428 """DecodeC from instruction
430 decodes register RC. this is "lane 3" into some CompUnits (not many)
433 def __init__(self
, dec
):
435 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
436 self
.insn_in
= Signal(32, reset_less
=True)
437 self
.reg_out
= Data(5, "reg_c")
439 def elaborate(self
, platform
):
445 # select Register C field
446 with m
.Switch(self
.sel_in
):
447 with m
.Case(In3Sel
.RB
):
448 # for M-Form shiftrot
449 comb
+= reg
.data
.eq(self
.dec
.RB
)
451 with m
.Case(In3Sel
.RS
):
452 comb
+= reg
.data
.eq(self
.dec
.RS
)
458 class DecodeOut(Elaboratable
):
459 """DecodeOut from instruction
461 decodes output register RA, RT or SPR
464 def __init__(self
, dec
):
466 self
.sel_in
= Signal(OutSel
, reset_less
=True)
467 self
.insn_in
= Signal(32, reset_less
=True)
468 self
.reg_out
= Data(5, "reg_o")
469 self
.spr_out
= Data(SPR
, "spr_o")
470 self
.fast_out
= Data(3, "fast_o")
472 def elaborate(self
, platform
):
475 m
.submodules
.sprmap
= sprmap
= SPRMap()
479 # select Register out field
480 with m
.Switch(self
.sel_in
):
481 with m
.Case(OutSel
.RT
):
482 comb
+= reg
.data
.eq(self
.dec
.RT
)
484 with m
.Case(OutSel
.RA
):
485 comb
+= reg
.data
.eq(self
.dec
.RA
)
487 with m
.Case(OutSel
.SPR
):
488 spr
= Signal(10, reset_less
=True)
489 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
490 # MFSPR move to SPRs - needs mapping
491 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
492 comb
+= sprmap
.spr_i
.eq(spr
)
493 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
494 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
497 with m
.Switch(op
.internal_op
):
499 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
500 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
501 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
503 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
504 comb
+= self
.fast_out
.ok
.eq(1)
506 # RFID 1st spr (fast)
507 with m
.Case(MicrOp
.OP_RFID
):
508 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
509 comb
+= self
.fast_out
.ok
.eq(1)
514 class DecodeOut2(Elaboratable
):
515 """DecodeOut2 from instruction
517 decodes output registers (2nd one). note that RA is *implicit* below,
518 which now causes problems with SVP64
520 TODO: SVP64 is a little more complex, here. svp64 allows extending
521 by one more destination by having one more EXTRA field. RA-as-src
522 is not the same as RA-as-dest. limited in that it's the same first
523 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
524 for operations that have src-as-dest: mostly this is LD/ST-with-update
525 but there are others.
528 def __init__(self
, dec
):
530 self
.sel_in
= Signal(OutSel
, reset_less
=True)
531 self
.lk
= Signal(reset_less
=True)
532 self
.insn_in
= Signal(32, reset_less
=True)
533 self
.reg_out
= Data(5, "reg_o2")
534 self
.fast_out
= Data(3, "fast_o2")
536 def elaborate(self
, platform
):
540 #m.submodules.svdec = svdec = SVP64RegExtra()
542 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
543 #reg = Signal(5, reset_less=True)
545 if hasattr(self
.dec
.op
, "upd"):
546 # update mode LD/ST uses read-reg A also as an output
547 with m
.If(self
.dec
.op
.upd
== LDSTMode
.update
):
548 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
549 comb
+= self
.reg_out
.ok
.eq(1)
551 # B, BC or BCREG: potential implicit register (LR) output
552 # these give bl, bcl, bclrl, etc.
553 with m
.Switch(op
.internal_op
):
555 # BC* implicit register (LR)
556 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
557 with m
.If(self
.lk
): # "link" mode
558 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
) # constant: LR
559 comb
+= self
.fast_out
.ok
.eq(1)
561 # RFID 2nd spr (fast)
562 with m
.Case(MicrOp
.OP_RFID
):
563 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
564 comb
+= self
.fast_out
.ok
.eq(1)
569 class DecodeRC(Elaboratable
):
570 """DecodeRc from instruction
572 decodes Record bit Rc
575 def __init__(self
, dec
):
577 self
.sel_in
= Signal(RC
, reset_less
=True)
578 self
.insn_in
= Signal(32, reset_less
=True)
579 self
.rc_out
= Data(1, "rc")
581 def elaborate(self
, platform
):
585 # select Record bit out field
586 with m
.Switch(self
.sel_in
):
588 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
589 comb
+= self
.rc_out
.ok
.eq(1)
591 comb
+= self
.rc_out
.data
.eq(1)
592 comb
+= self
.rc_out
.ok
.eq(1)
593 with m
.Case(RC
.NONE
):
594 comb
+= self
.rc_out
.data
.eq(0)
595 comb
+= self
.rc_out
.ok
.eq(1)
600 class DecodeOE(Elaboratable
):
601 """DecodeOE from instruction
603 decodes OE field: uses RC decode detection which might not be good
605 -- For now, use "rc" in the decode table to decide whether oe exists.
606 -- This is not entirely correct architecturally: For mulhd and
607 -- mulhdu, the OE field is reserved. It remains to be seen what an
608 -- actual POWER9 does if we set it on those instructions, for now we
609 -- test that further down when assigning to the multiplier oe input.
612 def __init__(self
, dec
):
614 self
.sel_in
= Signal(RC
, reset_less
=True)
615 self
.insn_in
= Signal(32, reset_less
=True)
616 self
.oe_out
= Data(1, "oe")
618 def elaborate(self
, platform
):
623 with m
.Switch(op
.internal_op
):
625 # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
627 # XXX ARGH! ignoring OE causes incompatibility with microwatt
628 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
629 with m
.Case(MicrOp
.OP_MUL_H64
, MicrOp
.OP_MUL_H32
,
630 MicrOp
.OP_EXTS
, MicrOp
.OP_CNTZ
,
631 MicrOp
.OP_SHL
, MicrOp
.OP_SHR
, MicrOp
.OP_RLC
,
632 MicrOp
.OP_LOAD
, MicrOp
.OP_STORE
,
633 MicrOp
.OP_RLCL
, MicrOp
.OP_RLCR
,
637 # all other ops decode OE field
639 # select OE bit out field
640 with m
.Switch(self
.sel_in
):
642 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
643 comb
+= self
.oe_out
.ok
.eq(1)
648 class DecodeCRIn(Elaboratable
):
649 """Decodes input CR from instruction
651 CR indices - insn fields - (not the data *in* the CR) require only 3
652 bits because they refer to CR0-CR7
655 def __init__(self
, dec
):
657 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
658 self
.insn_in
= Signal(32, reset_less
=True)
659 self
.cr_bitfield
= Data(3, "cr_bitfield")
660 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
661 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
662 self
.whole_reg
= Data(8, "cr_fxm")
664 def elaborate(self
, platform
):
668 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
671 # zero-initialisation
672 comb
+= self
.cr_bitfield
.ok
.eq(0)
673 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
674 comb
+= self
.cr_bitfield_o
.ok
.eq(0)
675 comb
+= self
.whole_reg
.ok
.eq(0)
677 # select the relevant CR bitfields
678 with m
.Switch(self
.sel_in
):
679 with m
.Case(CRInSel
.NONE
):
680 pass # No bitfield activated
681 with m
.Case(CRInSel
.CR0
):
682 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
683 comb
+= self
.cr_bitfield
.ok
.eq(1)
684 with m
.Case(CRInSel
.BI
):
685 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
686 comb
+= self
.cr_bitfield
.ok
.eq(1)
687 with m
.Case(CRInSel
.BFA
):
688 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
689 comb
+= self
.cr_bitfield
.ok
.eq(1)
690 with m
.Case(CRInSel
.BA_BB
):
691 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
692 comb
+= self
.cr_bitfield
.ok
.eq(1)
693 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
694 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
695 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
696 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
697 with m
.Case(CRInSel
.BC
):
698 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
699 comb
+= self
.cr_bitfield
.ok
.eq(1)
700 with m
.Case(CRInSel
.WHOLE_REG
):
701 comb
+= self
.whole_reg
.ok
.eq(1)
702 move_one
= Signal(reset_less
=True)
703 comb
+= move_one
.eq(self
.insn_in
[20]) # MSB0 bit 11
704 with m
.If((op
.internal_op
== MicrOp
.OP_MFCR
) & move_one
):
705 # must one-hot the FXM field
706 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
707 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
709 # otherwise use all of it
710 comb
+= self
.whole_reg
.data
.eq(0xff)
715 class DecodeCROut(Elaboratable
):
716 """Decodes input CR from instruction
718 CR indices - insn fields - (not the data *in* the CR) require only 3
719 bits because they refer to CR0-CR7
722 def __init__(self
, dec
):
724 self
.rc_in
= Signal(reset_less
=True)
725 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
726 self
.insn_in
= Signal(32, reset_less
=True)
727 self
.cr_bitfield
= Data(3, "cr_bitfield")
728 self
.whole_reg
= Data(8, "cr_fxm")
730 def elaborate(self
, platform
):
734 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
737 comb
+= self
.cr_bitfield
.ok
.eq(0)
738 comb
+= self
.whole_reg
.ok
.eq(0)
740 with m
.Switch(self
.sel_in
):
741 with m
.Case(CROutSel
.NONE
):
742 pass # No bitfield activated
743 with m
.Case(CROutSel
.CR0
):
744 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
745 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
746 with m
.Case(CROutSel
.BF
):
747 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
748 comb
+= self
.cr_bitfield
.ok
.eq(1)
749 with m
.Case(CROutSel
.BT
):
750 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
751 comb
+= self
.cr_bitfield
.ok
.eq(1)
752 with m
.Case(CROutSel
.WHOLE_REG
):
753 comb
+= self
.whole_reg
.ok
.eq(1)
754 move_one
= Signal(reset_less
=True)
755 comb
+= move_one
.eq(self
.insn_in
[20])
756 with m
.If((op
.internal_op
== MicrOp
.OP_MTCRF
)):
758 # must one-hot the FXM field
759 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
760 with m
.If(ppick
.en_o
):
761 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
763 comb
+= self
.whole_reg
.data
.eq(0b00000001) # CR7
765 comb
+= self
.whole_reg
.data
.eq(self
.dec
.FXM
)
767 # otherwise use all of it
768 comb
+= self
.whole_reg
.data
.eq(0xff)
772 # dictionary of Input Record field names that, if they exist,
773 # will need a corresponding CSV Decoder file column (actually, PowerOp)
774 # to be decoded (this includes the single bit names)
775 record_names
= {'insn_type': 'internal_op',
776 'fn_unit': 'function_unit',
780 'imm_data': 'in2_sel',
781 'invert_in': 'inv_a',
782 'invert_out': 'inv_out',
785 'output_carry': 'cry_out',
786 'input_carry': 'cry_in',
787 'is_32bit': 'is_32b',
790 'data_len': 'ldst_len',
791 'byte_reverse': 'br',
792 'sign_extend': 'sgn_ext',
797 class PowerDecodeSubset(Elaboratable
):
798 """PowerDecodeSubset: dynamic subset decoder
800 only fields actually requested are copied over. hence, "subset" (duh).
802 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None):
804 self
.sv_rm
= SVP64Rec(name
="dec_svp64") # SVP64 RM field
807 self
.fn_name
= fn_name
809 opkls
= Decode2ToOperand
810 self
.do
= opkls(fn_name
)
811 col_subset
= self
.get_col_subset(self
.do
)
813 # only needed for "main" PowerDecode2
815 self
.e
= Decode2ToExecute1Type(name
=self
.fn_name
, do
=self
.do
)
817 # create decoder if one not already given
819 dec
= create_pdecode(name
=fn_name
, col_subset
=col_subset
,
820 row_subset
=self
.rowsubsetfn
)
823 # state information needed by the Decoder
825 state
= CoreState("dec2")
828 def get_col_subset(self
, do
):
829 subset
= { 'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
830 for k
, v
in record_names
.items():
833 print ("get_col_subset", self
.fn_name
, do
.fields
, subset
)
836 def rowsubsetfn(self
, opcode
, row
):
837 return row
['unit'] == self
.fn_name
840 return self
.dec
.ports() + self
.e
.ports() + self
.sv_rm
.ports()
842 def needs_field(self
, field
, op_field
):
847 return hasattr(do
, field
) and self
.op_get(op_field
) is not None
849 def do_copy(self
, field
, val
, final
=False):
850 if final
or self
.final
:
854 if hasattr(do
, field
) and val
is not None:
855 return getattr(do
, field
).eq(val
)
858 def op_get(self
, op_field
):
859 return getattr(self
.dec
.op
, op_field
, None)
861 def elaborate(self
, platform
):
865 op
, do
= self
.dec
.op
, self
.do
866 msr
, cia
= state
.msr
, state
.pc
868 # fill in for a normal instruction (not an exception)
869 # copy over if non-exception, non-privileged etc. is detected
871 if self
.fn_name
is None:
874 name
= self
.fn_name
+ "tmp"
875 self
.e_tmp
= Decode2ToExecute1Type(name
=name
, opkls
=self
.opkls
)
877 # set up submodule decoders
878 m
.submodules
.dec
= self
.dec
879 m
.submodules
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
880 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
)
881 m
.submodules
.dec_cr_in
= self
.dec_cr_in
= DecodeCRIn(self
.dec
)
882 m
.submodules
.dec_cr_out
= self
.dec_cr_out
= DecodeCROut(self
.dec
)
884 # copy instruction through...
886 dec_rc
.insn_in
, dec_oe
.insn_in
,
887 self
.dec_cr_in
.insn_in
, self
.dec_cr_out
.insn_in
]:
888 comb
+= i
.eq(self
.dec
.opcode_in
)
890 # ...and subdecoders' input fields
891 comb
+= dec_rc
.sel_in
.eq(op
.rc_sel
)
892 comb
+= dec_oe
.sel_in
.eq(op
.rc_sel
) # XXX should be OE sel
893 comb
+= self
.dec_cr_in
.sel_in
.eq(op
.cr_in
)
894 comb
+= self
.dec_cr_out
.sel_in
.eq(op
.cr_out
)
895 comb
+= self
.dec_cr_out
.rc_in
.eq(dec_rc
.rc_out
.data
)
898 comb
+= self
.do_copy("msr", msr
)
899 comb
+= self
.do_copy("cia", cia
)
901 # set up instruction type
902 # no op: defaults to OP_ILLEGAL
903 if self
.fn_name
=="MMU":
904 # mmu is special case: needs SPR opcode as well
905 mmu0
= self
.mmu0_spr_dec
906 with m
.If(((mmu0
.dec
.op
.internal_op
== MicrOp
.OP_MTSPR
) |
907 (mmu0
.dec
.op
.internal_op
== MicrOp
.OP_MFSPR
))):
908 comb
+= self
.do_copy("insn_type", mmu0
.op_get("internal_op"))
910 comb
+= self
.do_copy("insn_type", self
.op_get("internal_op"))
912 comb
+= self
.do_copy("insn_type", self
.op_get("internal_op"))
914 # function unit for decoded instruction: requires minor redirect
916 fn
= self
.op_get("function_unit")
917 spr
= Signal(10, reset_less
=True)
918 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
920 SPR_PID
= 48 # TODO read docs for POWER9
921 # Microwatt doesn't implement the partition table
922 # instead has PRTBL register (SPR) to point to process table
923 SPR_PRTBL
= 720 # see common.vhdl in microwatt, not in POWER9
924 with m
.If(((self
.dec
.op
.internal_op
== MicrOp
.OP_MTSPR
) |
925 (self
.dec
.op
.internal_op
== MicrOp
.OP_MFSPR
)) &
926 ((spr
== SPR
.DSISR
) |
(spr
== SPR
.DAR
)
927 |
(spr
==SPR_PRTBL
) |
(spr
==SPR_PID
))):
928 comb
+= self
.do_copy("fn_unit", Function
.MMU
)
930 comb
+= self
.do_copy("fn_unit",fn
)
933 if self
.needs_field("zero_a", "in1_sel"):
934 m
.submodules
.dec_ai
= dec_ai
= DecodeAImm(self
.dec
)
935 comb
+= dec_ai
.sel_in
.eq(op
.in1_sel
)
936 comb
+= self
.do_copy("zero_a", dec_ai
.immz_out
) # RA==0 detected
937 if self
.needs_field("imm_data", "in2_sel"):
938 m
.submodules
.dec_bi
= dec_bi
= DecodeBImm(self
.dec
)
939 comb
+= dec_bi
.sel_in
.eq(op
.in2_sel
)
940 comb
+= self
.do_copy("imm_data", dec_bi
.imm_out
) # imm in RB
943 comb
+= self
.do_copy("rc", dec_rc
.rc_out
)
944 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
947 comb
+= self
.do_copy("read_cr_whole", self
.dec_cr_in
.whole_reg
)
948 comb
+= self
.do_copy("write_cr_whole", self
.dec_cr_out
.whole_reg
)
949 comb
+= self
.do_copy("write_cr0", self
.dec_cr_out
.cr_bitfield
.ok
)
951 comb
+= self
.do_copy("input_cr", self
.op_get("cr_in")) # CR in
952 comb
+= self
.do_copy("output_cr", self
.op_get("cr_out")) # CR out
954 # decoded/selected instruction flags
955 comb
+= self
.do_copy("data_len", self
.op_get("ldst_len"))
956 comb
+= self
.do_copy("invert_in", self
.op_get("inv_a"))
957 comb
+= self
.do_copy("invert_out", self
.op_get("inv_out"))
958 comb
+= self
.do_copy("input_carry", self
.op_get("cry_in"))
959 comb
+= self
.do_copy("output_carry", self
.op_get("cry_out"))
960 comb
+= self
.do_copy("is_32bit", self
.op_get("is_32b"))
961 comb
+= self
.do_copy("is_signed", self
.op_get("sgn"))
962 lk
= self
.op_get("lk")
965 comb
+= self
.do_copy("lk", self
.dec
.LK
) # XXX TODO: accessor
967 comb
+= self
.do_copy("byte_reverse", self
.op_get("br"))
968 comb
+= self
.do_copy("sign_extend", self
.op_get("sgn_ext"))
969 comb
+= self
.do_copy("ldst_mode", self
.op_get("upd")) # LD/ST mode
974 class PowerDecode2(PowerDecodeSubset
):
975 """PowerDecode2: the main instruction decoder.
977 whilst PowerDecode is responsible for decoding the actual opcode, this
978 module encapsulates further specialist, sparse information and
979 expansion of fields that is inconvenient to have in the CSV files.
980 for example: the encoding of the immediates, which are detected
981 and expanded out to their full value from an annotated (enum)
984 implicit register usage is also set up, here. for example: OP_BC
985 requires implicitly reading CTR, OP_RFID requires implicitly writing
988 in addition, PowerDecoder2 is responsible for detecting whether
989 instructions are illegal (or privileged) or not, and instead of
990 just leaving at that, *replacing* the instruction to execute with
991 a suitable alternative (trap).
993 LDSTExceptions are done the cycle _after_ they're detected (after
994 they come out of LDSTCompUnit). basically despite the instruction
995 being decoded, the results of the decode are completely ignored
996 and "exception.happened" used to set the "actual" instruction to
997 "OP_TRAP". the LDSTException data structure gets filled in,
998 in the CompTrapOpSubset and that's what it fills in SRR.
1000 to make this work, TestIssuer must notice "exception.happened"
1001 after the (failed) LD/ST and copies the LDSTException info from
1002 the output, into here (PowerDecoder2). without incrementing PC.
1005 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None):
1006 super().__init
__(dec
, opkls
, fn_name
, final
, state
)
1007 self
.exc
= LDSTException("dec2_exc")
1009 self
.cr_out_isvec
= Signal(1, name
="cr_out_isvec")
1010 self
.cr_in_isvec
= Signal(1, name
="cr_in_isvec")
1011 self
.cr_in_b_isvec
= Signal(1, name
="cr_in_b_isvec")
1012 self
.cr_in_o_isvec
= Signal(1, name
="cr_in_o_isvec")
1013 self
.in1_isvec
= Signal(1, name
="reg_a_isvec")
1014 self
.in2_isvec
= Signal(1, name
="reg_b_isvec")
1015 self
.in3_isvec
= Signal(1, name
="reg_c_isvec")
1016 self
.o_isvec
= Signal(1, name
="reg_o_isvec")
1017 self
.o2_isvec
= Signal(1, name
="reg_o2_isvec")
1018 self
.no_out_vec
= Signal(1, name
="no_out_vec") # no outputs are vectors
1020 def get_col_subset(self
, opkls
):
1021 subset
= super().get_col_subset(opkls
)
1022 subset
.add("asmcode")
1023 subset
.add("in1_sel")
1024 subset
.add("in2_sel")
1025 subset
.add("in3_sel")
1026 subset
.add("out_sel")
1027 subset
.add("sv_in1")
1028 subset
.add("sv_in2")
1029 subset
.add("sv_in3")
1030 subset
.add("sv_out")
1031 subset
.add("sv_cr_in")
1032 subset
.add("sv_cr_out")
1033 subset
.add("SV_Etype")
1034 subset
.add("SV_Ptype")
1036 subset
.add("internal_op")
1040 def elaborate(self
, platform
):
1041 m
= super().elaborate(platform
)
1044 e_out
, op
, do_out
= self
.e
, self
.dec
.op
, self
.e
.do
1045 dec_spr
, msr
, cia
, ext_irq
= state
.dec
, state
.msr
, state
.pc
, state
.eint
1049 # fill in for a normal instruction (not an exception)
1050 # copy over if non-exception, non-privileged etc. is detected
1052 # set up submodule decoders
1053 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
)
1054 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
)
1055 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
)
1056 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
)
1057 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
)
1059 # and SVP64 Extra decoders
1060 m
.submodules
.crout_svdec
= crout_svdec
= SVP64CRExtra()
1061 m
.submodules
.crin_svdec
= crin_svdec
= SVP64CRExtra()
1062 m
.submodules
.crin_svdec_b
= crin_svdec_b
= SVP64CRExtra()
1063 m
.submodules
.crin_svdec_o
= crin_svdec_o
= SVP64CRExtra()
1064 m
.submodules
.in1_svdec
= in1_svdec
= SVP64RegExtra()
1065 m
.submodules
.in2_svdec
= in2_svdec
= SVP64RegExtra()
1066 m
.submodules
.in3_svdec
= in3_svdec
= SVP64RegExtra()
1067 m
.submodules
.o_svdec
= o_svdec
= SVP64RegExtra()
1068 m
.submodules
.o2_svdec
= o2_svdec
= SVP64RegExtra()
1070 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
1071 reg
= Signal(5, reset_less
=True)
1073 # copy instruction through...
1074 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
1075 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1076 comb
+= i
.eq(self
.dec
.opcode_in
)
1078 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
1079 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1080 # which in turn were auto-generated by sv_analysis.py
1081 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
1085 comb
+= crout_svdec
.idx
.eq(op
.sv_cr_out
) # SVP64 CR out
1086 comb
+= self
.cr_out_isvec
.eq(crout_svdec
.isvec
)
1089 # CR in - index selection slightly different due to shared CR field sigh
1090 cr_a_idx
= Signal(SVEXTRA
)
1091 cr_b_idx
= Signal(SVEXTRA
)
1093 # these change slightly, when decoding BA/BB. really should have
1094 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1095 comb
+= cr_a_idx
.eq(op
.sv_cr_in
)
1096 comb
+= cr_b_idx
.eq(SVEXTRA
.NONE
)
1097 with m
.If(op
.sv_cr_in
== SVEXTRA
.Idx_1_2
.value
):
1098 comb
+= cr_a_idx
.eq(SVEXTRA
.Idx1
)
1099 comb
+= cr_b_idx
.eq(SVEXTRA
.Idx2
)
1101 comb
+= self
.cr_in_isvec
.eq(crin_svdec
.isvec
)
1102 comb
+= self
.cr_in_b_isvec
.eq(crin_svdec_b
.isvec
)
1103 comb
+= self
.cr_in_o_isvec
.eq(crin_svdec_o
.isvec
)
1105 # indices are slightly different, BA/BB mess sorted above
1106 comb
+= crin_svdec
.idx
.eq(cr_a_idx
) # SVP64 CR in A
1107 comb
+= crin_svdec_b
.idx
.eq(cr_b_idx
) # SVP64 CR in B
1108 comb
+= crin_svdec_o
.idx
.eq(op
.sv_cr_out
) # SVP64 CR out
1110 # ...and subdecoders' input fields
1111 comb
+= dec_a
.sel_in
.eq(op
.in1_sel
)
1112 comb
+= dec_b
.sel_in
.eq(op
.in2_sel
)
1113 comb
+= dec_c
.sel_in
.eq(op
.in3_sel
)
1114 comb
+= dec_o
.sel_in
.eq(op
.out_sel
)
1115 comb
+= dec_o2
.sel_in
.eq(op
.out_sel
)
1116 if hasattr(do
, "lk"):
1117 comb
+= dec_o2
.lk
.eq(do
.lk
)
1119 # get SVSTATE srcstep (TODO: elwidth, dststep etc.) needed below
1120 srcstep
= Signal
.like(self
.state
.svstate
.srcstep
)
1121 comb
+= srcstep
.eq(self
.state
.svstate
.srcstep
)
1123 # registers a, b, c and out and out2 (LD/ST EA)
1124 for to_reg
, fromreg
, svdec
in (
1125 (e
.read_reg1
, dec_a
.reg_out
, in1_svdec
),
1126 (e
.read_reg2
, dec_b
.reg_out
, in2_svdec
),
1127 (e
.read_reg3
, dec_c
.reg_out
, in3_svdec
),
1128 (e
.write_reg
, dec_o
.reg_out
, o_svdec
),
1129 (e
.write_ea
, dec_o2
.reg_out
, o2_svdec
)):
1130 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1131 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
1132 comb
+= svdec
.reg_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1133 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1134 # detect if Vectorised: add srcstep if yes. TODO: a LOT.
1135 # this trick only holds when elwidth=default and in single-pred
1136 with m
.If(svdec
.isvec
):
1137 comb
+= to_reg
.data
.eq(srcstep
+svdec
.reg_out
) # 7-bit output
1139 comb
+= to_reg
.data
.eq(svdec
.reg_out
) # 7-bit output
1141 comb
+= in1_svdec
.idx
.eq(op
.sv_in1
) # SVP64 reg #1 (matches in1_sel)
1142 comb
+= in2_svdec
.idx
.eq(op
.sv_in2
) # SVP64 reg #2 (matches in2_sel)
1143 comb
+= in3_svdec
.idx
.eq(op
.sv_in3
) # SVP64 reg #3 (matches in3_sel)
1144 comb
+= o_svdec
.idx
.eq(op
.sv_out
) # SVP64 output (matches out_sel)
1145 # XXX TODO - work out where this should come from. the problem is
1146 # that LD-with-update is implied (computed from "is instruction in
1147 # "update mode" rather than specified cleanly as its own CSV column
1148 #comb += o2_svdec.idx.eq(op.sv_out) # SVP64 output (implicit)
1150 # output reg-is-vectorised (and when no output is vectorised)
1151 comb
+= self
.in1_isvec
.eq(in1_svdec
.isvec
)
1152 comb
+= self
.in2_isvec
.eq(in2_svdec
.isvec
)
1153 comb
+= self
.in3_isvec
.eq(in3_svdec
.isvec
)
1154 comb
+= self
.o_isvec
.eq(o_svdec
.isvec
)
1155 comb
+= self
.o2_isvec
.eq(o2_svdec
.isvec
)
1156 # TODO: include SPRs and CRs here! must be True when *all* are scalar
1157 comb
+= self
.no_out_vec
.eq((~o2_svdec
.isvec
) & (~o_svdec
.isvec
))
1160 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
1161 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
1164 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
1165 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
1166 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
)
1167 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
)
1169 # condition registers (CR)
1170 for to_reg
, fromreg
, svdec
in (
1171 (e
.read_cr1
, self
.dec_cr_in
.cr_bitfield
, crin_svdec
),
1172 (e
.read_cr2
, self
.dec_cr_in
.cr_bitfield_b
, crin_svdec_b
),
1173 (e
.read_cr3
, self
.dec_cr_in
.cr_bitfield_o
, crin_svdec_o
),
1174 (e
.write_cr
, self
.dec_cr_out
.cr_bitfield
, crout_svdec
)):
1175 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1176 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
1177 comb
+= svdec
.cr_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1178 with m
.If(svdec
.isvec
):
1179 comb
+= to_reg
.data
.eq(srcstep
+svdec
.cr_out
) # 7-bit output
1181 comb
+= to_reg
.data
.eq(svdec
.cr_out
) # 7-bit output
1182 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1184 # sigh this is exactly the sort of thing for which the
1185 # decoder is designed to not need. MTSPR, MFSPR and others need
1186 # access to the XER bits. however setting e.oe is not appropriate
1187 with m
.If(op
.internal_op
== MicrOp
.OP_MFSPR
):
1188 comb
+= e
.xer_in
.eq(0b111) # SO, CA, OV
1189 with m
.If(op
.internal_op
== MicrOp
.OP_CMP
):
1190 comb
+= e
.xer_in
.eq(1<<XERRegs
.SO
) # SO
1191 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
1192 comb
+= e
.xer_out
.eq(1)
1194 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1195 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
1196 # *DO NOT* call self.trap here. that would reset absolutely
1197 # everything including destroying read of RA and RB.
1198 comb
+= self
.do_copy("trapaddr", 0x70) # strip first nibble
1200 ####################
1201 # ok so the instruction's been decoded, blah blah, however
1202 # now we need to determine if it's actually going to go ahead...
1203 # *or* if in fact it's a privileged operation, whether there's
1204 # an external interrupt, etc. etc. this is a simple priority
1205 # if-elif-elif sequence. decrement takes highest priority,
1206 # EINT next highest, privileged operation third.
1208 # check if instruction is privileged
1209 is_priv_insn
= instr_is_priv(m
, op
.internal_op
, e
.do
.insn
)
1211 # different IRQ conditions
1212 ext_irq_ok
= Signal()
1213 dec_irq_ok
= Signal()
1218 comb
+= ext_irq_ok
.eq(ext_irq
& msr
[MSR
.EE
]) # v3.0B p944 (MSR.EE)
1219 comb
+= dec_irq_ok
.eq(dec_spr
[63] & msr
[MSR
.EE
]) # 6.5.11 p1076
1220 comb
+= priv_ok
.eq(is_priv_insn
& msr
[MSR
.PR
])
1221 comb
+= illeg_ok
.eq(op
.internal_op
== MicrOp
.OP_ILLEGAL
)
1223 # LD/ST exceptions. TestIssuer copies the exception info at us
1224 # after a failed LD/ST.
1225 with m
.If(exc
.happened
):
1226 with m
.If(exc
.alignment
):
1227 self
.trap(m
, TT
.PRIV
, 0x600)
1228 with m
.Elif(exc
.instr_fault
):
1229 with m
.If(exc
.segment_fault
):
1230 self
.trap(m
, TT
.PRIV
, 0x480)
1232 # pass exception info to trap to create SRR1
1233 self
.trap(m
, TT
.MEMEXC
, 0x400, exc
)
1235 with m
.If(exc
.segment_fault
):
1236 self
.trap(m
, TT
.PRIV
, 0x380)
1238 self
.trap(m
, TT
.PRIV
, 0x300)
1240 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1241 with m
.Elif(dec_irq_ok
):
1242 self
.trap(m
, TT
.DEC
, 0x900) # v3.0B 6.5 p1065
1244 # external interrupt? only if MSR.EE set
1245 with m
.Elif(ext_irq_ok
):
1246 self
.trap(m
, TT
.EINT
, 0x500)
1248 # privileged instruction trap
1249 with m
.Elif(priv_ok
):
1250 self
.trap(m
, TT
.PRIV
, 0x700)
1252 # illegal instruction must redirect to trap. this is done by
1253 # *overwriting* the decoded instruction and starting again.
1254 # (note: the same goes for interrupts and for privileged operations,
1255 # just with different trapaddr and traptype)
1256 with m
.Elif(illeg_ok
):
1257 # illegal instruction trap
1258 self
.trap(m
, TT
.ILLEG
, 0x700)
1260 # no exception, just copy things to the output
1264 ####################
1265 # follow-up after trap/irq to set up SRR0/1
1267 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1268 # Note: OP_SC could actually be modified to just be a trap
1269 with m
.If((do_out
.insn_type
== MicrOp
.OP_TRAP
) |
1270 (do_out
.insn_type
== MicrOp
.OP_SC
)):
1271 # TRAP write fast1 = SRR0
1272 comb
+= e_out
.write_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
1273 comb
+= e_out
.write_fast1
.ok
.eq(1)
1274 # TRAP write fast2 = SRR1
1275 comb
+= e_out
.write_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
1276 comb
+= e_out
.write_fast2
.ok
.eq(1)
1278 # RFID: needs to read SRR0/1
1279 with m
.If(do_out
.insn_type
== MicrOp
.OP_RFID
):
1280 # TRAP read fast1 = SRR0
1281 comb
+= e_out
.read_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
1282 comb
+= e_out
.read_fast1
.ok
.eq(1)
1283 # TRAP read fast2 = SRR1
1284 comb
+= e_out
.read_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
1285 comb
+= e_out
.read_fast2
.ok
.eq(1)
1287 # annoying simulator bug
1288 if hasattr(e_out
, "asmcode") and hasattr(self
.dec
.op
, "asmcode"):
1289 comb
+= e_out
.asmcode
.eq(self
.dec
.op
.asmcode
)
1293 def trap(self
, m
, traptype
, trapaddr
, exc
=None):
1294 """trap: this basically "rewrites" the decoded instruction as a trap
1297 op
, e
= self
.dec
.op
, self
.e
1298 comb
+= e
.eq(0) # reset eeeeeverything
1301 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1302 comb
+= self
.do_copy("insn_type", MicrOp
.OP_TRAP
, True)
1303 comb
+= self
.do_copy("fn_unit", Function
.TRAP
, True)
1304 comb
+= self
.do_copy("trapaddr", trapaddr
>> 4, True) # bottom 4 bits
1305 comb
+= self
.do_copy("traptype", traptype
, True) # request type
1306 comb
+= self
.do_copy("ldst_exc", exc
, True) # request type
1307 comb
+= self
.do_copy("msr", self
.state
.msr
, True) # copy of MSR "state"
1308 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # copy of PC "state"
1311 # SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
1312 # identifies if an instruction is a SVP64-encoded prefix, and extracts
1313 # the 24-bit SVP64 context (RM) if it is
1314 class SVP64PrefixDecoder(Elaboratable
):
1317 self
.opcode_in
= Signal(32, reset_less
=True)
1318 self
.raw_opcode_in
= Signal
.like(self
.opcode_in
, reset_less
=True)
1319 self
.is_svp64_mode
= Signal(1, reset_less
=True)
1320 self
.svp64_rm
= Signal(24, reset_less
=True)
1321 self
.bigendian
= Signal(reset_less
=True)
1323 def elaborate(self
, platform
):
1325 opcode_in
= self
.opcode_in
1327 # sigh copied this from TopPowerDecoder
1328 # raw opcode in assumed to be in LE order: byte-reverse it to get BE
1329 raw_le
= self
.raw_opcode_in
1331 for i
in range(0, 32, 8):
1332 l
.append(raw_le
[i
:i
+8])
1335 comb
+= opcode_in
.eq(Mux(self
.bigendian
, raw_be
, raw_le
))
1337 # start identifying if the incoming opcode is SVP64 prefix)
1338 major
= Signal(6, reset_less
=True)
1339 ident
= Signal(2, reset_less
=True)
1341 comb
+= major
.eq(sel(opcode_in
, SVP64P
.OPC
))
1342 comb
+= ident
.eq(sel(opcode_in
, SVP64P
.SVP64_7_9
))
1344 comb
+= self
.is_svp64_mode
.eq(
1345 (major
== Const(1, 6)) & # EXT01
1346 (ident
== Const(0b11, 2)) # identifier bits
1349 with m
.If(self
.is_svp64_mode
):
1350 # now grab the 24-bit ReMap context bits,
1351 comb
+= self
.svp64_rm
.eq(sel(opcode_in
, SVP64P
.RM
))
1356 return [self
.opcode_in
, self
.raw_opcode_in
, self
.is_svp64_mode
,
1357 self
.svp64_rm
, self
.bigendian
]
1359 def get_rdflags(e
, cu
):
1361 for idx
in range(cu
.n_src
):
1362 regfile
, regname
, _
= cu
.get_in_spec(idx
)
1363 rdflag
, read
= regspec_decode_read(e
, regfile
, regname
)
1365 print("rdflags", rdl
)
1369 if __name__
== '__main__':
1370 svp64
= SVP64PowerDecoder()
1371 vl
= rtlil
.convert(svp64
, ports
=svp64
.ports())
1372 with
open("svp64_dec.il", "w") as f
:
1374 pdecode
= create_pdecode()
1375 dec2
= PowerDecode2(pdecode
)
1376 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
1377 with
open("dec2.il", "w") as f
: