1 # Based on GardenSnake - a parser generator demonstration program
2 # GardenSnake was released into the Public Domain by Andrew Dalke.
4 # Portions of this work are derived from Python's Grammar definition
5 # and may be covered under the Python copyright and license
7 # Andrew Dalke / Dalke Scientific Software, LLC
8 # 30 August 2006 / Cape Town, South Africa
10 # Modifications for inclusion in PLY distribution
12 from pprint
import pprint
14 from ply
import lex
, yacc
18 from soc
.decoder
.power_decoder
import create_pdecode
19 from nmigen
.back
.pysim
import Simulator
, Delay
20 from nmigen
import Module
, Signal
22 from soc
.decoder
.pseudo
.parser
import GardenSnakeCompiler
23 from soc
.decoder
.selectable_int
import SelectableInt
, selectconcat
24 from soc
.decoder
.isa
.caller
import GPR
, Mem
27 ####### Test code #######
32 index <- (RS)[8*i:8*i+7]
33 RA <- [0]*56 || perm[0:7]
38 if index < 64 then index <- 0
49 index <- (RS)[8*i:8*i+7]
54 RA <- [0]*56|| perm[0:7]
61 if (RS)[63-n] = 0b1 then
71 else if a > EXTS(SI) then
80 in_range <- ((x | y) &
82 in_range <- (x + y) - (a + b)
87 src1 <- EXTZ((RA)[56:63])
89 in_range <- src21lo <= src1 & src1 <= src21hi
103 RT <- (RA) + EXTS(SI || [0]*16)
113 RT <- (load_data[56:63] || load_data[48:55]
114 || load_data[40:47] || load_data[32:39]
115 || load_data[24:31] || load_data[16:23]
116 || load_data[8:15] || load_data[0:7])
127 MEM(EA, 1) <- (RS)[56:63]
133 MEM(EA, 4) <- GPR(r)[32:63]
143 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
144 cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
167 l
.append(1 if (num
& (1 << i
)) else 0)
172 def get_reg_hex(reg
):
173 return hex(reg
.value
)
175 def convert_to_python(pcode
):
177 gsc
= GardenSnakeCompiler()
179 tree
= gsc
.compile(pcode
, mode
="exec", filename
="string")
180 tree
= ast
.fix_missing_locations(tree
)
181 regsused
= {'read_regs': gsc
.parser
.read_regs
,
182 'write_regs': gsc
.parser
.write_regs
,
183 'uninit_regs': gsc
.parser
.uninit_regs
}
184 return astor
.to_source(tree
), regsused
189 gsc
= GardenSnakeCompiler(debug
=True)
194 gsc
.gpr
= GPR(gsc
.parser
.sd
, gsc
.regfile
)
197 _compile
= gsc
.compile
199 tree
= _compile(code
, mode
="single", filename
="string")
200 tree
= ast
.fix_missing_locations(tree
)
201 print(ast
.dump(tree
))
204 print(astor
.dump_tree(tree
))
206 source
= astor
.to_source(tree
)
211 # Set up the GardenSnake run-time environment
214 print("-->", " ".join(map(str, args
)))
216 from soc
.decoder
.helpers
import (EXTS64
, EXTZ64
, ROTL64
, ROTL32
, MASK
,)
222 d
["SelectableInt"] = SelectableInt
223 d
["concat"] = selectconcat
226 d
["memassign"] = gsc
.mem
.memassign
229 gsc
.gpr
.set_form(form
)
230 getform
= gsc
.parser
.sd
.sigforms
[form
]._asdict
()
231 #print ("getform", form)
232 # for k, f in getform.items():
236 compiled_code
= compile(source
, mode
="exec", filename
="<string>")
240 instruction
= Signal(32)
242 m
.submodules
.decode
= decode
= gsc
.parser
.sd
243 comb
+= decode
.raw_opcode_in
.eq(instruction
)
250 print("0x{:X}".format(ins
& 0xffffffff))
252 # ask the decoder to decode this binary data (endian'd)
253 yield decode
.bigendian
.eq(0) # little / big?
254 yield instruction
.eq(ins
) # raw binary instr.
257 # uninitialised regs, drop them into dict for function
258 for rname
in gsc
.parser
.uninit_regs
:
259 d
[rname
] = SelectableInt(0, 64) # uninitialised (to zero)
260 print("uninitialised", rname
, hex(d
[rname
].value
))
262 # read regs, drop them into dict for function
263 for rname
in gsc
.parser
.read_regs
:
264 regidx
= yield getattr(decode
.sigforms
['X'], rname
)
265 d
[rname
] = gsc
.gpr
[regidx
] # contents of regfile
266 d
["_%s" % rname
] = regidx
# actual register value
267 print("read reg", rname
, regidx
, hex(d
[rname
].value
))
269 exec(compiled_code
, d
) # code gets executed here in dict "d"
272 print(d
.keys()) # shows the variables that may have been created
274 print(decode
.sigforms
['X'])
275 x
= yield decode
.sigforms
['X'].RS
276 ra
= yield decode
.sigforms
['X'].RA
277 rb
= yield decode
.sigforms
['X'].RB
278 print("RA", ra
, d
['RA'])
279 print("RB", rb
, d
['RB'])
282 for wname
in gsc
.parser
.write_regs
:
285 print("write regs", regidx
, wname
, d
[wname
], reg
)
286 gsc
.gpr
[regidx
] = d
[wname
]
288 sim
.add_process(process
)
289 with sim
.write_vcd("simulator.vcd", "simulator.gtkw",
290 traces
=decode
.ports()):
295 for i
in range(0, len(gsc
.mem
.mem
), 16):
298 hexstr
.append("%02x" % gsc
.mem
.mem
[i
+j
])
299 hexstr
= ' '.join(hexstr
)
300 print ("mem %4x" % i
, hexstr
)
302 if __name__
== '__main__':