src/soc/experiment/alu_fsm.py

   1 """Simple example of a FSM-based ALU
   2
   3 This demonstrates a design that follows the valid/ready protocol of the
   4 ALU, but with a FSM implementation, instead of a pipeline.
   5
   6 The basic rules are:
   7
   8 1) p.ready_o is asserted on the initial ("Idle") state, otherwise it keeps low.
   9 2) n.valid_o is asserted on the final ("Done") state, otherwise it keeps low.
  10 3) The FSM stays in the Idle state while p.valid_i is low, otherwise
  11    it accepts the input data and moves on.
  12 4) The FSM stays in the Done state while n.ready_i is low, otherwise
  13    it releases the output data and goes back to the Idle state.
  14 """