src/soc/experiment/compldst_multi.py

   1 """LOAD / STORE Computation Unit.
   2
   3 This module covers POWER9-compliant Load and Store operations,
   4 with selection on each between immediate and indexed mode as
   5 options for the calculation of the Effective Address (EA),
   6 and also "update" mode which optionally stores that EA into
   7 an additional register.
   8
   9 ----
  10 Note: it took 15 attempts over several weeks to redraw the diagram
  11 needed to capture this FSM properly.  To understand it fully, please
  12 take the time to review the links, video, and diagram.
  13 ----
  14
  15 Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
  16 compute the "Effective Address", and, when ready the operand (src3_i)
  17 is stored in the computed address (passed through to the PortInterface)
  18
  19 Loads are activated when Go_Write[0] is enabled.  The EA is computed,
  20 and (as long as there was no exception) the data comes out (at any
  21 time from the PortInterface), and is captured by the LDCompSTUnit.
  22
  23 Both LD and ST may request that the address be computed from summing
  24 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
  25 the immediate (from the opcode).
  26
  27 Both LD and ST may also request "update" mode (op_is_update) which
  28 activates the use of Go_Write[1] to control storage of the EA into
  29 a *second* operand in the register file.
  30
  31 Thus this module has *TWO* write-requests to the register file and
  32 *THREE* read-requests to the register file (not all at the same time!)
  33 The regfile port usage is:
  34
  35     * LD-imm         1R1W
  36     * LD-imm-update  1R2W
  37     * LD-idx         2R1W
  38     * LD-idx-update  2R2W
  39
  40     * ST-imm         2R
  41     * ST-imm-update  2R1W
  42     * ST-idx         3R
  43     * ST-idx-update  3R1W
  44
  45 It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
  46 is not suited to (nmigen.FSM is clock-driven, and some aspects of
  47 the nested FSMs below are *combinatorial*).
  48
  49     * One FSM covers Operand collection and communication address-side
  50       with the LD/ST PortInterface.  its role ends when "RD_DONE" is asserted
  51
  52     * A second FSM activates to cover LD.  it activates if op_is_ld is true
  53
  54     * A third FSM activates to cover ST.  it activates if op_is_st is true
  55
  56     * The "overall" (fourth) FSM coordinates the progression and completion
  57       of the three other FSMs, firing "WR_RESET" which switches off "busy"
  58
  59 Full diagram:
  60
  61     https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
  62
  63 Links including to walk-through videos:
  64
  65     * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
  66     * http://libre-soc.org/openpower/isa/fixedload
  67     * http://libre-soc.org/openpower/isa/fixedstore
  68
  69 Related Bugreports:
  70
  71     * https://bugs.libre-soc.org/show_bug.cgi?id=302
  72     * https://bugs.libre-soc.org/show_bug.cgi?id=216
  73
  74 Terminology:
  75
  76     * EA - Effective Address
  77     * LD - Load
  78     * ST - Store
  79 """
  80
  81 from nmigen.compat.sim import run_simulation
  82 from nmigen.cli import verilog, rtlil
  83 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
  84 from nmigen.hdl.rec import Record, Layout
  85
  86 from nmutil.latch import SRLatch, latchregister
  87 from nmutil.byterev import byte_reverse
  88
  89 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  90 from soc.experiment.l0_cache import PortInterface
  91 from soc.fu.regspec import RegSpecAPI
  92
  93 from soc.decoder.power_enums import MicrOp, Function, LDSTMode
  94 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  95 from soc.decoder.power_decoder2 import Data
  96
  97
  98 class LDSTCompUnitRecord(CompUnitRecord):
  99     def __init__(self, rwid, opsubset=CompLDSTOpSubset, name=None):
 100         CompUnitRecord.__init__(self, opsubset, rwid,
 101                                 n_src=3, n_dst=2, name=name)
 102
 103         self.ad = go_record(1, name="cu_ad")  # address go in, req out
 104         self.st = go_record(1, name="cu_st")  # store go in, req out
 105
 106         self.addr_exc_o = Signal(reset_less=True)   # address exception
 107
 108         self.ld_o = Signal(reset_less=True)  # operation is a LD
 109         self.st_o = Signal(reset_less=True)  # operation is a ST
 110
 111         # hmm... are these necessary?
 112         self.load_mem_o = Signal(reset_less=True)  # activate memory LOAD
 113         self.stwd_mem_o = Signal(reset_less=True)  # activate memory STORE
 114
 115
 116 class LDSTCompUnit(RegSpecAPI, Elaboratable):
 117     """LOAD / STORE Computation Unit
 118
 119     Inputs
 120     ------
 121
 122     * :pi:     a PortInterface to the memory subsystem (read-write capable)
 123     * :rwid:   register width
 124     * :awid:   address width
 125
 126     Data inputs
 127     -----------
 128     * :src_i:  Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
 129
 130     Data (outputs)
 131     --------------
 132     * :data_o:     Dest out (LD)          - managed by wr[0] go/req
 133     * :addr_o:     Address out (LD or ST) - managed by wr[1] go/req
 134     * :addr_exc_o: Address/Data Exception occurred.  LD/ST must terminate
 135
 136     TODO: make addr_exc_o a data-type rather than a single-bit signal
 137           (see bug #302)
 138
 139     Control Signals (In)
 140     --------------------
 141
 142     * :oper_i:     operation being carried out (POWER9 decode LD/ST subset)
 143     * :issue_i:    LD/ST is being "issued".
 144     * :shadown_i:  Inverted-shadow is being held (stops STORE *and* WRITE)
 145     * :go_rd_i:    read is being actioned (latches in src regs)
 146     * :go_wr_i:    write mode (exactly like ALU CompUnit)
 147     * :go_ad_i:    address is being actioned (triggers actual mem LD)
 148     * :go_st_i:    store is being actioned (triggers actual mem STORE)
 149     * :go_die_i:   resets the unit back to "wait for issue"
 150
 151     Control Signals (Out)
 152     ---------------------
 153
 154     * :busy_o:      function unit is busy
 155     * :rd_rel_o:    request src1/src2
 156     * :adr_rel_o:   request address (from mem)
 157     * :sto_rel_o:   request store (to mem)
 158     * :req_rel_o:   request write (result)
 159     * :load_mem_o:  activate memory LOAD
 160     * :stwd_mem_o:  activate memory STORE
 161
 162     Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
 163     in a single cycle and the CompUnit set back to doing another op.
 164     This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
 165     depending on whether the operation is a ST or LD.
 166
 167     Note: LDSTCompUnit takes care of LE/BE normalisation:
 168     * LD data is normalised after receipt from the PortInterface
 169     * ST data is normalised *prior* to sending onto the PortInterface
 170     TODO: use one module for the byte-reverse as it's quite expensive in gates
 171     """
 172
 173     def __init__(self, pi=None, rwid=64, awid=48, opsubset=CompLDSTOpSubset,
 174                  debugtest=False, name=None):
 175         super().__init__(rwid)
 176         self.awid = awid
 177         self.pi = pi
 178         self.cu = cu = LDSTCompUnitRecord(rwid, opsubset, name=name)
 179         self.debugtest = debugtest
 180
 181         # POWER-compliant LD/ST has index and update: *fixed* number of ports
 182         self.n_src = n_src = 3   # RA, RB, RT/RS
 183         self.n_dst = n_dst = 2  # RA, RT/RS
 184
 185         # set up array of src and dest signals
 186         for i in range(n_src):
 187             j = i + 1  # name numbering to match src1/src2
 188             name = "src%d_i" % j
 189             setattr(self, name, getattr(cu, name))
 190
 191         dst = []
 192         for i in range(n_dst):
 193             j = i + 1  # name numbering to match dest1/2...
 194             name = "dest%d_o" % j
 195             setattr(self, name, getattr(cu, name))
 196
 197         # convenience names
 198         self.rd = cu.rd
 199         self.wr = cu.wr
 200         self.rdmaskn = cu.rdmaskn
 201         self.wrmask = cu.wrmask
 202         self.ad = cu.ad
 203         self.st = cu.st
 204         self.dest = cu._dest
 205
 206         # HACK: get data width from dest[0].  this is used across the board
 207         # (it really shouldn't be)
 208         self.data_wid = self.dest[0].shape()
 209
 210         self.go_rd_i = self.rd.go_i  # temporary naming
 211         self.go_wr_i = self.wr.go_i  # temporary naming
 212         self.go_ad_i = self.ad.go_i  # temp naming: go address in
 213         self.go_st_i = self.st.go_i  # temp naming: go store in
 214
 215         self.rd_rel_o = self.rd.rel_o  # temporary naming
 216         self.req_rel_o = self.wr.rel_o  # temporary naming
 217         self.adr_rel_o = self.ad.rel_o  # request address (from mem)
 218         self.sto_rel_o = self.st.rel_o  # request store (to mem)
 219
 220         self.issue_i = cu.issue_i
 221         self.shadown_i = cu.shadown_i
 222         self.go_die_i = cu.go_die_i
 223
 224         self.oper_i = cu.oper_i
 225         self.src_i = cu._src_i
 226
 227         self.data_o = Data(self.data_wid, name="o")  # Dest1 out: RT
 228         self.addr_o = Data(self.data_wid, name="ea")  # Addr out: Update => RA
 229         self.addr_exc_o = cu.addr_exc_o
 230         self.done_o = cu.done_o
 231         self.busy_o = cu.busy_o
 232
 233         self.ld_o = cu.ld_o
 234         self.st_o = cu.st_o
 235
 236         self.load_mem_o = cu.load_mem_o
 237         self.stwd_mem_o = cu.stwd_mem_o
 238
 239     def elaborate(self, platform):
 240         m = Module()
 241
 242         # temp/convenience
 243         comb = m.d.comb
 244         sync = m.d.sync
 245         issue_i = self.issue_i
 246
 247         #####################
 248         # latches for the FSM.
 249         m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
 250         m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
 251         m.submodules.alu_l = alu_l = SRLatch(sync=False, name="alu")
 252         m.submodules.adr_l = adr_l = SRLatch(sync=False, name="adr")
 253         m.submodules.lod_l = lod_l = SRLatch(sync=False, name="lod")
 254         m.submodules.sto_l = sto_l = SRLatch(sync=False, name="sto")
 255         m.submodules.wri_l = wri_l = SRLatch(sync=False, name="wri")
 256         m.submodules.upd_l = upd_l = SRLatch(sync=False, name="upd")
 257         m.submodules.rst_l = rst_l = SRLatch(sync=False, name="rst")
 258         m.submodules.lsd_l = lsd_l = SRLatch(sync=False, name="lsd") # done
 259
 260         ####################
 261         # signals
 262
 263         # opcode decode
 264         op_is_ld = Signal(reset_less=True)
 265         op_is_st = Signal(reset_less=True)
 266
 267         # ALU/LD data output control
 268         alu_valid = Signal(reset_less=True)  # ALU operands are valid
 269         alu_ok = Signal(reset_less=True)    # ALU out ok (1 clock delay valid)
 270         addr_ok = Signal(reset_less=True)   # addr ok (from PortInterface)
 271         ld_ok = Signal(reset_less=True)     # LD out ok from PortInterface
 272         wr_any = Signal(reset_less=True)    # any write (incl. store)
 273         rda_any = Signal(reset_less=True)   # any read for address ops
 274         rd_done = Signal(reset_less=True)   # all *necessary* operands read
 275         wr_reset = Signal(reset_less=True)  # final reset condition
 276
 277         # LD and ALU out
 278         alu_o = Signal(self.data_wid, reset_less=True)
 279         ldd_o = Signal(self.data_wid, reset_less=True)
 280
 281         ##############################
 282         # reset conditions for latches
 283
 284         # temporaries (also convenient when debugging)
 285         reset_o = Signal(reset_less=True)             # reset opcode
 286         reset_w = Signal(reset_less=True)             # reset write
 287         reset_u = Signal(reset_less=True)             # reset update
 288         reset_a = Signal(reset_less=True)             # reset adr latch
 289         reset_i = Signal(reset_less=True)             # issue|die (use a lot)
 290         reset_r = Signal(self.n_src, reset_less=True)  # reset src
 291         reset_s = Signal(reset_less=True)             # reset store
 292
 293         comb += reset_i.eq(issue_i | self.go_die_i)       # various
 294         comb += reset_o.eq(wr_reset | self.go_die_i)      # opcode reset
 295         comb += reset_w.eq(self.wr.go_i[0] | self.go_die_i)  # write reg 1
 296         comb += reset_u.eq(self.wr.go_i[1] | self.go_die_i)  # update (reg 2)
 297         comb += reset_s.eq(self.go_st_i | self.go_die_i)  # store reset
 298         comb += reset_r.eq(self.rd.go_i | Repl(self.go_die_i, self.n_src))
 299         comb += reset_a.eq(self.go_ad_i | self.go_die_i)
 300
 301         p_st_go = Signal(reset_less=True)
 302         sync += p_st_go.eq(self.st.go_i)
 303
 304         ##########################
 305         # FSM implemented through sequence of latches.  approximately this:
 306         # - opc_l       : opcode
 307         #    - src_l[0] : operands
 308         #    - src_l[1]
 309         #       - alu_l : looks after add of src1/2/imm (EA)
 310         #       - adr_l : waits for add (EA)
 311         #       - upd_l : waits for adr and Regfile (port 2)
 312         #    - src_l[2] : ST
 313         # - lod_l       : waits for adr (EA) and for LD Data
 314         # - wri_l       : waits for LD Data and Regfile (port 1)
 315         # - st_l        : waits for alu and operand2
 316         # - rst_l       : waits for all FSM paths to converge.
 317         # NOTE: use sync to stop combinatorial loops.
 318
 319         # opcode latch - inverted so that busy resets to 0
 320         # note this MUST be sync so as to avoid a combinatorial loop
 321         # between busy_o and issue_i on the reset latch (rst_l)
 322         sync += opc_l.s.eq(issue_i)  # XXX NOTE: INVERTED FROM book!
 323         sync += opc_l.r.eq(reset_o)  # XXX NOTE: INVERTED FROM book!
 324
 325         # src operand latch
 326         sync += src_l.s.eq(Repl(issue_i, self.n_src))
 327         sync += src_l.r.eq(reset_r)
 328
 329         # alu latch.  use sync-delay between alu_ok and valid to generate pulse
 330         comb += alu_l.s.eq(reset_i)
 331         comb += alu_l.r.eq(alu_ok & ~alu_valid & ~rda_any)
 332
 333         # addr latch
 334         comb += adr_l.s.eq(reset_i)
 335         sync += adr_l.r.eq(reset_a)
 336
 337         # ld latch
 338         comb += lod_l.s.eq(reset_i)
 339         comb += lod_l.r.eq(ld_ok)
 340
 341         # dest operand latch
 342         comb += wri_l.s.eq(issue_i)
 343         sync += wri_l.r.eq(reset_w | Repl(self.done_o, self.n_dst))
 344
 345         # update-mode operand latch (EA written to reg 2)
 346         sync += upd_l.s.eq(reset_i)
 347         sync += upd_l.r.eq(reset_u)
 348
 349         # store latch
 350         comb += sto_l.s.eq(addr_ok & op_is_st)
 351         sync += sto_l.r.eq(reset_s | p_st_go)
 352
 353         # ld/st done.  needed to stop LD/ST from activating repeatedly
 354         comb += lsd_l.s.eq(issue_i)
 355         sync += lsd_l.r.eq(reset_s | p_st_go | ld_ok)
 356
 357         # reset latch
 358         comb += rst_l.s.eq(addr_ok)  # start when address is ready
 359         comb += rst_l.r.eq(issue_i)
 360
 361         # create a latch/register for the operand
 362         oper_r = CompLDSTOpSubset(name="oper_r")  # Dest register
 363         with m.If(self.issue_i):
 364             sync += oper_r.eq(self.oper_i)
 365
 366         # and for LD
 367         ldd_r = Signal(self.data_wid, reset_less=True)  # Dest register
 368         latchregister(m, ldd_o, ldd_r, ld_ok, name="ldo_r")
 369
 370         # and for each input from the incoming src operands
 371         srl = []
 372         for i in range(self.n_src):
 373             name = "src_r%d" % i
 374             src_r = Signal(self.data_wid, name=name, reset_less=True)
 375             with m.If(self.rd.go_i[i]):
 376                 sync += src_r.eq(self.src_i[i])
 377             with m.If(self.issue_i):
 378                 sync += src_r.eq(0)
 379             srl.append(src_r)
 380
 381         # and one for the output from the ADD (for the EA)
 382         addr_r = Signal(self.data_wid, reset_less=True)  # Effective Address
 383         latchregister(m, alu_o, addr_r, alu_l.q, "ea_r")
 384
 385         # select either zero or src1 if opcode says so
 386         op_is_z = oper_r.zero_a
 387         src1_or_z = Signal(self.data_wid, reset_less=True)
 388         m.d.comb += src1_or_z.eq(Mux(op_is_z, 0, srl[0]))
 389
 390         # select either immediate or src2 if opcode says so
 391         op_is_imm = oper_r.imm_data.imm_ok
 392         src2_or_imm = Signal(self.data_wid, reset_less=True)
 393         m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.imm, srl[1]))
 394
 395         # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
 396         comb += alu_o.eq(src1_or_z + src2_or_imm)  # actual EA
 397         m.d.sync += alu_ok.eq(alu_valid)             # keep ack in sync with EA
 398
 399         # decode bits of operand (latched)
 400         comb += op_is_st.eq(oper_r.insn_type == MicrOp.OP_STORE)  # ST
 401         comb += op_is_ld.eq(oper_r.insn_type == MicrOp.OP_LOAD)  # LD
 402         op_is_update = oper_r.ldst_mode == LDSTMode.update           # UPDATE
 403         op_is_cix = oper_r.ldst_mode == LDSTMode.cix           # cache-inhibit
 404         comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
 405         comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i)
 406         comb += self.ld_o.eq(op_is_ld)
 407         comb += self.st_o.eq(op_is_st)
 408
 409         ############################
 410         # Control Signal calculation
 411
 412         # busy signal
 413         busy_o = self.busy_o
 414         comb += self.busy_o.eq(opc_l.q)  # | self.pi.busy_o)  # busy out
 415
 416         # 1st operand read-request only when zero not active
 417         # 2nd operand only needed when immediate is not active
 418         slg = Cat(op_is_z, op_is_imm)
 419         bro = Repl(self.busy_o, self.n_src)
 420         comb += self.rd.rel_o.eq(src_l.q & bro & ~slg & ~self.rdmaskn)
 421
 422         # note when the address-related read "go" signals are active
 423         comb += rda_any.eq(self.rd.go_i[0] | self.rd.go_i[1])
 424
 425         # alu input valid when 1st and 2nd ops done (or imm not active)
 426         comb += alu_valid.eq(busy_o & ~(self.rd.rel_o[0] | self.rd.rel_o[1]))
 427
 428         # 3rd operand only needed when operation is a store
 429         comb += self.rd.rel_o[2].eq(src_l.q[2] & busy_o & op_is_st)
 430
 431         # all reads done when alu is valid and 3rd operand needed
 432         comb += rd_done.eq(alu_valid & ~self.rd.rel_o[2])
 433
 434         # address release only if addr ready, but Port must be idle
 435         comb += self.adr_rel_o.eq(alu_valid & adr_l.q & busy_o)
 436
 437         # store release when st ready *and* all operands read (and no shadow)
 438         comb += self.st.rel_o.eq(sto_l.q & busy_o & rd_done & op_is_st &
 439                                self.shadown_i)
 440
 441         # request write of LD result.  waits until shadow is dropped.
 442         comb += self.wr.rel_o[0].eq(rd_done & wri_l.q & busy_o & lod_l.qn &
 443                                   op_is_ld & self.shadown_i)
 444
 445         # request write of EA result only in update mode
 446         comb += self.wr.rel_o[1].eq(upd_l.q & busy_o & op_is_update &
 447                                   alu_valid & self.shadown_i)
 448
 449         # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
 450         comb += wr_any.eq(self.st.go_i | p_st_go |
 451                           self.wr.go_i[0] | self.wr.go_i[1])
 452         comb += wr_reset.eq(rst_l.q & busy_o & self.shadown_i &
 453                             ~(self.st.rel_o | self.wr.rel_o[0] |
 454                               self.wr.rel_o[1]) &
 455                             (lod_l.qn | op_is_st))
 456         comb += self.done_o.eq(wr_reset)
 457
 458         ######################
 459         # Data/Address outputs
 460
 461         # put the LD-output register directly onto the output bus on a go_write
 462         comb += self.data_o.data.eq(self.dest[0])
 463         with m.If(self.wr.go_i[0]):
 464             comb += self.dest[0].eq(ldd_r)
 465
 466         # "update" mode, put address out on 2nd go-write
 467         comb += self.addr_o.data.eq(self.dest[1])
 468         with m.If(op_is_update & self.wr.go_i[1]):
 469             comb += self.dest[1].eq(addr_r)
 470
 471         # need to look like MultiCompUnit: put wrmask out.
 472         # XXX may need to make this enable only when write active
 473         comb += self.wrmask.eq(bro & Cat(op_is_ld, op_is_update))
 474
 475         ###########################
 476         # PortInterface connections
 477         pi = self.pi
 478
 479         # connect to LD/ST PortInterface.
 480         comb += pi.is_ld_i.eq(op_is_ld & busy_o)  # decoded-LD
 481         comb += pi.is_st_i.eq(op_is_st & busy_o)  # decoded-ST
 482         comb += pi.data_len.eq(oper_r.data_len)  # data_len
 483         # address: use sync to avoid long latency
 484         sync += pi.addr.data.eq(addr_r)           # EA from adder
 485         sync += pi.addr.ok.eq(alu_ok & lsd_l.q)  # "do address stuff" (once)
 486         comb += self.addr_exc_o.eq(pi.addr_exc_o)  # exception occurred
 487         comb += addr_ok.eq(self.pi.addr_ok_o)  # no exc, address fine
 488
 489         # byte-reverse on LD
 490         with m.If(oper_r.byte_reverse):
 491             # byte-reverse the data based on ld/st width (turn it to LE)
 492             data_len = oper_r.data_len
 493             lddata_r = byte_reverse(m, 'lddata_r', pi.ld.data, data_len)
 494             comb += ldd_o.eq(lddata_r)  # put reversed- data out
 495         with m.Else():
 496             comb += ldd_o.eq(pi.ld.data)  # put data out, straight (as BE)
 497         # ld - ld gets latched in via lod_l
 498         comb += ld_ok.eq(pi.ld.ok)  # ld.ok *closes* (freezes) ld data
 499
 500         # byte-reverse on ST
 501         op3 = srl[2] # 3rd operand latch
 502         with m.If(oper_r.byte_reverse):
 503             # byte-reverse the data based on width
 504             data_len = oper_r.data_len
 505             stdata_r = byte_reverse(m, 'stdata_r', op3, data_len)
 506             comb += pi.st.data.eq(stdata_r)
 507         with m.Else():
 508             comb += pi.st.data.eq(op3)
 509         # store - data goes in based on go_st
 510         comb += pi.st.ok.eq(self.st.go_i)  # go store signals st data valid
 511
 512         return m
 513
 514     def get_out(self, i):
 515         """make LDSTCompUnit look like RegSpecALUAPI"""
 516         if i == 0:
 517             return self.data_o
 518         if i == 1:
 519             return self.addr_o
 520         # return self.dest[i]
 521
 522     def get_fu_out(self, i):
 523         return self.get_out(i)
 524
 525     def __iter__(self):
 526         yield self.rd.go_i
 527         yield self.go_ad_i
 528         yield self.wr.go_i
 529         yield self.go_st_i
 530         yield self.issue_i
 531         yield self.shadown_i
 532         yield self.go_die_i
 533         yield from self.oper_i.ports()
 534         yield from self.src_i
 535         yield self.busy_o
 536         yield self.rd.rel_o
 537         yield self.adr_rel_o
 538         yield self.sto_rel_o
 539         yield self.wr.rel_o
 540         yield from self.data_o.ports()
 541         yield from self.addr_o.ports()
 542         yield self.load_mem_o
 543         yield self.stwd_mem_o
 544
 545     def ports(self):
 546         return list(self)
 547
 548
 549 def wait_for(sig, wait=True, test1st=False):
 550     v = (yield sig)
 551     print("wait for", sig, v, wait, test1st)
 552     if test1st and bool(v) == wait:
 553         return
 554     while True:
 555         yield
 556         v = (yield sig)
 557         #print("...wait for", sig, v)
 558         if bool(v) == wait:
 559             break
 560
 561
 562 def store(dut, src1, src2, src3, imm, imm_ok=True, update=False,
 563           byterev=True):
 564     print("ST", src1, src2, src3, imm, imm_ok, update)
 565     yield dut.oper_i.insn_type.eq(MicrOp.OP_STORE)
 566     yield dut.oper_i.data_len.eq(2)  # half-word
 567     yield dut.oper_i.byte_reverse.eq(byterev)
 568     yield dut.src1_i.eq(src1)
 569     yield dut.src2_i.eq(src2)
 570     yield dut.src3_i.eq(src3)
 571     yield dut.oper_i.imm_data.imm.eq(imm)
 572     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 573     yield dut.oper_i.update.eq(update)
 574     yield dut.issue_i.eq(1)
 575     yield
 576     yield dut.issue_i.eq(0)
 577
 578     if imm_ok:
 579         active_rel = 0b101
 580     else:
 581         active_rel = 0b111
 582     # wait for all active rel signals to come up
 583     while True:
 584         rel = yield dut.rd.rel_o
 585         if rel == active_rel:
 586             break
 587         yield
 588     yield dut.rd.go.eq(active_rel)
 589     yield
 590     yield dut.rd.go.eq(0)
 591
 592     yield from wait_for(dut.adr_rel_o, False, test1st=True)
 593     # yield from wait_for(dut.adr_rel_o)
 594     # yield dut.ad.go.eq(1)
 595     # yield
 596     # yield dut.ad.go.eq(0)
 597
 598     if update:
 599         yield from wait_for(dut.wr.rel_o[1])
 600         yield dut.wr.go.eq(0b10)
 601         yield
 602         addr = yield dut.addr_o
 603         print("addr", addr)
 604         yield dut.wr.go.eq(0)
 605     else:
 606         addr = None
 607
 608     yield from wait_for(dut.sto_rel_o)
 609     yield dut.go_st_i.eq(1)
 610     yield
 611     yield dut.go_st_i.eq(0)
 612     yield from wait_for(dut.busy_o, False)
 613     # wait_for(dut.stwd_mem_o)
 614     yield
 615     return addr
 616
 617
 618 def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False,
 619          byterev=True):
 620     print("LD", src1, src2, imm, imm_ok, update)
 621     yield dut.oper_i.insn_type.eq(MicrOp.OP_LOAD)
 622     yield dut.oper_i.data_len.eq(2)  # half-word
 623     yield dut.oper_i.byte_reverse.eq(byterev)
 624     yield dut.src1_i.eq(src1)
 625     yield dut.src2_i.eq(src2)
 626     yield dut.oper_i.zero_a.eq(zero_a)
 627     yield dut.oper_i.imm_data.imm.eq(imm)
 628     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 629     yield dut.issue_i.eq(1)
 630     yield
 631     yield dut.issue_i.eq(0)
 632     yield
 633
 634     # set up read-operand flags
 635     rd = 0b00
 636     if not imm_ok:  # no immediate means RB register needs to be read
 637         rd |= 0b10
 638     if not zero_a:  # no zero-a means RA needs to be read
 639         rd |= 0b01
 640
 641     # wait for the operands (RA, RB, or both)
 642     if rd:
 643         yield dut.rd.go.eq(rd)
 644         yield from wait_for(dut.rd.rel_o)
 645         yield dut.rd.go.eq(0)
 646
 647     yield from wait_for(dut.adr_rel_o, False, test1st=True)
 648     # yield dut.ad.go.eq(1)
 649     # yield
 650     # yield dut.ad.go.eq(0)
 651
 652     if update:
 653         yield from wait_for(dut.wr.rel_o[1])
 654         yield dut.wr.go.eq(0b10)
 655         yield
 656         addr = yield dut.addr_o
 657         print("addr", addr)
 658         yield dut.wr.go.eq(0)
 659     else:
 660         addr = None
 661
 662     yield from wait_for(dut.wr.rel_o[0], test1st=True)
 663     yield dut.wr.go.eq(1)
 664     yield
 665     data = yield dut.data_o
 666     print(data)
 667     yield dut.wr.go.eq(0)
 668     yield from wait_for(dut.busy_o)
 669     yield
 670     # wait_for(dut.stwd_mem_o)
 671     return data, addr
 672
 673
 674 def ldst_sim(dut):
 675
 676     ###################
 677     # immediate version
 678
 679     # two STs (different addresses)
 680     yield from store(dut, 4, 0, 3, 2)  # ST reg4 into addr rfile[reg3]+2
 681     yield from store(dut, 2, 0, 9, 2)  # ST reg4 into addr rfile[reg9]+2
 682     yield
 683     # two LDs (deliberately LD from the 1st address then 2nd)
 684     data, addr = yield from load(dut, 4, 0, 2)
 685     assert data == 0x0003, "returned %x" % data
 686     data, addr = yield from load(dut, 2, 0, 2)
 687     assert data == 0x0009, "returned %x" % data
 688     yield
 689
 690     # indexed version
 691     yield from store(dut, 9, 5, 3, 0, imm_ok=False)
 692     data, addr = yield from load(dut, 9, 5, 0, imm_ok=False)
 693     assert data == 0x0003, "returned %x" % data
 694
 695     # update-immediate version
 696     addr = yield from store(dut, 9, 6, 3, 2, update=True)
 697     assert addr == 0x000b, "returned %x" % addr
 698
 699     # update-indexed version
 700     data, addr = yield from load(dut, 9, 5, 0, imm_ok=False, update=True)
 701     assert data == 0x0003, "returned %x" % data
 702     assert addr == 0x000e, "returned %x" % addr
 703
 704     # immediate *and* zero version
 705     data, addr = yield from load(dut, 1, 4, 8, imm_ok=True, zero_a=True)
 706     assert data == 0x0008, "returned %x" % data
 707
 708
 709 class TestLDSTCompUnit(LDSTCompUnit):
 710
 711     def __init__(self, rwid):
 712         from soc.experiment.l0_cache import TstL0CacheBuffer
 713         self.l0 = l0 = TstL0CacheBuffer()
 714         pi = l0.l0.dports[0].pi
 715         LDSTCompUnit.__init__(self, pi, rwid, 4)
 716
 717     def elaborate(self, platform):
 718         m = LDSTCompUnit.elaborate(self, platform)
 719         m.submodules.l0 = self.l0
 720         m.d.comb += self.ad.go.eq(self.ad.rel)  # link addr-go direct to rel
 721         return m
 722
 723
 724 def test_scoreboard():
 725
 726     dut = TestLDSTCompUnit(16)
 727     vl = rtlil.convert(dut, ports=dut.ports())
 728     with open("test_ldst_comp.il", "w") as f:
 729         f.write(vl)
 730
 731     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd')
 732
 733
 734 class TestLDSTCompUnitRegSpec(LDSTCompUnit):
 735
 736     def __init__(self):
 737         from soc.experiment.l0_cache import TstL0CacheBuffer
 738         from soc.fu.ldst.pipe_data import LDSTPipeSpec
 739         regspec = LDSTPipeSpec.regspec
 740         self.l0 = l0 = TstL0CacheBuffer()
 741         pi = l0.l0.dports[0].pi
 742         LDSTCompUnit.__init__(self, pi, regspec, 4)
 743
 744     def elaborate(self, platform):
 745         m = LDSTCompUnit.elaborate(self, platform)
 746         m.submodules.l0 = self.l0
 747         m.d.comb += self.ad.go.eq(self.ad.rel)  # link addr-go direct to rel
 748         return m
 749
 750
 751 def test_scoreboard_regspec():
 752
 753     dut = TestLDSTCompUnitRegSpec()
 754     vl = rtlil.convert(dut, ports=dut.ports())
 755     with open("test_ldst_comp.il", "w") as f:
 756         f.write(vl)
 757
 758     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_regspec.vcd')
 759
 760
 761 if __name__ == '__main__':
 762     test_scoreboard_regspec()
 763     test_scoreboard()