src/soc/experiment/compldst_multi.py

   1 """ LOAD / STORE Computation Unit.
   2
   3     This module covers POWER9-compliant Load and Store operations,
   4     with selection on each between immediate and indexed mode as
   5     options for the calculation of the Effective Address (EA),
   6     and also "update" mode which optionally stores that EA into
   7     an additional register.
   8
   9     ----
  10     Note: it took 15 attempts over several weeks to redraw the diagram
  11     needed to capture this FSM properly.  To understand it fully, please
  12     take the time to review the links, video, and diagram.
  13     ----
  14
  15     Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
  16     compute the "Effective Address", and, when ready the operand (src3_i)
  17     is stored in the computed address (passed through to the PortInterface)
  18
  19     Loads are activated when Go_Write[0] is enabled.  The EA is computed,
  20     and (as long as there was no exception) the data comes out (at any
  21     time from the PortInterface), and is captured by the LDCompSTUnit.
  22
  23     Both LD and ST may request that the address be computed from summing
  24     operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
  25     the immediate (from the opcode).
  26
  27     Both LD and ST may also request "update" mode (op_is_update) which
  28     activates the use of Go_Write[1] to control storage of the EA into
  29     a *second* operand in the register file.
  30
  31     Thus this module has *TWO* write-requests to the register file and
  32     *THREE* read-requests to the register file (not all at the same time!)
  33     The regfile port usage is:
  34
  35     * LD-imm         1R1W
  36     * LD-imm-update  1R2W
  37     * LD-idx         2R1W
  38     * LD-idx-update  2R2W
  39
  40     * ST-imm         2R
  41     * ST-imm-update  2R1W
  42     * ST-idx         3R
  43     * ST-idx-update  3R1W
  44
  45     It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
  46     is not suited to (nmigen.FSM is clock-driven, and some aspects of
  47     the nested FSMs below are *combinatorial*).
  48
  49     * One FSM covers Operand collection and communication address-side
  50       with the LD/ST PortInterface.  its role ends when "RD_DONE" is asserted
  51
  52     * A second FSM activates to cover LD.  it activates if op_is_ld is true
  53
  54     * A third FSM activates to cover ST.  it activates if op_is_st is true
  55
  56     * The "overall" (fourth) FSM coordinates the progression and completion
  57       of the three other FSMs, firing "WR_RESET" which switches off "busy"
  58
  59     Full diagram:
  60     https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
  61
  62     Links including to walk-through videos:
  63     * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
  64     * http://libre-soc.org/openpower/isa/fixedload
  65     * http://libre-soc.org/openpower/isa/fixedstore
  66
  67     Related Bugreports:
  68     * https://bugs.libre-soc.org/show_bug.cgi?id=302
  69
  70     Terminology:
  71
  72     * EA - Effective Address
  73     * LD - Load
  74     * ST - Store
  75 """
  76
  77 from nmigen.compat.sim import run_simulation
  78 from nmigen.cli import verilog, rtlil
  79 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
  80 from nmigen.hdl.rec import Record, Layout
  81
  82 from nmutil.latch import SRLatch, latchregister
  83
  84 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  85 from soc.experiment.l0_cache import PortInterface
  86 from soc.experiment.testmem import TestMemory
  87
  88 from soc.decoder.power_enums import InternalOp, Function
  89 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  90
  91
  92 class LDSTCompUnitRecord(CompUnitRecord):
  93     def __init__(self, rwid, name=None):
  94         CompUnitRecord.__init__(self, CompLDSTOpSubset, rwid,
  95                                 n_src=3, n_dst=2, name=name)
  96
  97         self.ad = go_record(1, name="ad") # address go in, req out
  98         self.st = go_record(1, name="st") # store go in, req out
  99
 100         self.addr_exc_o = Signal(reset_less=True)   # address exception
 101
 102         self.ld_o = Signal(reset_less=True)  # operation is a LD
 103         self.st_o = Signal(reset_less=True)  # operation is a ST
 104
 105         # hmm... are these necessary?
 106         self.load_mem_o = Signal(reset_less=True)  # activate memory LOAD
 107         self.stwd_mem_o = Signal(reset_less=True)  # activate memory STORE
 108
 109
 110 class LDSTCompUnit(Elaboratable):
 111     """LOAD / STORE Computation Unit
 112
 113     Inputs
 114     ------
 115
 116     * :pi:     a PortInterface to the memory subsystem (read-write capable)
 117     * :rwid:   register width
 118     * :awid:   address width
 119
 120     Data inputs
 121     -----------
 122     * :src_i:  Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
 123
 124     Data (outputs)
 125     --------------
 126     * :data_o:     Dest out (LD)          - managed by wr[0] go/req
 127     * :addr_o:     Address out (LD or ST) - managed by wr[1] go/req
 128     * :addr_exc_o: Address/Data Exception occurred.  LD/ST must terminate
 129
 130     TODO: make addr_exc_o a data-type rather than a single-bit signal
 131           (see bug #302)
 132
 133     Control Signals (In)
 134     --------------------
 135
 136     * :oper_i:     operation being carried out (POWER9 decode LD/ST subset)
 137     * :issue_i:    LD/ST is being "issued".
 138     * :shadown_i:  Inverted-shadow is being held (stops STORE *and* WRITE)
 139     * :go_rd_i:    read is being actioned (latches in src regs)
 140     * :go_wr_i:    write mode (exactly like ALU CompUnit)
 141     * :go_ad_i:    address is being actioned (triggers actual mem LD)
 142     * :go_st_i:    store is being actioned (triggers actual mem STORE)
 143     * :go_die_i:   resets the unit back to "wait for issue"
 144
 145     Control Signals (Out)
 146     ---------------------
 147
 148     * :busy_o:      function unit is busy
 149     * :rd_rel_o:    request src1/src2
 150     * :adr_rel_o:   request address (from mem)
 151     * :sto_rel_o:   request store (to mem)
 152     * :req_rel_o:   request write (result)
 153     * :load_mem_o:  activate memory LOAD
 154     * :stwd_mem_o:  activate memory STORE
 155
 156     Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
 157     in a single cycle and the CompUnit set back to doing another op.
 158     This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
 159     depending on whether the operation is a ST or LD.
 160     """
 161
 162     def __init__(self, pi, rwid=64, awid=48, debugtest=False):
 163         self.rwid = rwid
 164         self.awid = awid
 165         self.pi = pi
 166         self.cu = cu = LDSTCompUnitRecord(rwid)
 167         self.debugtest = debugtest
 168
 169         # POWER-compliant LD/ST has index and update: *fixed* number of ports
 170         self.n_src = n_src = 3   # RA, RB, RT/RS
 171         self.n_dst = n_dst = 2 # RA, RT/RS
 172
 173         # set up array of src and dest signals
 174         for i in range(n_src):
 175             j = i + 1 # name numbering to match src1/src2
 176             name = "src%d_i" % j
 177             setattr(self, name, getattr(cu, name))
 178
 179         dst = []
 180         for i in range(n_dst):
 181             j = i + 1 # name numbering to match dest1/2...
 182             name = "dest%d_i" % j
 183             setattr(self, name, getattr(cu, name))
 184
 185         # convenience names
 186         self.rd = cu.rd
 187         self.wr = cu.wr
 188         self.ad = cu.ad
 189         self.st = cu.st
 190
 191         self.go_rd_i = self.rd.go # temporary naming
 192         self.go_wr_i = self.wr.go # temporary naming
 193         self.go_ad_i = self.ad.go # temp naming: go address in
 194         self.go_st_i = self.st.go  # temp naming: go store in
 195
 196         self.rd_rel_o = self.rd.rel # temporary naming
 197         self.req_rel_o = self.wr.rel # temporary naming
 198         self.adr_rel_o = self.ad.rel  # request address (from mem)
 199         self.sto_rel_o = self.st.rel  # request store (to mem)
 200
 201         self.issue_i = cu.issue_i
 202         self.shadown_i = cu.shadown_i
 203         self.go_die_i = cu.go_die_i
 204
 205         self.oper_i = cu.oper_i
 206         self.src_i = cu._src_i
 207         self.dest = cu._dest
 208
 209         self.data_o = self.dest[0]  # Dest1 out: RT
 210         self.addr_o = self.dest[1]  # Address out (LD or ST) - Update => RA
 211         self.addr_exc_o = cu.addr_exc_o
 212         self.done_o = cu.done_o
 213         self.busy_o = cu.busy_o
 214
 215         self.ld_o = cu.ld_o
 216         self.st_o = cu.st_o
 217
 218         self.load_mem_o = cu.load_mem_o
 219         self.stwd_mem_o = cu.stwd_mem_o
 220
 221     def elaborate(self, platform):
 222         m = Module()
 223
 224         # temp/convenience
 225         comb = m.d.comb
 226         sync = m.d.sync
 227         issue_i = self.issue_i
 228
 229         #####################
 230         # latches for the FSM.
 231         m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
 232         m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
 233         m.submodules.alu_l = alu_l = SRLatch(sync=False, name="alu")
 234         m.submodules.adr_l = adr_l = SRLatch(sync=False, name="adr")
 235         m.submodules.lod_l = lod_l = SRLatch(sync=False, name="lod")
 236         m.submodules.sto_l = sto_l = SRLatch(sync=False, name="sto")
 237         m.submodules.wri_l = wri_l = SRLatch(sync=False, name="wri")
 238         m.submodules.upd_l = upd_l = SRLatch(sync=False, name="upd")
 239         m.submodules.rst_l = rst_l = SRLatch(sync=False, name="rst")
 240
 241         ####################
 242         # signals
 243
 244         # opcode decode
 245         op_is_ld = Signal(reset_less=True)
 246         op_is_st = Signal(reset_less=True)
 247
 248         # ALU/LD data output control
 249         alu_valid = Signal(reset_less=True) # ALU operands are valid
 250         alu_ok = Signal(reset_less=True)    # ALU out ok (1 clock delay valid)
 251         addr_ok = Signal(reset_less=True)   # addr ok (from PortInterface)
 252         ld_ok = Signal(reset_less=True)     # LD out ok from PortInterface
 253         wr_any = Signal(reset_less=True)    # any write (incl. store)
 254         rda_any = Signal(reset_less=True)   # any read for address ops
 255         rd_done = Signal(reset_less=True)   # all *necessary* operands read
 256         wr_reset = Signal(reset_less=True)  # final reset condition
 257
 258         # LD and ALU out
 259         alu_o = Signal(self.rwid, reset_less=True)
 260         ldd_o = Signal(self.rwid, reset_less=True)
 261
 262         # select immediate or src2 reg to add
 263         src2_or_imm = Signal(self.rwid, reset_less=True)
 264         src_sel = Signal(reset_less=True)
 265
 266         ##############################
 267         # reset conditions for latches
 268
 269         # temporaries (also convenient when debugging)
 270         reset_o = Signal(reset_less=True)             # reset opcode
 271         reset_w = Signal(reset_less=True)             # reset write
 272         reset_u = Signal(reset_less=True)             # reset update
 273         reset_a = Signal(reset_less=True)             # reset adr latch
 274         reset_i = Signal(reset_less=True)             # issue|die (use a lot)
 275         reset_r = Signal(self.n_src, reset_less=True) # reset src
 276         reset_s = Signal(reset_less=True)             # reset store
 277
 278         comb += reset_i.eq(issue_i | self.go_die_i)       # various
 279         comb += reset_o.eq(wr_reset | self.go_die_i)      # opcode reset
 280         comb += reset_w.eq(self.wr.go[0] | self.go_die_i) # write reg 1
 281         comb += reset_u.eq(self.wr.go[1] | self.go_die_i) # update (reg 2)
 282         comb += reset_s.eq(self.go_st_i | self.go_die_i)  # store reset
 283         comb += reset_r.eq(self.rd.go | Repl(self.go_die_i, self.n_src))
 284         comb += reset_a.eq(self.go_ad_i | self.go_die_i)
 285
 286         ##########################
 287         # FSM implemented through sequence of latches.  approximately this:
 288         # - opc_l       : opcode
 289         #    - src_l[0] : operands
 290         #    - src_l[1]
 291         #       - alu_l : looks after add of src1/2/imm (EA)
 292         #       - adr_l : waits for add (EA)
 293         #       - upd_l : waits for adr and Regfile (port 2)
 294         #    - src_l[2] : ST
 295         # - lod_l       : waits for adr (EA) and for LD Data
 296         # - wri_l       : waits for LD Data and Regfile (port 1)
 297         # - st_l        : waits for alu and operand2
 298         # - rst_l       : waits for all FSM paths to converge.
 299         # NOTE: use sync to stop combinatorial loops.
 300
 301         # opcode latch - inverted so that busy resets to 0
 302         # note this MUST be sync so as to avoid a combinatorial loop
 303         # between busy_o and issue_i on the reset latch (rst_l)
 304         sync += opc_l.s.eq(issue_i)  # XXX NOTE: INVERTED FROM book!
 305         sync += opc_l.r.eq(reset_o)  # XXX NOTE: INVERTED FROM book!
 306
 307         # src operand latch
 308         sync += src_l.s.eq(Repl(issue_i, self.n_src))
 309         sync += src_l.r.eq(reset_r)
 310
 311         # alu latch.  use sync-delay between alu_ok and valid to generate pulse
 312         comb += alu_l.s.eq(reset_i)
 313         comb += alu_l.r.eq(alu_ok & ~alu_valid & ~rda_any)
 314
 315         # addr latch
 316         comb += adr_l.s.eq(reset_i)
 317         sync += adr_l.r.eq(reset_a)
 318
 319         # ld latch
 320         comb += lod_l.s.eq(reset_i)
 321         comb += lod_l.r.eq(ld_ok)
 322
 323         # dest operand latch
 324         comb += wri_l.s.eq(issue_i)
 325         sync += wri_l.r.eq(reset_w)
 326
 327         # update-mode operand latch (EA written to reg 2)
 328         sync += upd_l.s.eq(reset_i)
 329         sync += upd_l.r.eq(reset_u)
 330
 331         # store latch
 332         comb += sto_l.s.eq(addr_ok & op_is_st)
 333         comb += sto_l.r.eq(reset_s)
 334
 335         # reset latch
 336         comb += rst_l.s.eq(addr_ok) # start when address is ready
 337         comb += rst_l.r.eq(issue_i)
 338
 339         # create a latch/register for the operand
 340         oper_r = CompLDSTOpSubset()  # Dest register
 341         latchregister(m, self.oper_i, oper_r, self.issue_i, name="oper_l")
 342
 343         # and for LD
 344         ldd_r = Signal(self.rwid, reset_less=True)  # Dest register
 345         latchregister(m, ldd_o, ldd_r, ld_ok, name="ldo_r")
 346
 347         # and for each input from the incoming src operands
 348         srl = []
 349         for i in range(self.n_src):
 350             name = "src_r%d" % i
 351             src_r = Signal(self.rwid, name=name, reset_less=True)
 352             latchregister(m, self.src_i[i], src_r, src_l.q[i], name + '_l')
 353             srl.append(src_r)
 354
 355         # and one for the output from the ADD (for the EA)
 356         addr_r = Signal(self.rwid, reset_less=True)  # Effective Address Latch
 357         latchregister(m, alu_o, addr_r, alu_l.q, "ea_r")
 358
 359         # select either immediate or src2 if opcode says so
 360         op_is_imm = oper_r.imm_data.imm_ok
 361         src2_or_imm = Signal(self.rwid, reset_less=True)
 362         m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.imm, srl[1]))
 363
 364         # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
 365         sync += alu_o.eq(srl[0] + src2_or_imm) # actual EA
 366         sync += alu_ok.eq(alu_valid)             # keep ack in sync with EA
 367
 368         # decode bits of operand (latched)
 369         comb += op_is_st.eq(oper_r.insn_type == InternalOp.OP_STORE) # ST
 370         comb += op_is_ld.eq(oper_r.insn_type == InternalOp.OP_LOAD)  # LD
 371         op_is_update = oper_r.update                                 # UPDATE
 372         comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
 373         comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i)
 374         comb += self.ld_o.eq(op_is_ld)
 375         comb += self.st_o.eq(op_is_st)
 376
 377         ############################
 378         # Control Signal calculation
 379
 380         # busy signal
 381         busy_o = self.busy_o
 382         comb += self.busy_o.eq(opc_l.q) # | self.pi.busy_o)  # busy out
 383
 384         # 1st operand read-request is simple: always need it
 385         comb += self.rd.rel[0].eq(src_l.q[0] & busy_o)
 386
 387         # 2nd operand only needed when immediate is not active
 388         comb += self.rd.rel[1].eq(src_l.q[1] & busy_o & ~op_is_imm)
 389
 390         # note when the address-related read "go" signals are active
 391         comb += rda_any.eq(self.rd.go[0] | self.rd.go[1])
 392
 393         # alu input valid when 1st and 2nd ops done (or imm not active)
 394         comb += alu_valid.eq(busy_o & ~(self.rd.rel[0] | self.rd.rel[1]))
 395
 396         # 3rd operand only needed when operation is a store
 397         comb += self.rd.rel[2].eq(src_l.q[2] & busy_o & op_is_st)
 398
 399         # all reads done when alu is valid and 3rd operand needed
 400         comb += rd_done.eq(alu_valid & ~self.rd.rel[2])
 401
 402         # address release only if addr ready, but Port must be idle
 403         comb += self.adr_rel_o.eq(adr_l.q & busy_o)
 404
 405         # store release when st ready *and* all operands read (and no shadow)
 406         comb += self.st.rel.eq(sto_l.q & busy_o & rd_done & op_is_st &
 407                                self.shadown_i)
 408
 409         # request write of LD result.  waits until shadow is dropped.
 410         comb += self.wr.rel[0].eq(wri_l.q & busy_o & lod_l.qn & op_is_ld &
 411                                   self.shadown_i)
 412
 413         # request write of EA result only in update mode
 414         comb += self.wr.rel[1].eq(upd_l.q & busy_o & op_is_update &
 415                                   self.shadown_i)
 416
 417         # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
 418         comb += wr_any.eq(self.st.go | self.wr.go[0] | self.wr.go[1])
 419         comb += wr_reset.eq(rst_l.q & busy_o & self.shadown_i &
 420                     ~(self.st.rel | self.wr.rel[0] | self.wr.rel[1]) &
 421                      (lod_l.qn | op_is_st))
 422         comb += self.done_o.eq(wr_reset)
 423
 424         ######################
 425         # Data/Address outputs
 426
 427         # put the LD-output register directly onto the output bus on a go_write
 428         with m.If(self.wr.go[0]):
 429             comb += self.data_o.eq(ldd_r)
 430
 431         # "update" mode, put address out on 2nd go-write
 432         with m.If(op_is_update & self.wr.go[1]):
 433             comb += self.addr_o.eq(addr_r)
 434
 435         ###########################
 436         # PortInterface connections
 437         pi = self.pi
 438
 439         # connect to LD/ST PortInterface.
 440         comb += pi.is_ld_i.eq(op_is_ld & busy_o)  # decoded-LD
 441         comb += pi.is_st_i.eq(op_is_st & busy_o)  # decoded-ST
 442         comb += pi.op.eq(self.oper_i)    # op details (not all needed)
 443         # address
 444         comb += pi.addr.data.eq(addr_r)           # EA from adder
 445         comb += pi.addr.ok.eq(alu_ok & lod_l.q) # "go do address stuff"
 446         comb += self.addr_exc_o.eq(pi.addr_exc_o) # exception occurred
 447         comb += addr_ok.eq(self.pi.addr_ok_o)  # no exc, address fine
 448         # ld - ld gets latched in via lod_l
 449         comb += ldd_o.eq(pi.ld.data)  # ld data goes into ld reg (above)
 450         comb += ld_ok.eq(pi.ld.ok) # ld.ok *closes* (freezes) ld data
 451         # store - data goes in based on go_st
 452         comb += pi.st.data.eq(srl[2]) # 3rd operand latch
 453         comb += pi.st.ok.eq(self.st.go)  # go store signals st data valid
 454
 455         return m
 456
 457     def __iter__(self):
 458         yield self.rd.go
 459         yield self.go_ad_i
 460         yield self.wr.go
 461         yield self.go_st_i
 462         yield self.issue_i
 463         yield self.shadown_i
 464         yield self.go_die_i
 465         yield from self.oper_i.ports()
 466         yield from self.src_i
 467         yield self.busy_o
 468         yield self.rd.rel
 469         yield self.adr_rel_o
 470         yield self.sto_rel_o
 471         yield self.wr.rel
 472         yield self.data_o
 473         yield self.addr_o
 474         yield self.load_mem_o
 475         yield self.stwd_mem_o
 476
 477     def ports(self):
 478         return list(self)
 479
 480
 481 def wait_for(sig, wait=True, test1st=False):
 482     v = (yield sig)
 483     print("wait for", sig, v, wait, test1st)
 484     if test1st and bool(v) == wait:
 485         return
 486     while True:
 487         yield
 488         v = (yield sig)
 489         #print("...wait for", sig, v)
 490         if bool(v) == wait:
 491             break
 492
 493
 494 def store(dut, src1, src2, src3, imm, imm_ok=True, update=False):
 495     print ("ST", src1, src2, src3, imm, imm_ok, update)
 496     yield dut.oper_i.insn_type.eq(InternalOp.OP_STORE)
 497     yield dut.src1_i.eq(src1)
 498     yield dut.src2_i.eq(src2)
 499     yield dut.src3_i.eq(src3)
 500     yield dut.oper_i.imm_data.imm.eq(imm)
 501     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 502     yield dut.oper_i.update.eq(update)
 503     yield dut.issue_i.eq(1)
 504     yield
 505     yield dut.issue_i.eq(0)
 506     yield
 507     if imm_ok:
 508         yield dut.rd.go.eq(0b101)
 509     else:
 510         yield dut.rd.go.eq(0b111)
 511     yield from wait_for(dut.rd.rel)
 512     yield dut.rd.go.eq(0)
 513
 514     yield from wait_for(dut.adr_rel_o, False, test1st=True)
 515     #yield from wait_for(dut.adr_rel_o)
 516     #yield dut.ad.go.eq(1)
 517     #yield
 518     #yield dut.ad.go.eq(0)
 519
 520     if update:
 521         yield from wait_for(dut.wr.rel[1])
 522         yield dut.wr.go.eq(0b10)
 523         yield
 524         addr = yield dut.addr_o
 525         print ("addr", addr)
 526         yield dut.wr.go.eq(0)
 527     else:
 528         addr = None
 529
 530     yield from wait_for(dut.sto_rel_o)
 531     yield dut.go_st_i.eq(1)
 532     yield
 533     yield dut.go_st_i.eq(0)
 534     yield from wait_for(dut.busy_o, False)
 535     #wait_for(dut.stwd_mem_o)
 536     yield
 537     return addr
 538
 539
 540 def load(dut, src1, src2, imm, imm_ok=True, update=False):
 541     print ("LD", src1, src2, imm, imm_ok, update)
 542     yield dut.oper_i.insn_type.eq(InternalOp.OP_LOAD)
 543     yield dut.src1_i.eq(src1)
 544     yield dut.src2_i.eq(src2)
 545     yield dut.oper_i.imm_data.imm.eq(imm)
 546     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 547     yield dut.issue_i.eq(1)
 548     yield
 549     yield dut.issue_i.eq(0)
 550     yield
 551     if imm_ok:
 552         yield dut.rd.go.eq(0b01)
 553     else:
 554         yield dut.rd.go.eq(0b11)
 555     yield from wait_for(dut.rd.rel)
 556     yield dut.rd.go.eq(0)
 557
 558     yield from wait_for(dut.adr_rel_o, False, test1st=True)
 559     #yield dut.ad.go.eq(1)
 560     #yield
 561     #yield dut.ad.go.eq(0)
 562
 563     if update:
 564         yield from wait_for(dut.wr.rel[1])
 565         yield dut.wr.go.eq(0b10)
 566         yield
 567         addr = yield dut.addr_o
 568         print ("addr", addr)
 569         yield dut.wr.go.eq(0)
 570     else:
 571         addr = None
 572
 573     yield from wait_for(dut.wr.rel[0], test1st=True)
 574     yield dut.wr.go.eq(1)
 575     yield
 576     data = yield dut.data_o
 577     print (data)
 578     yield dut.wr.go.eq(0)
 579     yield from wait_for(dut.busy_o)
 580     yield
 581     # wait_for(dut.stwd_mem_o)
 582     return data, addr
 583
 584
 585 def scoreboard_sim(dut):
 586
 587     ###################
 588     # immediate version
 589
 590     # two STs (different addresses)
 591     yield from store(dut, 4, 0, 3, 2)  # ST reg4 into addr rfile[reg3]+2
 592     yield from store(dut, 2, 0, 9, 2)  # ST reg4 into addr rfile[reg9]+2
 593     yield
 594     # two LDs (deliberately LD from the 1st address then 2nd)
 595     data, addr = yield from load(dut, 4, 0, 2)
 596     assert data == 0x0003, "returned %x" % data
 597     data, addr  = yield from load(dut, 2, 0, 2)
 598     assert data == 0x0009, "returned %x" % data
 599     yield
 600
 601     # indexed version
 602     yield from store(dut, 4, 5, 3, 0, imm_ok=False)
 603     data, addr = yield from load(dut, 4, 5, 0, imm_ok=False)
 604     assert data == 0x0003, "returned %x" % data
 605
 606     # update-immediate version
 607     addr = yield from store(dut, 4, 6, 3, 2, update=True)
 608     assert addr == 0x0006, "returned %x" % addr
 609
 610     # update-indexed version
 611     data, addr  = yield from load(dut, 4, 5, 0, imm_ok=False, update=True)
 612     assert addr == 0x0009, "returned %x" % addr
 613
 614 class TestLDSTCompUnit(LDSTCompUnit):
 615
 616     def __init__(self, rwid):
 617         from soc.experiment.l0_cache import TstL0CacheBuffer
 618         self.l0 = l0 = TstL0CacheBuffer()
 619         pi = l0.l0.dports[0].pi
 620         LDSTCompUnit.__init__(self, pi, rwid, 4)
 621
 622     def elaborate(self, platform):
 623         m = LDSTCompUnit.elaborate(self, platform)
 624         m.submodules.l0 = self.l0
 625         m.d.comb += self.ad.go.eq(self.ad.rel) # link addr-go direct to rel
 626         return m
 627
 628
 629 def test_scoreboard():
 630
 631     dut = TestLDSTCompUnit(16)
 632     vl = rtlil.convert(dut, ports=dut.ports())
 633     with open("test_ldst_comp.il", "w") as f:
 634         f.write(vl)
 635
 636     run_simulation(dut, scoreboard_sim(dut), vcd_name='test_ldst_comp.vcd')
 637
 638
 639 if __name__ == '__main__':
 640     test_scoreboard()