1 """LOAD / STORE Computation Unit.
3 This module covers POWER9-compliant Load and Store operations,
4 with selection on each between immediate and indexed mode as
5 options for the calculation of the Effective Address (EA),
6 and also "update" mode which optionally stores that EA into
7 an additional register.
10 Note: it took 15 attempts over several weeks to redraw the diagram
11 needed to capture this FSM properly. To understand it fully, please
12 take the time to review the links, video, and diagram.
15 Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
16 compute the "Effective Address", and, when ready the operand (src3_i)
17 is stored in the computed address (passed through to the PortInterface)
19 Loads are activated when Go_Write[0] is enabled. The EA is computed,
20 and (as long as there was no exception) the data comes out (at any
21 time from the PortInterface), and is captured by the LDCompSTUnit.
23 Both LD and ST may request that the address be computed from summing
24 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
25 the immediate (from the opcode).
27 Both LD and ST may also request "update" mode (op_is_update) which
28 activates the use of Go_Write[1] to control storage of the EA into
29 a *second* operand in the register file.
31 Thus this module has *TWO* write-requests to the register file and
32 *THREE* read-requests to the register file (not all at the same time!)
33 The regfile port usage is:
45 It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
46 is not suited to (nmigen.FSM is clock-driven, and some aspects of
47 the nested FSMs below are *combinatorial*).
49 * One FSM covers Operand collection and communication address-side
50 with the LD/ST PortInterface. its role ends when "RD_DONE" is asserted
52 * A second FSM activates to cover LD. it activates if op_is_ld is true
54 * A third FSM activates to cover ST. it activates if op_is_st is true
56 * The "overall" (fourth) FSM coordinates the progression and completion
57 of the three other FSMs, firing "WR_RESET" which switches off "busy"
61 https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
63 Links including to walk-through videos:
65 * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
66 * http://libre-soc.org/openpower/isa/fixedload
67 * http://libre-soc.org/openpower/isa/fixedstore
71 * https://bugs.libre-soc.org/show_bug.cgi?id=302
72 * https://bugs.libre-soc.org/show_bug.cgi?id=216
76 * EA - Effective Address
81 from nmigen
.compat
.sim
import run_simulation
82 from nmigen
.cli
import verilog
, rtlil
83 from nmigen
import Module
, Signal
, Mux
, Cat
, Elaboratable
, Array
, Repl
84 from nmigen
.hdl
.rec
import Record
, Layout
86 from nmutil
.latch
import SRLatch
, latchregister
87 from nmutil
.byterev
import byte_reverse
88 from nmutil
.extend
import exts
90 from soc
.experiment
.compalu_multi
import go_record
, CompUnitRecord
91 from soc
.experiment
.l0_cache
import PortInterface
92 from soc
.experiment
.pimem
import LDSTException
93 from soc
.fu
.regspec
import RegSpecAPI
95 from openpower
.decoder
.power_enums
import MicrOp
, Function
, LDSTMode
96 from soc
.fu
.ldst
.ldst_input_record
import CompLDSTOpSubset
97 from openpower
.decoder
.power_decoder2
import Data
98 from openpower
.consts
import MSR
99 from soc
.config
.test
.test_loadstore
import TestMemPspec
102 from nmutil
.util
import Display
105 # TODO: LDSTInputData and LDSTOutputData really should be used
106 # here, to make things more like the other CompUnits. currently,
107 # also, RegSpecAPI is used explicitly here
110 class LDSTCompUnitRecord(CompUnitRecord
):
111 def __init__(self
, rwid
, opsubset
=CompLDSTOpSubset
, name
=None):
112 CompUnitRecord
.__init
__(self
, opsubset
, rwid
,
113 n_src
=3, n_dst
=2, name
=name
)
115 self
.ad
= go_record(1, name
="cu_ad") # address go in, req out
116 self
.st
= go_record(1, name
="cu_st") # store go in, req out
118 self
.exc_o
= LDSTException("exc_o")
120 self
.ld_o
= Signal(reset_less
=True) # operation is a LD
121 self
.st_o
= Signal(reset_less
=True) # operation is a ST
123 # hmm... are these necessary?
124 self
.load_mem_o
= Signal(reset_less
=True) # activate memory LOAD
125 self
.stwd_mem_o
= Signal(reset_less
=True) # activate memory STORE
128 class LDSTCompUnit(RegSpecAPI
, Elaboratable
):
129 """LOAD / STORE Computation Unit
134 * :pi: a PortInterface to the memory subsystem (read-write capable)
135 * :rwid: register width
136 * :awid: address width
140 * :src_i: Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
144 * :data_o: Dest out (LD) - managed by wr[0] go/req
145 * :addr_o: Address out (LD or ST) - managed by wr[1] go/req
146 * :exc_o: Address/Data Exception occurred. LD/ST must terminate
148 TODO: make exc_o a data-type rather than a single-bit signal
154 * :oper_i: operation being carried out (POWER9 decode LD/ST subset)
155 * :issue_i: LD/ST is being "issued".
156 * :shadown_i: Inverted-shadow is being held (stops STORE *and* WRITE)
157 * :go_rd_i: read is being actioned (latches in src regs)
158 * :go_wr_i: write mode (exactly like ALU CompUnit)
159 * :go_ad_i: address is being actioned (triggers actual mem LD)
160 * :go_st_i: store is being actioned (triggers actual mem STORE)
161 * :go_die_i: resets the unit back to "wait for issue"
163 Control Signals (Out)
164 ---------------------
166 * :busy_o: function unit is busy
167 * :rd_rel_o: request src1/src2
168 * :adr_rel_o: request address (from mem)
169 * :sto_rel_o: request store (to mem)
170 * :req_rel_o: request write (result)
171 * :load_mem_o: activate memory LOAD
172 * :stwd_mem_o: activate memory STORE
174 Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
175 in a single cycle and the CompUnit set back to doing another op.
176 This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
177 depending on whether the operation is a ST or LD.
179 Note: LDSTCompUnit takes care of LE/BE normalisation:
180 * LD data is normalised after receipt from the PortInterface
181 * ST data is normalised *prior* to sending onto the PortInterface
182 TODO: use one module for the byte-reverse as it's quite expensive in gates
185 def __init__(self
, pi
=None, rwid
=64, awid
=48, opsubset
=CompLDSTOpSubset
,
186 debugtest
=False, name
=None):
187 super().__init
__(rwid
)
190 self
.cu
= cu
= LDSTCompUnitRecord(rwid
, opsubset
, name
=name
)
191 self
.debugtest
= debugtest
193 # POWER-compliant LD/ST has index and update: *fixed* number of ports
194 self
.n_src
= n_src
= 3 # RA, RB, RT/RS
195 self
.n_dst
= n_dst
= 2 # RA, RT/RS
197 # set up array of src and dest signals
198 for i
in range(n_src
):
199 j
= i
+ 1 # name numbering to match src1/src2
201 setattr(self
, name
, getattr(cu
, name
))
204 for i
in range(n_dst
):
205 j
= i
+ 1 # name numbering to match dest1/2...
206 name
= "dest%d_o" % j
207 setattr(self
, name
, getattr(cu
, name
))
212 self
.rdmaskn
= cu
.rdmaskn
213 self
.wrmask
= cu
.wrmask
218 # HACK: get data width from dest[0]. this is used across the board
219 # (it really shouldn't be)
220 self
.data_wid
= self
.dest
[0].shape()
222 self
.go_rd_i
= self
.rd
.go_i
# temporary naming
223 self
.go_wr_i
= self
.wr
.go_i
# temporary naming
224 self
.go_ad_i
= self
.ad
.go_i
# temp naming: go address in
225 self
.go_st_i
= self
.st
.go_i
# temp naming: go store in
227 self
.rd_rel_o
= self
.rd
.rel_o
# temporary naming
228 self
.req_rel_o
= self
.wr
.rel_o
# temporary naming
229 self
.adr_rel_o
= self
.ad
.rel_o
# request address (from mem)
230 self
.sto_rel_o
= self
.st
.rel_o
# request store (to mem)
232 self
.issue_i
= cu
.issue_i
233 self
.shadown_i
= cu
.shadown_i
234 self
.go_die_i
= cu
.go_die_i
236 self
.oper_i
= cu
.oper_i
237 self
.src_i
= cu
._src
_i
239 self
.data_o
= Data(self
.data_wid
, name
="o") # Dest1 out: RT
240 self
.addr_o
= Data(self
.data_wid
, name
="ea") # Addr out: Update => RA
241 self
.exc_o
= cu
.exc_o
242 self
.done_o
= cu
.done_o
243 self
.busy_o
= cu
.busy_o
248 self
.load_mem_o
= cu
.load_mem_o
249 self
.stwd_mem_o
= cu
.stwd_mem_o
251 def elaborate(self
, platform
):
257 issue_i
= self
.issue_i
259 #####################
260 # latches for the FSM.
261 m
.submodules
.opc_l
= opc_l
= SRLatch(sync
=False, name
="opc")
262 m
.submodules
.src_l
= src_l
= SRLatch(False, self
.n_src
, name
="src")
263 m
.submodules
.alu_l
= alu_l
= SRLatch(sync
=False, name
="alu")
264 m
.submodules
.adr_l
= adr_l
= SRLatch(sync
=False, name
="adr")
265 m
.submodules
.lod_l
= lod_l
= SRLatch(sync
=False, name
="lod")
266 m
.submodules
.sto_l
= sto_l
= SRLatch(sync
=False, name
="sto")
267 m
.submodules
.wri_l
= wri_l
= SRLatch(sync
=False, name
="wri")
268 m
.submodules
.upd_l
= upd_l
= SRLatch(sync
=False, name
="upd")
269 m
.submodules
.rst_l
= rst_l
= SRLatch(sync
=False, name
="rst")
270 m
.submodules
.lsd_l
= lsd_l
= SRLatch(sync
=False, name
="lsd") # done
276 op_is_ld
= Signal(reset_less
=True)
277 op_is_st
= Signal(reset_less
=True)
279 # ALU/LD data output control
280 alu_valid
= Signal(reset_less
=True) # ALU operands are valid
281 alu_ok
= Signal(reset_less
=True) # ALU out ok (1 clock delay valid)
282 addr_ok
= Signal(reset_less
=True) # addr ok (from PortInterface)
283 ld_ok
= Signal(reset_less
=True) # LD out ok from PortInterface
284 wr_any
= Signal(reset_less
=True) # any write (incl. store)
285 rda_any
= Signal(reset_less
=True) # any read for address ops
286 rd_done
= Signal(reset_less
=True) # all *necessary* operands read
287 wr_reset
= Signal(reset_less
=True) # final reset condition
290 alu_o
= Signal(self
.data_wid
, reset_less
=True)
291 ldd_o
= Signal(self
.data_wid
, reset_less
=True)
293 ##############################
294 # reset conditions for latches
296 # temporaries (also convenient when debugging)
297 reset_o
= Signal(reset_less
=True) # reset opcode
298 reset_w
= Signal(reset_less
=True) # reset write
299 reset_u
= Signal(reset_less
=True) # reset update
300 reset_a
= Signal(reset_less
=True) # reset adr latch
301 reset_i
= Signal(reset_less
=True) # issue|die (use a lot)
302 reset_r
= Signal(self
.n_src
, reset_less
=True) # reset src
303 reset_s
= Signal(reset_less
=True) # reset store
305 # end execution when a terminating condition is detected:
306 # - go_die_i: a speculative operation was cancelled
307 # - exc_o.happened: an exception has occurred
309 comb
+= terminate
.eq(self
.go_die_i | self
.exc_o
.happened
)
311 comb
+= reset_i
.eq(issue_i | terminate
) # various
312 comb
+= reset_o
.eq(self
.done_o | terminate
) # opcode reset
313 comb
+= reset_w
.eq(self
.wr
.go_i
[0] | terminate
) # write reg 1
314 comb
+= reset_u
.eq(self
.wr
.go_i
[1] | terminate
) # update (reg 2)
315 comb
+= reset_s
.eq(self
.go_st_i | terminate
) # store reset
316 comb
+= reset_r
.eq(self
.rd
.go_i |
Repl(terminate
, self
.n_src
))
317 comb
+= reset_a
.eq(self
.go_ad_i | terminate
)
319 p_st_go
= Signal(reset_less
=True)
320 sync
+= p_st_go
.eq(self
.st
.go_i
)
322 # decode bits of operand (latched)
323 oper_r
= CompLDSTOpSubset(name
="oper_r") # Dest register
324 comb
+= op_is_st
.eq(oper_r
.insn_type
== MicrOp
.OP_STORE
) # ST
325 comb
+= op_is_ld
.eq(oper_r
.insn_type
== MicrOp
.OP_LOAD
) # LD
326 comb
+= Display("compldst_multi: op_is_dcbz = %i",
327 (oper_r
.insn_type
== MicrOp
.OP_DCBZ
))
328 op_is_update
= oper_r
.ldst_mode
== LDSTMode
.update
# UPDATE
329 op_is_cix
= oper_r
.ldst_mode
== LDSTMode
.cix
# cache-inhibit
330 comb
+= self
.load_mem_o
.eq(op_is_ld
& self
.go_ad_i
)
331 comb
+= self
.stwd_mem_o
.eq(op_is_st
& self
.go_st_i
)
332 comb
+= self
.ld_o
.eq(op_is_ld
)
333 comb
+= self
.st_o
.eq(op_is_st
)
335 ##########################
336 # FSM implemented through sequence of latches. approximately this:
338 # - src_l[0] : operands
340 # - alu_l : looks after add of src1/2/imm (EA)
341 # - adr_l : waits for add (EA)
342 # - upd_l : waits for adr and Regfile (port 2)
344 # - lod_l : waits for adr (EA) and for LD Data
345 # - wri_l : waits for LD Data and Regfile (port 1)
346 # - st_l : waits for alu and operand2
347 # - rst_l : waits for all FSM paths to converge.
348 # NOTE: use sync to stop combinatorial loops.
350 # opcode latch - inverted so that busy resets to 0
351 # note this MUST be sync so as to avoid a combinatorial loop
352 # between busy_o and issue_i on the reset latch (rst_l)
353 sync
+= opc_l
.s
.eq(issue_i
) # XXX NOTE: INVERTED FROM book!
354 sync
+= opc_l
.r
.eq(reset_o
) # XXX NOTE: INVERTED FROM book!
357 sync
+= src_l
.s
.eq(Repl(issue_i
, self
.n_src
))
358 sync
+= src_l
.r
.eq(reset_r
)
360 # alu latch. use sync-delay between alu_ok and valid to generate pulse
361 comb
+= alu_l
.s
.eq(reset_i
)
362 comb
+= alu_l
.r
.eq(alu_ok
& ~alu_valid
& ~rda_any
)
365 comb
+= adr_l
.s
.eq(reset_i
)
366 sync
+= adr_l
.r
.eq(reset_a
)
369 comb
+= lod_l
.s
.eq(reset_i
)
370 comb
+= lod_l
.r
.eq(ld_ok
)
373 comb
+= wri_l
.s
.eq(issue_i
)
374 sync
+= wri_l
.r
.eq(reset_w |
Repl(wr_reset |
375 (~self
.pi
.busy_o
& op_is_update
),
376 #(self.pi.busy_o & op_is_update),
377 #self.done_o | (self.pi.busy_o & op_is_update),
380 # update-mode operand latch (EA written to reg 2)
381 sync
+= upd_l
.s
.eq(reset_i
)
382 sync
+= upd_l
.r
.eq(reset_u
)
385 comb
+= sto_l
.s
.eq(addr_ok
& op_is_st
)
386 sync
+= sto_l
.r
.eq(reset_s | p_st_go
)
388 # ld/st done. needed to stop LD/ST from activating repeatedly
389 comb
+= lsd_l
.s
.eq(issue_i
)
390 sync
+= lsd_l
.r
.eq(reset_s | p_st_go | ld_ok
)
393 comb
+= rst_l
.s
.eq(addr_ok
) # start when address is ready
394 comb
+= rst_l
.r
.eq(issue_i
)
396 # create a latch/register for the operand
397 with m
.If(self
.issue_i
):
398 sync
+= oper_r
.eq(self
.oper_i
)
399 with m
.If(self
.done_o | terminate
):
403 ldd_r
= Signal(self
.data_wid
, reset_less
=True) # Dest register
404 latchregister(m
, ldd_o
, ldd_r
, ld_ok
, name
="ldo_r")
406 # and for each input from the incoming src operands
408 for i
in range(self
.n_src
):
410 src_r
= Signal(self
.data_wid
, name
=name
, reset_less
=True)
411 with m
.If(self
.rd
.go_i
[i
]):
412 sync
+= src_r
.eq(self
.src_i
[i
])
413 with m
.If(self
.issue_i
):
417 # and one for the output from the ADD (for the EA)
418 addr_r
= Signal(self
.data_wid
, reset_less
=True) # Effective Address
419 latchregister(m
, alu_o
, addr_r
, alu_l
.q
, "ea_r")
421 # select either zero or src1 if opcode says so
422 op_is_z
= oper_r
.zero_a
423 src1_or_z
= Signal(self
.data_wid
, reset_less
=True)
424 m
.d
.comb
+= src1_or_z
.eq(Mux(op_is_z
, 0, srl
[0]))
426 # select either immediate or src2 if opcode says so
427 op_is_imm
= oper_r
.imm_data
.ok
428 src2_or_imm
= Signal(self
.data_wid
, reset_less
=True)
429 m
.d
.comb
+= src2_or_imm
.eq(Mux(op_is_imm
, oper_r
.imm_data
.data
, srl
[1]))
431 # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
432 comb
+= alu_o
.eq(src1_or_z
+ src2_or_imm
) # actual EA
433 m
.d
.sync
+= alu_ok
.eq(alu_valid
) # keep ack in sync with EA
435 ############################
436 # Control Signal calculation
440 comb
+= self
.busy_o
.eq(opc_l
.q
) # | self.pi.busy_o) # busy out
442 # 1st operand read-request only when zero not active
443 # 2nd operand only needed when immediate is not active
444 slg
= Cat(op_is_z
, op_is_imm
)
445 bro
= Repl(self
.busy_o
, self
.n_src
)
446 comb
+= self
.rd
.rel_o
.eq(src_l
.q
& bro
& ~slg
& ~self
.rdmaskn
)
448 # note when the address-related read "go" signals are active
449 comb
+= rda_any
.eq(self
.rd
.go_i
[0] | self
.rd
.go_i
[1])
451 # alu input valid when 1st and 2nd ops done (or imm not active)
452 comb
+= alu_valid
.eq(busy_o
& ~
(self
.rd
.rel_o
[0] | self
.rd
.rel_o
[1]))
454 # 3rd operand only needed when operation is a store
455 comb
+= self
.rd
.rel_o
[2].eq(src_l
.q
[2] & busy_o
& op_is_st
)
457 # all reads done when alu is valid and 3rd operand needed
458 comb
+= rd_done
.eq(alu_valid
& ~self
.rd
.rel_o
[2])
460 # address release only if addr ready, but Port must be idle
461 comb
+= self
.adr_rel_o
.eq(alu_valid
& adr_l
.q
& busy_o
)
463 # the write/store (etc) all must be cancelled if an exception occurs
464 # note: cancel is active low, like shadown_i,
465 # while exc_o.happpened is active high
466 cancel
= Signal(reset_less
=True)
467 comb
+= cancel
.eq(~self
.exc_o
.happened
& self
.shadown_i
)
469 # store release when st ready *and* all operands read (and no shadow)
470 comb
+= self
.st
.rel_o
.eq(sto_l
.q
& busy_o
& rd_done
& op_is_st
&
473 # request write of LD result. waits until shadow is dropped.
474 comb
+= self
.wr
.rel_o
[0].eq(rd_done
& wri_l
.q
& busy_o
& lod_l
.qn
&
477 # request write of EA result only in update mode
478 comb
+= self
.wr
.rel_o
[1].eq(upd_l
.q
& busy_o
& op_is_update
&
481 # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
482 comb
+= wr_any
.eq(self
.st
.go_i | p_st_go |
483 self
.wr
.go_i
[0] | self
.wr
.go_i
[1])
484 comb
+= wr_reset
.eq(rst_l
.q
& busy_o
& cancel
&
485 ~
(self
.st
.rel_o | self
.wr
.rel_o
[0] |
487 (lod_l
.qn | op_is_st
)
489 comb
+= self
.done_o
.eq(wr_reset
& (~self
.pi
.busy_o | op_is_ld
))
491 ######################
492 # Data/Address outputs
494 # put the LD-output register directly onto the output bus on a go_write
495 comb
+= self
.data_o
.data
.eq(self
.dest
[0])
496 with m
.If(self
.wr
.go_i
[0]):
497 comb
+= self
.dest
[0].eq(ldd_r
)
499 # "update" mode, put address out on 2nd go-write
500 comb
+= self
.addr_o
.data
.eq(self
.dest
[1])
501 with m
.If(op_is_update
& self
.wr
.go_i
[1]):
502 comb
+= self
.dest
[1].eq(addr_r
)
504 # need to look like MultiCompUnit: put wrmask out.
505 # XXX may need to make this enable only when write active
506 comb
+= self
.wrmask
.eq(bro
& Cat(op_is_ld
, op_is_update
))
508 ###########################
509 # PortInterface connections
512 # connect to LD/ST PortInterface.
513 comb
+= pi
.is_ld_i
.eq(op_is_ld
& busy_o
) # decoded-LD
514 comb
+= pi
.is_st_i
.eq(op_is_st
& busy_o
) # decoded-ST
515 comb
+= pi
.data_len
.eq(oper_r
.data_len
) # data_len
516 # address: use sync to avoid long latency
517 sync
+= pi
.addr
.data
.eq(addr_r
) # EA from adder
518 sync
+= pi
.addr
.ok
.eq(alu_ok
& lsd_l
.q
) # "do address stuff" (once)
519 comb
+= self
.exc_o
.eq(pi
.exc_o
) # exception occurred
520 comb
+= addr_ok
.eq(self
.pi
.addr_ok_o
) # no exc, address fine
521 # connect MSR.PR for priv/virt operation
522 comb
+= pi
.msr_pr
.eq(oper_r
.msr
[MSR
.PR
])
525 revnorev
= Signal(64, reset_less
=True)
526 with m
.If(oper_r
.byte_reverse
):
527 # byte-reverse the data based on ld/st width (turn it to LE)
528 data_len
= oper_r
.data_len
529 lddata_r
= byte_reverse(m
, 'lddata_r', pi
.ld
.data
, data_len
)
530 comb
+= revnorev
.eq(lddata_r
) # put reversed- data out
532 comb
+= revnorev
.eq(pi
.ld
.data
) # put data out, straight (as BE)
534 # then check sign-extend
535 with m
.If(oper_r
.sign_extend
):
536 # okok really should "if data_len == 4" and so on here
537 with m
.If(oper_r
.data_len
== 2):
538 comb
+= ldd_o
.eq(exts(revnorev
, 16, 64)) # sign-extend hword
540 comb
+= ldd_o
.eq(exts(revnorev
, 32, 64)) # sign-extend dword
542 comb
+= ldd_o
.eq(revnorev
)
544 # ld - ld gets latched in via lod_l
545 comb
+= ld_ok
.eq(pi
.ld
.ok
) # ld.ok *closes* (freezes) ld data
548 op3
= srl
[2] # 3rd operand latch
549 with m
.If(oper_r
.byte_reverse
):
550 # byte-reverse the data based on width
551 data_len
= oper_r
.data_len
552 stdata_r
= byte_reverse(m
, 'stdata_r', op3
, data_len
)
553 comb
+= pi
.st
.data
.eq(stdata_r
)
555 comb
+= pi
.st
.data
.eq(op3
)
556 # store - data goes in based on go_st
557 comb
+= pi
.st
.ok
.eq(self
.st
.go_i
) # go store signals st data valid
561 def get_out(self
, i
):
562 """make LDSTCompUnit look like RegSpecALUAPI. these correspond
563 to LDSTOutputData o and o1 respectively.
566 return self
.data_o
# LDSTOutputData.regspec o
568 return self
.addr_o
# LDSTOutputData.regspec o1
569 # return self.dest[i]
571 def get_fu_out(self
, i
):
572 return self
.get_out(i
)
582 yield from self
.oper_i
.ports()
583 yield from self
.src_i
589 yield from self
.data_o
.ports()
590 yield from self
.addr_o
.ports()
591 yield self
.load_mem_o
592 yield self
.stwd_mem_o
598 def wait_for(sig
, wait
=True, test1st
=False):
600 print("wait for", sig
, v
, wait
, test1st
)
601 if test1st
and bool(v
) == wait
:
606 #print("...wait for", sig, v)
611 def store(dut
, src1
, src2
, src3
, imm
, imm_ok
=True, update
=False,
613 print("ST", src1
, src2
, src3
, imm
, imm_ok
, update
)
614 yield dut
.oper_i
.insn_type
.eq(MicrOp
.OP_STORE
)
615 yield dut
.oper_i
.data_len
.eq(2) # half-word
616 yield dut
.oper_i
.byte_reverse
.eq(byterev
)
617 yield dut
.src1_i
.eq(src1
)
618 yield dut
.src2_i
.eq(src2
)
619 yield dut
.src3_i
.eq(src3
)
620 yield dut
.oper_i
.imm_data
.data
.eq(imm
)
621 yield dut
.oper_i
.imm_data
.ok
.eq(imm_ok
)
622 #guess: this one was removed -- yield dut.oper_i.update.eq(update)
623 yield dut
.issue_i
.eq(1)
625 yield dut
.issue_i
.eq(0)
631 # wait for all active rel signals to come up
633 rel
= yield dut
.rd
.rel_o
634 if rel
== active_rel
:
637 yield dut
.rd
.go_i
.eq(active_rel
)
639 yield dut
.rd
.go_i
.eq(0)
641 yield from wait_for(dut
.adr_rel_o
, False, test1st
=True)
642 # yield from wait_for(dut.adr_rel_o)
643 # yield dut.ad.go.eq(1)
645 # yield dut.ad.go.eq(0)
648 yield from wait_for(dut
.wr
.rel_o
[1])
649 yield dut
.wr
.go
.eq(0b10)
651 addr
= yield dut
.addr_o
653 yield dut
.wr
.go
.eq(0)
657 yield from wait_for(dut
.sto_rel_o
)
658 yield dut
.go_st_i
.eq(1)
660 yield dut
.go_st_i
.eq(0)
661 yield from wait_for(dut
.busy_o
, False)
662 # wait_for(dut.stwd_mem_o)
667 def load(dut
, src1
, src2
, imm
, imm_ok
=True, update
=False, zero_a
=False,
669 print("LD", src1
, src2
, imm
, imm_ok
, update
)
670 yield dut
.oper_i
.insn_type
.eq(MicrOp
.OP_LOAD
)
671 yield dut
.oper_i
.data_len
.eq(2) # half-word
672 yield dut
.oper_i
.byte_reverse
.eq(byterev
)
673 yield dut
.src1_i
.eq(src1
)
674 yield dut
.src2_i
.eq(src2
)
675 yield dut
.oper_i
.zero_a
.eq(zero_a
)
676 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
677 yield dut
.oper_i
.imm_data
.ok
.eq(imm_ok
)
678 yield dut
.issue_i
.eq(1)
680 yield dut
.issue_i
.eq(0)
683 # set up read-operand flags
685 if not imm_ok
: # no immediate means RB register needs to be read
687 if not zero_a
: # no zero-a means RA needs to be read
690 # wait for the operands (RA, RB, or both)
692 yield dut
.rd
.go
.eq(rd
)
693 yield from wait_for(dut
.rd
.rel_o
)
694 yield dut
.rd
.go
.eq(0)
696 yield from wait_for(dut
.adr_rel_o
, False, test1st
=True)
697 # yield dut.ad.go.eq(1)
699 # yield dut.ad.go.eq(0)
702 yield from wait_for(dut
.wr
.rel_o
[1])
703 yield dut
.wr
.go
.eq(0b10)
705 addr
= yield dut
.addr_o
707 yield dut
.wr
.go
.eq(0)
711 yield from wait_for(dut
.wr
.rel_o
[0], test1st
=True)
712 yield dut
.wr
.go
.eq(1)
714 data
= yield dut
.data_o
716 yield dut
.wr
.go
.eq(0)
717 yield from wait_for(dut
.busy_o
)
719 # wait_for(dut.stwd_mem_o)
728 # two STs (different addresses)
729 yield from store(dut
, 4, 0, 3, 2) # ST reg4 into addr rfile[reg3]+2
730 yield from store(dut
, 2, 0, 9, 2) # ST reg4 into addr rfile[reg9]+2
732 # two LDs (deliberately LD from the 1st address then 2nd)
733 data
, addr
= yield from load(dut
, 4, 0, 2)
734 assert data
== 0x0003, "returned %x" % data
735 data
, addr
= yield from load(dut
, 2, 0, 2)
736 assert data
== 0x0009, "returned %x" % data
740 yield from store(dut
, 9, 5, 3, 0, imm_ok
=False)
741 data
, addr
= yield from load(dut
, 9, 5, 0, imm_ok
=False)
742 assert data
== 0x0003, "returned %x" % data
744 # update-immediate version
745 addr
= yield from store(dut
, 9, 6, 3, 2, update
=True)
746 assert addr
== 0x000b, "returned %x" % addr
748 # update-indexed version
749 data
, addr
= yield from load(dut
, 9, 5, 0, imm_ok
=False, update
=True)
750 assert data
== 0x0003, "returned %x" % data
751 assert addr
== 0x000e, "returned %x" % addr
753 # immediate *and* zero version
754 data
, addr
= yield from load(dut
, 1, 4, 8, imm_ok
=True, zero_a
=True)
755 assert data
== 0x0008, "returned %x" % data
758 class TestLDSTCompUnit(LDSTCompUnit
):
760 def __init__(self
, rwid
, pspec
):
761 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
762 self
.l0
= l0
= TstL0CacheBuffer(pspec
)
764 LDSTCompUnit
.__init
__(self
, pi
, rwid
, 4)
766 def elaborate(self
, platform
):
767 m
= LDSTCompUnit
.elaborate(self
, platform
)
768 m
.submodules
.l0
= self
.l0
769 m
.d
.comb
+= self
.ad
.go
.eq(self
.ad
.rel
) # link addr-go direct to rel
773 def test_scoreboard():
776 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
777 imem_ifacetype
='bare_wb',
783 dut
= TestLDSTCompUnit(16,pspec
)
784 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
785 with
open("test_ldst_comp.il", "w") as f
:
788 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_comp.vcd')
791 class TestLDSTCompUnitRegSpec(LDSTCompUnit
):
793 def __init__(self
, pspec
):
794 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
795 from soc
.fu
.ldst
.pipe_data
import LDSTPipeSpec
796 regspec
= LDSTPipeSpec
.regspec
797 self
.l0
= l0
= TstL0CacheBuffer(pspec
)
799 LDSTCompUnit
.__init
__(self
, pi
, regspec
, 4)
801 def elaborate(self
, platform
):
802 m
= LDSTCompUnit
.elaborate(self
, platform
)
803 m
.submodules
.l0
= self
.l0
804 # link addr-go direct to rel
805 m
.d
.comb
+= self
.ad
.go_i
.eq(self
.ad
.rel_o
)
809 def test_scoreboard_regspec():
812 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
813 imem_ifacetype
='bare_wb',
819 dut
= TestLDSTCompUnitRegSpec(pspec
)
820 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
821 with
open("test_ldst_comp.il", "w") as f
:
824 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_regspec.vcd')
827 if __name__
== '__main__':
828 test_scoreboard_regspec()