1 """LOAD / STORE Computation Unit.
3 This module covers POWER9-compliant Load and Store operations,
4 with selection on each between immediate and indexed mode as
5 options for the calculation of the Effective Address (EA),
6 and also "update" mode which optionally stores that EA into
7 an additional register.
10 Note: it took 15 attempts over several weeks to redraw the diagram
11 needed to capture this FSM properly. To understand it fully, please
12 take the time to review the links, video, and diagram.
15 Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
16 compute the "Effective Address", and, when ready the operand (src3_i)
17 is stored in the computed address (passed through to the PortInterface)
19 Loads are activated when Go_Write[0] is enabled. The EA is computed,
20 and (as long as there was no exception) the data comes out (at any
21 time from the PortInterface), and is captured by the LDCompSTUnit.
23 Both LD and ST may request that the address be computed from summing
24 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
25 the immediate (from the opcode).
27 Both LD and ST may also request "update" mode (op_is_update) which
28 activates the use of Go_Write[1] to control storage of the EA into
29 a *second* operand in the register file.
31 Thus this module has *TWO* write-requests to the register file and
32 *THREE* read-requests to the register file (not all at the same time!)
33 The regfile port usage is:
45 It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
46 is not suited to (nmigen.FSM is clock-driven, and some aspects of
47 the nested FSMs below are *combinatorial*).
49 * One FSM covers Operand collection and communication address-side
50 with the LD/ST PortInterface. its role ends when "RD_DONE" is asserted
52 * A second FSM activates to cover LD. it activates if op_is_ld is true
54 * A third FSM activates to cover ST. it activates if op_is_st is true
56 * The "overall" (fourth) FSM coordinates the progression and completion
57 of the three other FSMs, firing "WR_RESET" which switches off "busy"
61 https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
63 Links including to walk-through videos:
65 * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
66 * http://libre-soc.org/openpower/isa/fixedload
67 * http://libre-soc.org/openpower/isa/fixedstore
71 * https://bugs.libre-soc.org/show_bug.cgi?id=302
72 * https://bugs.libre-soc.org/show_bug.cgi?id=216
76 * EA - Effective Address
81 from nmigen
.compat
.sim
import run_simulation
82 from nmigen
.cli
import verilog
, rtlil
83 from nmigen
import Module
, Signal
, Mux
, Cat
, Elaboratable
, Array
, Repl
84 from nmigen
.hdl
.rec
import Record
, Layout
86 from nmutil
.latch
import SRLatch
, latchregister
87 from nmutil
.byterev
import byte_reverse
88 from nmutil
.extend
import exts
90 from soc
.experiment
.compalu_multi
import go_record
, CompUnitRecord
91 from soc
.experiment
.l0_cache
import PortInterface
92 from soc
.experiment
.pimem
import LDSTException
93 from soc
.fu
.regspec
import RegSpecAPI
95 from openpower
.decoder
.power_enums
import MicrOp
, Function
, LDSTMode
96 from soc
.fu
.ldst
.ldst_input_record
import CompLDSTOpSubset
97 from openpower
.decoder
.power_decoder2
import Data
100 class LDSTCompUnitRecord(CompUnitRecord
):
101 def __init__(self
, rwid
, opsubset
=CompLDSTOpSubset
, name
=None):
102 CompUnitRecord
.__init
__(self
, opsubset
, rwid
,
103 n_src
=3, n_dst
=2, name
=name
)
105 self
.ad
= go_record(1, name
="cu_ad") # address go in, req out
106 self
.st
= go_record(1, name
="cu_st") # store go in, req out
108 self
.exception_o
= LDSTException("exc_o")
110 self
.ld_o
= Signal(reset_less
=True) # operation is a LD
111 self
.st_o
= Signal(reset_less
=True) # operation is a ST
113 # hmm... are these necessary?
114 self
.load_mem_o
= Signal(reset_less
=True) # activate memory LOAD
115 self
.stwd_mem_o
= Signal(reset_less
=True) # activate memory STORE
118 class LDSTCompUnit(RegSpecAPI
, Elaboratable
):
119 """LOAD / STORE Computation Unit
124 * :pi: a PortInterface to the memory subsystem (read-write capable)
125 * :rwid: register width
126 * :awid: address width
130 * :src_i: Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
134 * :data_o: Dest out (LD) - managed by wr[0] go/req
135 * :addr_o: Address out (LD or ST) - managed by wr[1] go/req
136 * :exception_o: Address/Data Exception occurred. LD/ST must terminate
138 TODO: make exception_o a data-type rather than a single-bit signal
144 * :oper_i: operation being carried out (POWER9 decode LD/ST subset)
145 * :issue_i: LD/ST is being "issued".
146 * :shadown_i: Inverted-shadow is being held (stops STORE *and* WRITE)
147 * :go_rd_i: read is being actioned (latches in src regs)
148 * :go_wr_i: write mode (exactly like ALU CompUnit)
149 * :go_ad_i: address is being actioned (triggers actual mem LD)
150 * :go_st_i: store is being actioned (triggers actual mem STORE)
151 * :go_die_i: resets the unit back to "wait for issue"
153 Control Signals (Out)
154 ---------------------
156 * :busy_o: function unit is busy
157 * :rd_rel_o: request src1/src2
158 * :adr_rel_o: request address (from mem)
159 * :sto_rel_o: request store (to mem)
160 * :req_rel_o: request write (result)
161 * :load_mem_o: activate memory LOAD
162 * :stwd_mem_o: activate memory STORE
164 Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
165 in a single cycle and the CompUnit set back to doing another op.
166 This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
167 depending on whether the operation is a ST or LD.
169 Note: LDSTCompUnit takes care of LE/BE normalisation:
170 * LD data is normalised after receipt from the PortInterface
171 * ST data is normalised *prior* to sending onto the PortInterface
172 TODO: use one module for the byte-reverse as it's quite expensive in gates
175 def __init__(self
, pi
=None, rwid
=64, awid
=48, opsubset
=CompLDSTOpSubset
,
176 debugtest
=False, name
=None):
177 super().__init
__(rwid
)
180 self
.cu
= cu
= LDSTCompUnitRecord(rwid
, opsubset
, name
=name
)
181 self
.debugtest
= debugtest
183 # POWER-compliant LD/ST has index and update: *fixed* number of ports
184 self
.n_src
= n_src
= 3 # RA, RB, RT/RS
185 self
.n_dst
= n_dst
= 2 # RA, RT/RS
187 # set up array of src and dest signals
188 for i
in range(n_src
):
189 j
= i
+ 1 # name numbering to match src1/src2
191 setattr(self
, name
, getattr(cu
, name
))
194 for i
in range(n_dst
):
195 j
= i
+ 1 # name numbering to match dest1/2...
196 name
= "dest%d_o" % j
197 setattr(self
, name
, getattr(cu
, name
))
202 self
.rdmaskn
= cu
.rdmaskn
203 self
.wrmask
= cu
.wrmask
208 # HACK: get data width from dest[0]. this is used across the board
209 # (it really shouldn't be)
210 self
.data_wid
= self
.dest
[0].shape()
212 self
.go_rd_i
= self
.rd
.go_i
# temporary naming
213 self
.go_wr_i
= self
.wr
.go_i
# temporary naming
214 self
.go_ad_i
= self
.ad
.go_i
# temp naming: go address in
215 self
.go_st_i
= self
.st
.go_i
# temp naming: go store in
217 self
.rd_rel_o
= self
.rd
.rel_o
# temporary naming
218 self
.req_rel_o
= self
.wr
.rel_o
# temporary naming
219 self
.adr_rel_o
= self
.ad
.rel_o
# request address (from mem)
220 self
.sto_rel_o
= self
.st
.rel_o
# request store (to mem)
222 self
.issue_i
= cu
.issue_i
223 self
.shadown_i
= cu
.shadown_i
224 self
.go_die_i
= cu
.go_die_i
226 self
.oper_i
= cu
.oper_i
227 self
.src_i
= cu
._src
_i
229 self
.data_o
= Data(self
.data_wid
, name
="o") # Dest1 out: RT
230 self
.addr_o
= Data(self
.data_wid
, name
="ea") # Addr out: Update => RA
231 self
.exception_o
= cu
.exception_o
232 self
.done_o
= cu
.done_o
233 self
.busy_o
= cu
.busy_o
238 self
.load_mem_o
= cu
.load_mem_o
239 self
.stwd_mem_o
= cu
.stwd_mem_o
241 def elaborate(self
, platform
):
247 issue_i
= self
.issue_i
249 #####################
250 # latches for the FSM.
251 m
.submodules
.opc_l
= opc_l
= SRLatch(sync
=False, name
="opc")
252 m
.submodules
.src_l
= src_l
= SRLatch(False, self
.n_src
, name
="src")
253 m
.submodules
.alu_l
= alu_l
= SRLatch(sync
=False, name
="alu")
254 m
.submodules
.adr_l
= adr_l
= SRLatch(sync
=False, name
="adr")
255 m
.submodules
.lod_l
= lod_l
= SRLatch(sync
=False, name
="lod")
256 m
.submodules
.sto_l
= sto_l
= SRLatch(sync
=False, name
="sto")
257 m
.submodules
.wri_l
= wri_l
= SRLatch(sync
=False, name
="wri")
258 m
.submodules
.upd_l
= upd_l
= SRLatch(sync
=False, name
="upd")
259 m
.submodules
.rst_l
= rst_l
= SRLatch(sync
=False, name
="rst")
260 m
.submodules
.lsd_l
= lsd_l
= SRLatch(sync
=False, name
="lsd") # done
266 op_is_ld
= Signal(reset_less
=True)
267 op_is_st
= Signal(reset_less
=True)
269 # ALU/LD data output control
270 alu_valid
= Signal(reset_less
=True) # ALU operands are valid
271 alu_ok
= Signal(reset_less
=True) # ALU out ok (1 clock delay valid)
272 addr_ok
= Signal(reset_less
=True) # addr ok (from PortInterface)
273 ld_ok
= Signal(reset_less
=True) # LD out ok from PortInterface
274 wr_any
= Signal(reset_less
=True) # any write (incl. store)
275 rda_any
= Signal(reset_less
=True) # any read for address ops
276 rd_done
= Signal(reset_less
=True) # all *necessary* operands read
277 wr_reset
= Signal(reset_less
=True) # final reset condition
280 alu_o
= Signal(self
.data_wid
, reset_less
=True)
281 ldd_o
= Signal(self
.data_wid
, reset_less
=True)
283 ##############################
284 # reset conditions for latches
286 # temporaries (also convenient when debugging)
287 reset_o
= Signal(reset_less
=True) # reset opcode
288 reset_w
= Signal(reset_less
=True) # reset write
289 reset_u
= Signal(reset_less
=True) # reset update
290 reset_a
= Signal(reset_less
=True) # reset adr latch
291 reset_i
= Signal(reset_less
=True) # issue|die (use a lot)
292 reset_r
= Signal(self
.n_src
, reset_less
=True) # reset src
293 reset_s
= Signal(reset_less
=True) # reset store
295 comb
+= reset_i
.eq(issue_i | self
.go_die_i
) # various
296 comb
+= reset_o
.eq(self
.done_o | self
.go_die_i
) # opcode reset
297 comb
+= reset_w
.eq(self
.wr
.go_i
[0] | self
.go_die_i
) # write reg 1
298 comb
+= reset_u
.eq(self
.wr
.go_i
[1] | self
.go_die_i
) # update (reg 2)
299 comb
+= reset_s
.eq(self
.go_st_i | self
.go_die_i
) # store reset
300 comb
+= reset_r
.eq(self
.rd
.go_i |
Repl(self
.go_die_i
, self
.n_src
))
301 comb
+= reset_a
.eq(self
.go_ad_i | self
.go_die_i
)
303 p_st_go
= Signal(reset_less
=True)
304 sync
+= p_st_go
.eq(self
.st
.go_i
)
306 # decode bits of operand (latched)
307 oper_r
= CompLDSTOpSubset(name
="oper_r") # Dest register
308 comb
+= op_is_st
.eq(oper_r
.insn_type
== MicrOp
.OP_STORE
) # ST
309 comb
+= op_is_ld
.eq(oper_r
.insn_type
== MicrOp
.OP_LOAD
) # LD
310 op_is_update
= oper_r
.ldst_mode
== LDSTMode
.update
# UPDATE
311 op_is_cix
= oper_r
.ldst_mode
== LDSTMode
.cix
# cache-inhibit
312 comb
+= self
.load_mem_o
.eq(op_is_ld
& self
.go_ad_i
)
313 comb
+= self
.stwd_mem_o
.eq(op_is_st
& self
.go_st_i
)
314 comb
+= self
.ld_o
.eq(op_is_ld
)
315 comb
+= self
.st_o
.eq(op_is_st
)
317 ##########################
318 # FSM implemented through sequence of latches. approximately this:
320 # - src_l[0] : operands
322 # - alu_l : looks after add of src1/2/imm (EA)
323 # - adr_l : waits for add (EA)
324 # - upd_l : waits for adr and Regfile (port 2)
326 # - lod_l : waits for adr (EA) and for LD Data
327 # - wri_l : waits for LD Data and Regfile (port 1)
328 # - st_l : waits for alu and operand2
329 # - rst_l : waits for all FSM paths to converge.
330 # NOTE: use sync to stop combinatorial loops.
332 # opcode latch - inverted so that busy resets to 0
333 # note this MUST be sync so as to avoid a combinatorial loop
334 # between busy_o and issue_i on the reset latch (rst_l)
335 sync
+= opc_l
.s
.eq(issue_i
) # XXX NOTE: INVERTED FROM book!
336 sync
+= opc_l
.r
.eq(reset_o
) # XXX NOTE: INVERTED FROM book!
339 sync
+= src_l
.s
.eq(Repl(issue_i
, self
.n_src
))
340 sync
+= src_l
.r
.eq(reset_r
)
342 # alu latch. use sync-delay between alu_ok and valid to generate pulse
343 comb
+= alu_l
.s
.eq(reset_i
)
344 comb
+= alu_l
.r
.eq(alu_ok
& ~alu_valid
& ~rda_any
)
347 comb
+= adr_l
.s
.eq(reset_i
)
348 sync
+= adr_l
.r
.eq(reset_a
)
351 comb
+= lod_l
.s
.eq(reset_i
)
352 comb
+= lod_l
.r
.eq(ld_ok
)
355 comb
+= wri_l
.s
.eq(issue_i
)
356 sync
+= wri_l
.r
.eq(reset_w |
Repl(wr_reset |
357 (~self
.pi
.busy_o
& op_is_update
),
358 #(self.pi.busy_o & op_is_update),
359 #self.done_o | (self.pi.busy_o & op_is_update),
362 # update-mode operand latch (EA written to reg 2)
363 sync
+= upd_l
.s
.eq(reset_i
)
364 sync
+= upd_l
.r
.eq(reset_u
)
367 comb
+= sto_l
.s
.eq(addr_ok
& op_is_st
)
368 sync
+= sto_l
.r
.eq(reset_s | p_st_go
)
370 # ld/st done. needed to stop LD/ST from activating repeatedly
371 comb
+= lsd_l
.s
.eq(issue_i
)
372 sync
+= lsd_l
.r
.eq(reset_s | p_st_go | ld_ok
)
375 comb
+= rst_l
.s
.eq(addr_ok
) # start when address is ready
376 comb
+= rst_l
.r
.eq(issue_i
)
378 # create a latch/register for the operand
379 with m
.If(self
.issue_i
):
380 sync
+= oper_r
.eq(self
.oper_i
)
381 with m
.If(self
.done_o
):
385 ldd_r
= Signal(self
.data_wid
, reset_less
=True) # Dest register
386 latchregister(m
, ldd_o
, ldd_r
, ld_ok
, name
="ldo_r")
388 # and for each input from the incoming src operands
390 for i
in range(self
.n_src
):
392 src_r
= Signal(self
.data_wid
, name
=name
, reset_less
=True)
393 with m
.If(self
.rd
.go_i
[i
]):
394 sync
+= src_r
.eq(self
.src_i
[i
])
395 with m
.If(self
.issue_i
):
399 # and one for the output from the ADD (for the EA)
400 addr_r
= Signal(self
.data_wid
, reset_less
=True) # Effective Address
401 latchregister(m
, alu_o
, addr_r
, alu_l
.q
, "ea_r")
403 # select either zero or src1 if opcode says so
404 op_is_z
= oper_r
.zero_a
405 src1_or_z
= Signal(self
.data_wid
, reset_less
=True)
406 m
.d
.comb
+= src1_or_z
.eq(Mux(op_is_z
, 0, srl
[0]))
408 # select either immediate or src2 if opcode says so
409 op_is_imm
= oper_r
.imm_data
.ok
410 src2_or_imm
= Signal(self
.data_wid
, reset_less
=True)
411 m
.d
.comb
+= src2_or_imm
.eq(Mux(op_is_imm
, oper_r
.imm_data
.data
, srl
[1]))
413 # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
414 comb
+= alu_o
.eq(src1_or_z
+ src2_or_imm
) # actual EA
415 m
.d
.sync
+= alu_ok
.eq(alu_valid
) # keep ack in sync with EA
417 ############################
418 # Control Signal calculation
422 comb
+= self
.busy_o
.eq(opc_l
.q
) # | self.pi.busy_o) # busy out
424 # 1st operand read-request only when zero not active
425 # 2nd operand only needed when immediate is not active
426 slg
= Cat(op_is_z
, op_is_imm
)
427 bro
= Repl(self
.busy_o
, self
.n_src
)
428 comb
+= self
.rd
.rel_o
.eq(src_l
.q
& bro
& ~slg
& ~self
.rdmaskn
)
430 # note when the address-related read "go" signals are active
431 comb
+= rda_any
.eq(self
.rd
.go_i
[0] | self
.rd
.go_i
[1])
433 # alu input valid when 1st and 2nd ops done (or imm not active)
434 comb
+= alu_valid
.eq(busy_o
& ~
(self
.rd
.rel_o
[0] | self
.rd
.rel_o
[1]))
436 # 3rd operand only needed when operation is a store
437 comb
+= self
.rd
.rel_o
[2].eq(src_l
.q
[2] & busy_o
& op_is_st
)
439 # all reads done when alu is valid and 3rd operand needed
440 comb
+= rd_done
.eq(alu_valid
& ~self
.rd
.rel_o
[2])
442 # address release only if addr ready, but Port must be idle
443 comb
+= self
.adr_rel_o
.eq(alu_valid
& adr_l
.q
& busy_o
)
445 # store release when st ready *and* all operands read (and no shadow)
446 comb
+= self
.st
.rel_o
.eq(sto_l
.q
& busy_o
& rd_done
& op_is_st
&
449 # request write of LD result. waits until shadow is dropped.
450 comb
+= self
.wr
.rel_o
[0].eq(rd_done
& wri_l
.q
& busy_o
& lod_l
.qn
&
451 op_is_ld
& self
.shadown_i
)
453 # request write of EA result only in update mode
454 comb
+= self
.wr
.rel_o
[1].eq(upd_l
.q
& busy_o
& op_is_update
&
455 alu_valid
& self
.shadown_i
)
457 # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
458 comb
+= wr_any
.eq(self
.st
.go_i | p_st_go |
459 self
.wr
.go_i
[0] | self
.wr
.go_i
[1])
460 comb
+= wr_reset
.eq(rst_l
.q
& busy_o
& self
.shadown_i
&
461 ~
(self
.st
.rel_o | self
.wr
.rel_o
[0] |
463 (lod_l
.qn | op_is_st
)
465 comb
+= self
.done_o
.eq(wr_reset
& (~self
.pi
.busy_o | op_is_ld
))
467 ######################
468 # Data/Address outputs
470 # put the LD-output register directly onto the output bus on a go_write
471 comb
+= self
.data_o
.data
.eq(self
.dest
[0])
472 with m
.If(self
.wr
.go_i
[0]):
473 comb
+= self
.dest
[0].eq(ldd_r
)
475 # "update" mode, put address out on 2nd go-write
476 comb
+= self
.addr_o
.data
.eq(self
.dest
[1])
477 with m
.If(op_is_update
& self
.wr
.go_i
[1]):
478 comb
+= self
.dest
[1].eq(addr_r
)
480 # need to look like MultiCompUnit: put wrmask out.
481 # XXX may need to make this enable only when write active
482 comb
+= self
.wrmask
.eq(bro
& Cat(op_is_ld
, op_is_update
))
484 ###########################
485 # PortInterface connections
488 # connect to LD/ST PortInterface.
489 comb
+= pi
.is_ld_i
.eq(op_is_ld
& busy_o
) # decoded-LD
490 comb
+= pi
.is_st_i
.eq(op_is_st
& busy_o
) # decoded-ST
491 comb
+= pi
.data_len
.eq(oper_r
.data_len
) # data_len
492 # address: use sync to avoid long latency
493 sync
+= pi
.addr
.data
.eq(addr_r
) # EA from adder
494 sync
+= pi
.addr
.ok
.eq(alu_ok
& lsd_l
.q
) # "do address stuff" (once)
495 comb
+= self
.exception_o
.eq(pi
.exception_o
) # exception occurred
496 comb
+= addr_ok
.eq(self
.pi
.addr_ok_o
) # no exc, address fine
499 revnorev
= Signal(64, reset_less
=True)
500 with m
.If(oper_r
.byte_reverse
):
501 # byte-reverse the data based on ld/st width (turn it to LE)
502 data_len
= oper_r
.data_len
503 lddata_r
= byte_reverse(m
, 'lddata_r', pi
.ld
.data
, data_len
)
504 comb
+= revnorev
.eq(lddata_r
) # put reversed- data out
506 comb
+= revnorev
.eq(pi
.ld
.data
) # put data out, straight (as BE)
508 # then check sign-extend
509 with m
.If(oper_r
.sign_extend
):
510 # okok really should "if data_len == 4" and so on here
511 with m
.If(oper_r
.data_len
== 2):
512 comb
+= ldd_o
.eq(exts(revnorev
, 16, 64)) # sign-extend hword
514 comb
+= ldd_o
.eq(exts(revnorev
, 32, 64)) # sign-extend dword
516 comb
+= ldd_o
.eq(revnorev
)
518 # ld - ld gets latched in via lod_l
519 comb
+= ld_ok
.eq(pi
.ld
.ok
) # ld.ok *closes* (freezes) ld data
522 op3
= srl
[2] # 3rd operand latch
523 with m
.If(oper_r
.byte_reverse
):
524 # byte-reverse the data based on width
525 data_len
= oper_r
.data_len
526 stdata_r
= byte_reverse(m
, 'stdata_r', op3
, data_len
)
527 comb
+= pi
.st
.data
.eq(stdata_r
)
529 comb
+= pi
.st
.data
.eq(op3
)
530 # store - data goes in based on go_st
531 comb
+= pi
.st
.ok
.eq(self
.st
.go_i
) # go store signals st data valid
535 def get_out(self
, i
):
536 """make LDSTCompUnit look like RegSpecALUAPI. these correspond
537 to LDSTOutputData o and o1 respectively.
540 return self
.data_o
# LDSTOutputData.regspec o
542 return self
.addr_o
# LDSTOutputData.regspec o1
543 # return self.dest[i]
545 def get_fu_out(self
, i
):
546 return self
.get_out(i
)
556 yield from self
.oper_i
.ports()
557 yield from self
.src_i
563 yield from self
.data_o
.ports()
564 yield from self
.addr_o
.ports()
565 yield self
.load_mem_o
566 yield self
.stwd_mem_o
572 def wait_for(sig
, wait
=True, test1st
=False):
574 print("wait for", sig
, v
, wait
, test1st
)
575 if test1st
and bool(v
) == wait
:
580 #print("...wait for", sig, v)
585 def store(dut
, src1
, src2
, src3
, imm
, imm_ok
=True, update
=False,
587 print("ST", src1
, src2
, src3
, imm
, imm_ok
, update
)
588 yield dut
.oper_i
.insn_type
.eq(MicrOp
.OP_STORE
)
589 yield dut
.oper_i
.data_len
.eq(2) # half-word
590 yield dut
.oper_i
.byte_reverse
.eq(byterev
)
591 yield dut
.src1_i
.eq(src1
)
592 yield dut
.src2_i
.eq(src2
)
593 yield dut
.src3_i
.eq(src3
)
594 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
595 yield dut
.oper_i
.imm_data
.ok
.eq(imm_ok
)
596 yield dut
.oper_i
.update
.eq(update
)
597 yield dut
.issue_i
.eq(1)
599 yield dut
.issue_i
.eq(0)
605 # wait for all active rel signals to come up
607 rel
= yield dut
.rd
.rel_o
608 if rel
== active_rel
:
611 yield dut
.rd
.go
.eq(active_rel
)
613 yield dut
.rd
.go
.eq(0)
615 yield from wait_for(dut
.adr_rel_o
, False, test1st
=True)
616 # yield from wait_for(dut.adr_rel_o)
617 # yield dut.ad.go.eq(1)
619 # yield dut.ad.go.eq(0)
622 yield from wait_for(dut
.wr
.rel_o
[1])
623 yield dut
.wr
.go
.eq(0b10)
625 addr
= yield dut
.addr_o
627 yield dut
.wr
.go
.eq(0)
631 yield from wait_for(dut
.sto_rel_o
)
632 yield dut
.go_st_i
.eq(1)
634 yield dut
.go_st_i
.eq(0)
635 yield from wait_for(dut
.busy_o
, False)
636 # wait_for(dut.stwd_mem_o)
641 def load(dut
, src1
, src2
, imm
, imm_ok
=True, update
=False, zero_a
=False,
643 print("LD", src1
, src2
, imm
, imm_ok
, update
)
644 yield dut
.oper_i
.insn_type
.eq(MicrOp
.OP_LOAD
)
645 yield dut
.oper_i
.data_len
.eq(2) # half-word
646 yield dut
.oper_i
.byte_reverse
.eq(byterev
)
647 yield dut
.src1_i
.eq(src1
)
648 yield dut
.src2_i
.eq(src2
)
649 yield dut
.oper_i
.zero_a
.eq(zero_a
)
650 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
651 yield dut
.oper_i
.imm_data
.ok
.eq(imm_ok
)
652 yield dut
.issue_i
.eq(1)
654 yield dut
.issue_i
.eq(0)
657 # set up read-operand flags
659 if not imm_ok
: # no immediate means RB register needs to be read
661 if not zero_a
: # no zero-a means RA needs to be read
664 # wait for the operands (RA, RB, or both)
666 yield dut
.rd
.go
.eq(rd
)
667 yield from wait_for(dut
.rd
.rel_o
)
668 yield dut
.rd
.go
.eq(0)
670 yield from wait_for(dut
.adr_rel_o
, False, test1st
=True)
671 # yield dut.ad.go.eq(1)
673 # yield dut.ad.go.eq(0)
676 yield from wait_for(dut
.wr
.rel_o
[1])
677 yield dut
.wr
.go
.eq(0b10)
679 addr
= yield dut
.addr_o
681 yield dut
.wr
.go
.eq(0)
685 yield from wait_for(dut
.wr
.rel_o
[0], test1st
=True)
686 yield dut
.wr
.go
.eq(1)
688 data
= yield dut
.data_o
690 yield dut
.wr
.go
.eq(0)
691 yield from wait_for(dut
.busy_o
)
693 # wait_for(dut.stwd_mem_o)
702 # two STs (different addresses)
703 yield from store(dut
, 4, 0, 3, 2) # ST reg4 into addr rfile[reg3]+2
704 yield from store(dut
, 2, 0, 9, 2) # ST reg4 into addr rfile[reg9]+2
706 # two LDs (deliberately LD from the 1st address then 2nd)
707 data
, addr
= yield from load(dut
, 4, 0, 2)
708 assert data
== 0x0003, "returned %x" % data
709 data
, addr
= yield from load(dut
, 2, 0, 2)
710 assert data
== 0x0009, "returned %x" % data
714 yield from store(dut
, 9, 5, 3, 0, imm_ok
=False)
715 data
, addr
= yield from load(dut
, 9, 5, 0, imm_ok
=False)
716 assert data
== 0x0003, "returned %x" % data
718 # update-immediate version
719 addr
= yield from store(dut
, 9, 6, 3, 2, update
=True)
720 assert addr
== 0x000b, "returned %x" % addr
722 # update-indexed version
723 data
, addr
= yield from load(dut
, 9, 5, 0, imm_ok
=False, update
=True)
724 assert data
== 0x0003, "returned %x" % data
725 assert addr
== 0x000e, "returned %x" % addr
727 # immediate *and* zero version
728 data
, addr
= yield from load(dut
, 1, 4, 8, imm_ok
=True, zero_a
=True)
729 assert data
== 0x0008, "returned %x" % data
732 class TestLDSTCompUnit(LDSTCompUnit
):
734 def __init__(self
, rwid
):
735 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
736 self
.l0
= l0
= TstL0CacheBuffer()
737 pi
= l0
.l0
.dports
[0].pi
738 LDSTCompUnit
.__init
__(self
, pi
, rwid
, 4)
740 def elaborate(self
, platform
):
741 m
= LDSTCompUnit
.elaborate(self
, platform
)
742 m
.submodules
.l0
= self
.l0
743 m
.d
.comb
+= self
.ad
.go
.eq(self
.ad
.rel
) # link addr-go direct to rel
747 def test_scoreboard():
749 dut
= TestLDSTCompUnit(16)
750 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
751 with
open("test_ldst_comp.il", "w") as f
:
754 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_comp.vcd')
757 class TestLDSTCompUnitRegSpec(LDSTCompUnit
):
760 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
761 from soc
.fu
.ldst
.pipe_data
import LDSTPipeSpec
762 regspec
= LDSTPipeSpec
.regspec
763 self
.l0
= l0
= TstL0CacheBuffer()
764 pi
= l0
.l0
.dports
[0].pi
765 LDSTCompUnit
.__init
__(self
, pi
, regspec
, 4)
767 def elaborate(self
, platform
):
768 m
= LDSTCompUnit
.elaborate(self
, platform
)
769 m
.submodules
.l0
= self
.l0
770 m
.d
.comb
+= self
.ad
.go
.eq(self
.ad
.rel
) # link addr-go direct to rel
774 def test_scoreboard_regspec():
776 dut
= TestLDSTCompUnitRegSpec()
777 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
778 with
open("test_ldst_comp.il", "w") as f
:
781 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_regspec.vcd')
784 if __name__
== '__main__':
785 test_scoreboard_regspec()