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dcache load/store test
[soc.git] / src / soc / experiment / dcache.py
1 """DCache
2
3 based on Anton Blanchard microwatt dcache.vhdl
4
5 """
6
7 from enum import Enum, unique
8
9 from nmigen import Module, Signal, Elaboratable, Cat, Repl, Array, Const
10 try:
11 from nmigen.hdl.ast import Display
12 except ImportError:
13 def Display(*args):
14 return []
15
16 from nmigen.cli import main
17 from nmutil.iocontrol import RecordObject
18 from nmutil.util import wrap
19 from nmigen.utils import log2_int
20 from soc.experiment.mem_types import (LoadStore1ToDCacheType,
21 DCacheToLoadStore1Type,
22 MMUToDCacheType,
23 DCacheToMMUType)
24
25 from soc.experiment.wb_types import (WB_ADDR_BITS, WB_DATA_BITS, WB_SEL_BITS,
26 WBAddrType, WBDataType, WBSelType,
27 WBMasterOut, WBSlaveOut,
28 WBMasterOutVector, WBSlaveOutVector,
29 WBIOMasterOut, WBIOSlaveOut)
30
31 from soc.experiment.cache_ram import CacheRam
32 from soc.experiment.plru import PLRU
33
34 # for test
35 from nmigen_soc.wishbone.sram import SRAM
36 from nmigen import Memory
37 from nmigen.cli import rtlil
38 if True:
39 from nmigen.back.pysim import Simulator, Delay, Settle
40 else:
41 from nmigen.sim.cxxsim import Simulator, Delay, Settle
42
43
44 # TODO: make these parameters of DCache at some point
45 LINE_SIZE = 64 # Line size in bytes
46 NUM_LINES = 16 # Number of lines in a set
47 NUM_WAYS = 4 # Number of ways
48 TLB_SET_SIZE = 64 # L1 DTLB entries per set
49 TLB_NUM_WAYS = 2 # L1 DTLB number of sets
50 TLB_LG_PGSZ = 12 # L1 DTLB log_2(page_size)
51 LOG_LENGTH = 0 # Non-zero to enable log data collection
52
53 # BRAM organisation: We never access more than
54 # -- WB_DATA_BITS at a time so to save
55 # -- resources we make the array only that wide, and
56 # -- use consecutive indices for to make a cache "line"
57 # --
58 # -- ROW_SIZE is the width in bytes of the BRAM
59 # -- (based on WB, so 64-bits)
60 ROW_SIZE = WB_DATA_BITS // 8;
61
62 # ROW_PER_LINE is the number of row (wishbone
63 # transactions) in a line
64 ROW_PER_LINE = LINE_SIZE // ROW_SIZE
65
66 # BRAM_ROWS is the number of rows in BRAM needed
67 # to represent the full dcache
68 BRAM_ROWS = NUM_LINES * ROW_PER_LINE
69
70
71 # Bit fields counts in the address
72
73 # REAL_ADDR_BITS is the number of real address
74 # bits that we store
75 REAL_ADDR_BITS = 56
76
77 # ROW_BITS is the number of bits to select a row
78 ROW_BITS = log2_int(BRAM_ROWS)
79
80 # ROW_LINE_BITS is the number of bits to select
81 # a row within a line
82 ROW_LINE_BITS = log2_int(ROW_PER_LINE)
83
84 # LINE_OFF_BITS is the number of bits for
85 # the offset in a cache line
86 LINE_OFF_BITS = log2_int(LINE_SIZE)
87
88 # ROW_OFF_BITS is the number of bits for
89 # the offset in a row
90 ROW_OFF_BITS = log2_int(ROW_SIZE)
91
92 # INDEX_BITS is the number if bits to
93 # select a cache line
94 INDEX_BITS = log2_int(NUM_LINES)
95
96 # SET_SIZE_BITS is the log base 2 of the set size
97 SET_SIZE_BITS = LINE_OFF_BITS + INDEX_BITS
98
99 # TAG_BITS is the number of bits of
100 # the tag part of the address
101 TAG_BITS = REAL_ADDR_BITS - SET_SIZE_BITS
102
103 # TAG_WIDTH is the width in bits of each way of the tag RAM
104 TAG_WIDTH = TAG_BITS + 7 - ((TAG_BITS + 7) % 8)
105
106 # WAY_BITS is the number of bits to select a way
107 WAY_BITS = log2_int(NUM_WAYS)
108
109 # Example of layout for 32 lines of 64 bytes:
110 #
111 # .. tag |index| line |
112 # .. | row | |
113 # .. | |---| | ROW_LINE_BITS (3)
114 # .. | |--- - --| LINE_OFF_BITS (6)
115 # .. | |- --| ROW_OFF_BITS (3)
116 # .. |----- ---| | ROW_BITS (8)
117 # .. |-----| | INDEX_BITS (5)
118 # .. --------| | TAG_BITS (45)
119
120 TAG_RAM_WIDTH = TAG_WIDTH * NUM_WAYS
121
122 def CacheTagArray():
123 return Array(Signal(TAG_RAM_WIDTH) for x in range(NUM_LINES))
124
125 def CacheValidBitsArray():
126 return Array(Signal(INDEX_BITS) for x in range(NUM_LINES))
127
128 def RowPerLineValidArray():
129 return Array(Signal(name="rows_valid%d" % x) for x in range(ROW_PER_LINE))
130
131 # L1 TLB
132 TLB_SET_BITS = log2_int(TLB_SET_SIZE)
133 TLB_WAY_BITS = log2_int(TLB_NUM_WAYS)
134 TLB_EA_TAG_BITS = 64 - (TLB_LG_PGSZ + TLB_SET_BITS)
135 TLB_TAG_WAY_BITS = TLB_NUM_WAYS * TLB_EA_TAG_BITS
136 TLB_PTE_BITS = 64
137 TLB_PTE_WAY_BITS = TLB_NUM_WAYS * TLB_PTE_BITS;
138
139 assert (LINE_SIZE % ROW_SIZE) == 0, "LINE_SIZE not multiple of ROW_SIZE"
140 assert (LINE_SIZE % 2) == 0, "LINE_SIZE not power of 2"
141 assert (NUM_LINES % 2) == 0, "NUM_LINES not power of 2"
142 assert (ROW_PER_LINE % 2) == 0, "ROW_PER_LINE not power of 2"
143 assert ROW_BITS == (INDEX_BITS + ROW_LINE_BITS), "geometry bits don't add up"
144 assert (LINE_OFF_BITS == ROW_OFF_BITS + ROW_LINE_BITS), \
145 "geometry bits don't add up"
146 assert REAL_ADDR_BITS == (TAG_BITS + INDEX_BITS + LINE_OFF_BITS), \
147 "geometry bits don't add up"
148 assert REAL_ADDR_BITS == (TAG_BITS + ROW_BITS + ROW_OFF_BITS), \
149 "geometry bits don't add up"
150 assert 64 == WB_DATA_BITS, "Can't yet handle wb width that isn't 64-bits"
151 assert SET_SIZE_BITS <= TLB_LG_PGSZ, "Set indexed by virtual address"
152
153
154 def TLBValidBitsArray():
155 return Array(Signal(TLB_NUM_WAYS) for x in range(TLB_SET_SIZE))
156
157 def TLBTagEAArray():
158 return Array(Signal(TLB_EA_TAG_BITS) for x in range (TLB_NUM_WAYS))
159
160 def TLBTagsArray():
161 return Array(Signal(TLB_TAG_WAY_BITS) for x in range (TLB_SET_SIZE))
162
163 def TLBPtesArray():
164 return Array(Signal(TLB_PTE_WAY_BITS) for x in range(TLB_SET_SIZE))
165
166 def HitWaySet():
167 return Array(Signal(WAY_BITS) for x in range(TLB_NUM_WAYS))
168
169 # Cache RAM interface
170 def CacheRamOut():
171 return Array(Signal(WB_DATA_BITS) for x in range(NUM_WAYS))
172
173 # PLRU output interface
174 def PLRUOut():
175 return Array(Signal(WAY_BITS) for x in range(NUM_LINES))
176
177 # TLB PLRU output interface
178 def TLBPLRUOut():
179 return Array(Signal(TLB_WAY_BITS) for x in range(TLB_SET_SIZE))
180
181 # Helper functions to decode incoming requests
182 #
183 # Return the cache line index (tag index) for an address
184 def get_index(addr):
185 return addr[LINE_OFF_BITS:SET_SIZE_BITS]
186
187 # Return the cache row index (data memory) for an address
188 def get_row(addr):
189 return addr[ROW_OFF_BITS:SET_SIZE_BITS]
190
191 # Return the index of a row within a line
192 def get_row_of_line(row):
193 return row[:ROW_LINE_BITS]
194
195 # Returns whether this is the last row of a line
196 def is_last_row_addr(addr, last):
197 return addr[ROW_OFF_BITS:LINE_OFF_BITS] == last
198
199 # Returns whether this is the last row of a line
200 def is_last_row(row, last):
201 return get_row_of_line(row) == last
202
203 # Return the next row in the current cache line. We use a
204 # dedicated function in order to limit the size of the
205 # generated adder to be only the bits within a cache line
206 # (3 bits with default settings)
207 def next_row(row):
208 row_v = row[0:ROW_LINE_BITS] + 1
209 return Cat(row_v[:ROW_LINE_BITS], row[ROW_LINE_BITS:])
210
211 # Get the tag value from the address
212 def get_tag(addr):
213 return addr[SET_SIZE_BITS:REAL_ADDR_BITS]
214
215 # Read a tag from a tag memory row
216 def read_tag(way, tagset):
217 return tagset.word_select(way, TAG_WIDTH)[:TAG_BITS]
218
219 # Read a TLB tag from a TLB tag memory row
220 def read_tlb_tag(way, tags):
221 return tags.word_select(way, TLB_EA_TAG_BITS)
222
223 # Write a TLB tag to a TLB tag memory row
224 def write_tlb_tag(way, tags, tag):
225 return read_tlb_tag(way, tags).eq(tag)
226
227 # Read a PTE from a TLB PTE memory row
228 def read_tlb_pte(way, ptes):
229 return ptes.word_select(way, TLB_PTE_BITS)
230
231 def write_tlb_pte(way, ptes, newpte):
232 return read_tlb_pte(way, ptes).eq(newpte)
233
234
235 # Record for storing permission, attribute, etc. bits from a PTE
236 class PermAttr(RecordObject):
237 def __init__(self, name=None):
238 super().__init__(name=name)
239 self.reference = Signal()
240 self.changed = Signal()
241 self.nocache = Signal()
242 self.priv = Signal()
243 self.rd_perm = Signal()
244 self.wr_perm = Signal()
245
246
247 def extract_perm_attr(pte):
248 pa = PermAttr()
249 pa.reference = pte[8]
250 pa.changed = pte[7]
251 pa.nocache = pte[5]
252 pa.priv = pte[3]
253 pa.rd_perm = pte[2]
254 pa.wr_perm = pte[1]
255 return pa;
256
257
258 # Type of operation on a "valid" input
259 @unique
260 class Op(Enum):
261 OP_NONE = 0
262 OP_BAD = 1 # NC cache hit, TLB miss, prot/RC failure
263 OP_STCX_FAIL = 2 # conditional store w/o reservation
264 OP_LOAD_HIT = 3 # Cache hit on load
265 OP_LOAD_MISS = 4 # Load missing cache
266 OP_LOAD_NC = 5 # Non-cachable load
267 OP_STORE_HIT = 6 # Store hitting cache
268 OP_STORE_MISS = 7 # Store missing cache
269
270
271 # Cache state machine
272 @unique
273 class State(Enum):
274 IDLE = 0 # Normal load hit processing
275 RELOAD_WAIT_ACK = 1 # Cache reload wait ack
276 STORE_WAIT_ACK = 2 # Store wait ack
277 NC_LOAD_WAIT_ACK = 3 # Non-cachable load wait ack
278
279
280 # Dcache operations:
281 #
282 # In order to make timing, we use the BRAMs with
283 # an output buffer, which means that the BRAM
284 # output is delayed by an extra cycle.
285 #
286 # Thus, the dcache has a 2-stage internal pipeline
287 # for cache hits with no stalls.
288 #
289 # All other operations are handled via stalling
290 # in the first stage.
291 #
292 # The second stage can thus complete a hit at the same
293 # time as the first stage emits a stall for a complex op.
294 #
295 # Stage 0 register, basically contains just the latched request
296
297 class RegStage0(RecordObject):
298 def __init__(self, name=None):
299 super().__init__(name=name)
300 self.req = LoadStore1ToDCacheType(name="lsmem")
301 self.tlbie = Signal()
302 self.doall = Signal()
303 self.tlbld = Signal()
304 self.mmu_req = Signal() # indicates source of request
305
306
307 class MemAccessRequest(RecordObject):
308 def __init__(self, name=None):
309 super().__init__(name=name)
310 self.op = Signal(Op)
311 self.valid = Signal()
312 self.dcbz = Signal()
313 self.real_addr = Signal(REAL_ADDR_BITS)
314 self.data = Signal(64)
315 self.byte_sel = Signal(8)
316 self.hit_way = Signal(WAY_BITS)
317 self.same_tag = Signal()
318 self.mmu_req = Signal()
319
320
321 # First stage register, contains state for stage 1 of load hits
322 # and for the state machine used by all other operations
323 class RegStage1(RecordObject):
324 def __init__(self, name=None):
325 super().__init__(name=name)
326 # Info about the request
327 self.full = Signal() # have uncompleted request
328 self.mmu_req = Signal() # request is from MMU
329 self.req = MemAccessRequest(name="reqmem")
330
331 # Cache hit state
332 self.hit_way = Signal(WAY_BITS)
333 self.hit_load_valid = Signal()
334 self.hit_index = Signal(INDEX_BITS)
335 self.cache_hit = Signal()
336
337 # TLB hit state
338 self.tlb_hit = Signal()
339 self.tlb_hit_way = Signal(TLB_NUM_WAYS)
340 self.tlb_hit_index = Signal(TLB_WAY_BITS)
341
342 # 2-stage data buffer for data forwarded from writes to reads
343 self.forward_data1 = Signal(64)
344 self.forward_data2 = Signal(64)
345 self.forward_sel1 = Signal(8)
346 self.forward_valid1 = Signal()
347 self.forward_way1 = Signal(WAY_BITS)
348 self.forward_row1 = Signal(ROW_BITS)
349 self.use_forward1 = Signal()
350 self.forward_sel = Signal(8)
351
352 # Cache miss state (reload state machine)
353 self.state = Signal(State)
354 self.dcbz = Signal()
355 self.write_bram = Signal()
356 self.write_tag = Signal()
357 self.slow_valid = Signal()
358 self.wb = WBMasterOut()
359 self.reload_tag = Signal(TAG_BITS)
360 self.store_way = Signal(WAY_BITS)
361 self.store_row = Signal(ROW_BITS)
362 self.store_index = Signal(INDEX_BITS)
363 self.end_row_ix = Signal(ROW_LINE_BITS)
364 self.rows_valid = RowPerLineValidArray()
365 self.acks_pending = Signal(3)
366 self.inc_acks = Signal()
367 self.dec_acks = Signal()
368
369 # Signals to complete (possibly with error)
370 self.ls_valid = Signal()
371 self.ls_error = Signal()
372 self.mmu_done = Signal()
373 self.mmu_error = Signal()
374 self.cache_paradox = Signal()
375
376 # Signal to complete a failed stcx.
377 self.stcx_fail = Signal()
378
379
380 # Reservation information
381 class Reservation(RecordObject):
382 def __init__(self):
383 super().__init__()
384 self.valid = Signal()
385 self.addr = Signal(64-LINE_OFF_BITS)
386
387
388 class DTLBUpdate(Elaboratable):
389 def __init__(self):
390 self.tlbie = Signal()
391 self.tlbwe = Signal()
392 self.doall = Signal()
393 self.updated = Signal()
394 self.v_updated = Signal()
395 self.tlb_hit = Signal()
396 self.tlb_req_index = Signal(TLB_SET_BITS)
397
398 self.tlb_hit_way = Signal(TLB_WAY_BITS)
399 self.tlb_tag_way = Signal(TLB_TAG_WAY_BITS)
400 self.tlb_pte_way = Signal(TLB_PTE_WAY_BITS)
401 self.repl_way = Signal(TLB_WAY_BITS)
402 self.eatag = Signal(TLB_EA_TAG_BITS)
403 self.pte_data = Signal(TLB_PTE_BITS)
404
405 self.dv = Signal(TLB_PTE_WAY_BITS)
406
407 self.tb_out = Signal(TLB_TAG_WAY_BITS)
408 self.pb_out = Signal(TLB_NUM_WAYS)
409 self.db_out = Signal(TLB_PTE_WAY_BITS)
410
411 def elaborate(self, platform):
412 m = Module()
413 comb = m.d.comb
414 sync = m.d.sync
415
416 tagset = Signal(TLB_TAG_WAY_BITS)
417 pteset = Signal(TLB_PTE_WAY_BITS)
418
419 tb_out, pb_out, db_out = self.tb_out, self.pb_out, self.db_out
420
421 with m.If(self.tlbie & self.doall):
422 pass # clear all back in parent
423 with m.Elif(self.tlbie):
424 with m.If(self.tlb_hit):
425 comb += db_out.eq(self.dv)
426 comb += db_out.bit_select(self.tlb_hit_way, 1).eq(1)
427 comb += self.v_updated.eq(1)
428
429 with m.Elif(self.tlbwe):
430
431 comb += tagset.eq(self.tlb_tag_way)
432 comb += write_tlb_tag(self.repl_way, tagset, self.eatag)
433 comb += tb_out.eq(tagset)
434
435 comb += pteset.eq(self.tlb_pte_way)
436 comb += write_tlb_pte(self.repl_way, pteset, self.pte_data)
437 comb += pb_out.eq(pteset)
438
439 comb += db_out.bit_select(self.repl_way, 1).eq(1)
440
441 comb += self.updated.eq(1)
442 comb += self.v_updated.eq(1)
443
444 return m
445
446 def dcache_request(self, m, r0, ra, req_index, req_row, req_tag,
447 r0_valid, r1, cache_valid_bits, replace_way,
448 use_forward1_next, use_forward2_next,
449 req_hit_way, plru_victim, rc_ok, perm_attr,
450 valid_ra, perm_ok, access_ok, req_op, req_go,
451 tlb_pte_way,
452 tlb_hit, tlb_hit_way, tlb_valid_way, cache_tag_set,
453 cancel_store, req_same_tag, r0_stall, early_req_row):
454 """Cache request parsing and hit detection
455 """
456
457 class DCachePendingHit(Elaboratable):
458
459 def __init__(self, tlb_pte_way, tlb_valid_way, tlb_hit_way,
460 cache_valid_idx, cache_tag_set,
461 req_addr,
462 hit_set):
463
464 self.go = Signal()
465 self.virt_mode = Signal()
466 self.is_hit = Signal()
467 self.tlb_hit = Signal()
468 self.hit_way = Signal(WAY_BITS)
469 self.rel_match = Signal()
470 self.req_index = Signal(INDEX_BITS)
471 self.reload_tag = Signal(TAG_BITS)
472
473 self.tlb_hit_way = tlb_hit_way
474 self.tlb_pte_way = tlb_pte_way
475 self.tlb_valid_way = tlb_valid_way
476 self.cache_valid_idx = cache_valid_idx
477 self.cache_tag_set = cache_tag_set
478 self.req_addr = req_addr
479 self.hit_set = hit_set
480
481 def elaborate(self, platform):
482 m = Module()
483 comb = m.d.comb
484 sync = m.d.sync
485
486 go = self.go
487 virt_mode = self.virt_mode
488 is_hit = self.is_hit
489 tlb_pte_way = self.tlb_pte_way
490 tlb_valid_way = self.tlb_valid_way
491 cache_valid_idx = self.cache_valid_idx
492 cache_tag_set = self.cache_tag_set
493 req_addr = self.req_addr
494 tlb_hit_way = self.tlb_hit_way
495 tlb_hit = self.tlb_hit
496 hit_set = self.hit_set
497 hit_way = self.hit_way
498 rel_match = self.rel_match
499 req_index = self.req_index
500 reload_tag = self.reload_tag
501
502 rel_matches = Array(Signal() for i in range(TLB_NUM_WAYS))
503 hit_way_set = HitWaySet()
504
505 # Test if pending request is a hit on any way
506 # In order to make timing in virtual mode,
507 # when we are using the TLB, we compare each
508 # way with each of the real addresses from each way of
509 # the TLB, and then decide later which match to use.
510
511 with m.If(virt_mode):
512 for j in range(TLB_NUM_WAYS):
513 s_tag = Signal(TAG_BITS, name="s_tag%d" % j)
514 s_hit = Signal()
515 s_pte = Signal(TLB_PTE_BITS)
516 s_ra = Signal(REAL_ADDR_BITS)
517 comb += s_pte.eq(read_tlb_pte(j, tlb_pte_way))
518 comb += s_ra.eq(Cat(req_addr[0:TLB_LG_PGSZ],
519 s_pte[TLB_LG_PGSZ:REAL_ADDR_BITS]))
520 comb += s_tag.eq(get_tag(s_ra))
521
522 for i in range(NUM_WAYS):
523 is_tag_hit = Signal(name="is_tag_hit_%d_%d" % (j, i))
524 comb += is_tag_hit.eq(go & cache_valid_idx[i] &
525 (read_tag(i, cache_tag_set) == s_tag)
526 & tlb_valid_way[j])
527 with m.If(is_tag_hit):
528 comb += hit_way_set[j].eq(i)
529 comb += s_hit.eq(1)
530 comb += hit_set[j].eq(s_hit)
531 with m.If(s_tag == reload_tag):
532 comb += rel_matches[j].eq(1)
533 with m.If(tlb_hit):
534 comb += is_hit.eq(hit_set[tlb_hit_way])
535 comb += hit_way.eq(hit_way_set[tlb_hit_way])
536 comb += rel_match.eq(rel_matches[tlb_hit_way])
537 with m.Else():
538 s_tag = Signal(TAG_BITS)
539 comb += s_tag.eq(get_tag(req_addr))
540 for i in range(NUM_WAYS):
541 is_tag_hit = Signal(name="is_tag_hit_%d" % i)
542 comb += is_tag_hit.eq(go & cache_valid_idx[i] &
543 (read_tag(i, cache_tag_set) == s_tag))
544 with m.If(is_tag_hit):
545 comb += hit_way.eq(i)
546 comb += is_hit.eq(1)
547 with m.If(s_tag == reload_tag):
548 comb += rel_match.eq(1)
549
550 return m
551
552
553 class DCache(Elaboratable):
554 """Set associative dcache write-through
555 TODO (in no specific order):
556 * See list in icache.vhdl
557 * Complete load misses on the cycle when WB data comes instead of
558 at the end of line (this requires dealing with requests coming in
559 while not idle...)
560 """
561 def __init__(self):
562 self.d_in = LoadStore1ToDCacheType("d_in")
563 self.d_out = DCacheToLoadStore1Type("d_out")
564
565 self.m_in = MMUToDCacheType("m_in")
566 self.m_out = DCacheToMMUType("m_out")
567
568 self.stall_out = Signal()
569
570 self.wb_out = WBMasterOut()
571 self.wb_in = WBSlaveOut()
572
573 self.log_out = Signal(20)
574
575 def stage_0(self, m, r0, r1, r0_full):
576 """Latch the request in r0.req as long as we're not stalling
577 """
578 comb = m.d.comb
579 sync = m.d.sync
580 d_in, d_out, m_in = self.d_in, self.d_out, self.m_in
581
582 r = RegStage0("stage0")
583
584 # TODO, this goes in unit tests and formal proofs
585 with m.If(~(d_in.valid & m_in.valid)):
586 #sync += Display("request collision loadstore vs MMU")
587 pass
588
589 with m.If(m_in.valid):
590 sync += r.req.valid.eq(1)
591 sync += r.req.load.eq(~(m_in.tlbie | m_in.tlbld))
592 sync += r.req.dcbz.eq(0)
593 sync += r.req.nc.eq(0)
594 sync += r.req.reserve.eq(0)
595 sync += r.req.virt_mode.eq(1)
596 sync += r.req.priv_mode.eq(1)
597 sync += r.req.addr.eq(m_in.addr)
598 sync += r.req.data.eq(m_in.pte)
599 sync += r.req.byte_sel.eq(~0) # Const -1 sets all to 0b111....
600 sync += r.tlbie.eq(m_in.tlbie)
601 sync += r.doall.eq(m_in.doall)
602 sync += r.tlbld.eq(m_in.tlbld)
603 sync += r.mmu_req.eq(1)
604 with m.Else():
605 sync += r.req.eq(d_in)
606 sync += r.tlbie.eq(0)
607 sync += r.doall.eq(0)
608 sync += r.tlbld.eq(0)
609 sync += r.mmu_req.eq(0)
610 with m.If(~(r1.full & r0_full)):
611 sync += r0.eq(r)
612 sync += r0_full.eq(r.req.valid)
613
614 def tlb_read(self, m, r0_stall, tlb_valid_way,
615 tlb_tag_way, tlb_pte_way, dtlb_valid_bits,
616 dtlb_tags, dtlb_ptes):
617 """TLB
618 Operates in the second cycle on the request latched in r0.req.
619 TLB updates write the entry at the end of the second cycle.
620 """
621 comb = m.d.comb
622 sync = m.d.sync
623 m_in, d_in = self.m_in, self.d_in
624
625 index = Signal(TLB_SET_BITS)
626 addrbits = Signal(TLB_SET_BITS)
627
628 amin = TLB_LG_PGSZ
629 amax = TLB_LG_PGSZ + TLB_SET_BITS
630
631 with m.If(m_in.valid):
632 comb += addrbits.eq(m_in.addr[amin : amax])
633 with m.Else():
634 comb += addrbits.eq(d_in.addr[amin : amax])
635 comb += index.eq(addrbits)
636
637 # If we have any op and the previous op isn't finished,
638 # then keep the same output for next cycle.
639 with m.If(~r0_stall):
640 sync += tlb_valid_way.eq(dtlb_valid_bits[index])
641 sync += tlb_tag_way.eq(dtlb_tags[index])
642 sync += tlb_pte_way.eq(dtlb_ptes[index])
643
644 def maybe_tlb_plrus(self, m, r1, tlb_plru_victim):
645 """Generate TLB PLRUs
646 """
647 comb = m.d.comb
648 sync = m.d.sync
649
650 if TLB_NUM_WAYS == 0:
651 return
652 for i in range(TLB_SET_SIZE):
653 # TLB PLRU interface
654 tlb_plru = PLRU(WAY_BITS)
655 setattr(m.submodules, "maybe_plru_%d" % i, tlb_plru)
656 tlb_plru_acc_en = Signal()
657
658 comb += tlb_plru_acc_en.eq(r1.tlb_hit & (r1.tlb_hit_index == i))
659 comb += tlb_plru.acc_en.eq(tlb_plru_acc_en)
660 comb += tlb_plru.acc.eq(r1.tlb_hit_way)
661 comb += tlb_plru_victim[i].eq(tlb_plru.lru_o)
662
663 def tlb_search(self, m, tlb_req_index, r0, r0_valid,
664 tlb_valid_way, tlb_tag_way, tlb_hit_way,
665 tlb_pte_way, pte, tlb_hit, valid_ra, perm_attr, ra):
666
667 comb = m.d.comb
668 sync = m.d.sync
669
670 hitway = Signal(TLB_WAY_BITS)
671 hit = Signal()
672 eatag = Signal(TLB_EA_TAG_BITS)
673
674 TLB_LG_END = TLB_LG_PGSZ + TLB_SET_BITS
675 comb += tlb_req_index.eq(r0.req.addr[TLB_LG_PGSZ : TLB_LG_END])
676 comb += eatag.eq(r0.req.addr[TLB_LG_END : 64 ])
677
678 for i in range(TLB_NUM_WAYS):
679 is_tag_hit = Signal()
680 comb += is_tag_hit.eq(tlb_valid_way[i]
681 & read_tlb_tag(i, tlb_tag_way) == eatag)
682 with m.If(is_tag_hit):
683 comb += hitway.eq(i)
684 comb += hit.eq(1)
685
686 comb += tlb_hit.eq(hit & r0_valid)
687 comb += tlb_hit_way.eq(hitway)
688
689 with m.If(tlb_hit):
690 comb += pte.eq(read_tlb_pte(hitway, tlb_pte_way))
691 with m.Else():
692 comb += pte.eq(0)
693 comb += valid_ra.eq(tlb_hit | ~r0.req.virt_mode)
694 with m.If(r0.req.virt_mode):
695 comb += ra.eq(Cat(Const(0, ROW_OFF_BITS),
696 r0.req.addr[ROW_OFF_BITS:TLB_LG_PGSZ],
697 pte[TLB_LG_PGSZ:REAL_ADDR_BITS]))
698 comb += perm_attr.eq(extract_perm_attr(pte))
699 with m.Else():
700 comb += ra.eq(Cat(Const(0, ROW_OFF_BITS),
701 r0.req.addr[ROW_OFF_BITS:REAL_ADDR_BITS]))
702
703 comb += perm_attr.reference.eq(1)
704 comb += perm_attr.changed.eq(1)
705 comb += perm_attr.nocache.eq(0)
706 comb += perm_attr.priv.eq(1)
707 comb += perm_attr.rd_perm.eq(1)
708 comb += perm_attr.wr_perm.eq(1)
709
710 def tlb_update(self, m, r0_valid, r0, dtlb_valid_bits, tlb_req_index,
711 tlb_hit_way, tlb_hit, tlb_plru_victim, tlb_tag_way,
712 dtlb_tags, tlb_pte_way, dtlb_ptes):
713
714 comb = m.d.comb
715 sync = m.d.sync
716
717 tlbie = Signal()
718 tlbwe = Signal()
719
720 comb += tlbie.eq(r0_valid & r0.tlbie)
721 comb += tlbwe.eq(r0_valid & r0.tlbld)
722
723 m.submodules.tlb_update = d = DTLBUpdate()
724 with m.If(tlbie & r0.doall):
725 # clear all valid bits at once
726 for i in range(TLB_SET_SIZE):
727 sync += dtlb_valid_bits[i].eq(0)
728 with m.If(d.updated):
729 sync += dtlb_tags[tlb_req_index].eq(d.tb_out)
730 sync += dtlb_ptes[tlb_req_index].eq(d.pb_out)
731 with m.If(d.v_updated):
732 sync += dtlb_valid_bits[tlb_req_index].eq(d.db_out)
733
734 comb += d.dv.eq(dtlb_valid_bits[tlb_req_index])
735
736 comb += d.tlbie.eq(tlbie)
737 comb += d.tlbwe.eq(tlbwe)
738 comb += d.doall.eq(r0.doall)
739 comb += d.tlb_hit.eq(tlb_hit)
740 comb += d.tlb_hit_way.eq(tlb_hit_way)
741 comb += d.tlb_tag_way.eq(tlb_tag_way)
742 comb += d.tlb_pte_way.eq(tlb_pte_way)
743 comb += d.tlb_req_index.eq(tlb_req_index)
744
745 with m.If(tlb_hit):
746 comb += d.repl_way.eq(tlb_hit_way)
747 with m.Else():
748 comb += d.repl_way.eq(tlb_plru_victim[tlb_req_index])
749 comb += d.eatag.eq(r0.req.addr[TLB_LG_PGSZ + TLB_SET_BITS:64])
750 comb += d.pte_data.eq(r0.req.data)
751
752 def maybe_plrus(self, m, r1, plru_victim):
753 """Generate PLRUs
754 """
755 comb = m.d.comb
756 sync = m.d.sync
757
758 if TLB_NUM_WAYS == 0:
759 return
760
761 for i in range(NUM_LINES):
762 # PLRU interface
763 plru = PLRU(WAY_BITS)
764 setattr(m.submodules, "plru%d" % i, plru)
765 plru_acc_en = Signal()
766
767 comb += plru_acc_en.eq(r1.cache_hit & (r1.hit_index == i))
768 comb += plru.acc_en.eq(plru_acc_en)
769 comb += plru.acc.eq(r1.hit_way)
770 comb += plru_victim[i].eq(plru.lru_o)
771
772 def cache_tag_read(self, m, r0_stall, req_index, cache_tag_set, cache_tags):
773 """Cache tag RAM read port
774 """
775 comb = m.d.comb
776 sync = m.d.sync
777 m_in, d_in = self.m_in, self.d_in
778
779 index = Signal(INDEX_BITS)
780
781 with m.If(r0_stall):
782 comb += index.eq(req_index)
783 with m.Elif(m_in.valid):
784 comb += index.eq(get_index(m_in.addr))
785 with m.Else():
786 comb += index.eq(get_index(d_in.addr))
787 sync += cache_tag_set.eq(cache_tags[index])
788
789 def dcache_request(self, m, r0, ra, req_index, req_row, req_tag,
790 r0_valid, r1, cache_valid_bits, replace_way,
791 use_forward1_next, use_forward2_next,
792 req_hit_way, plru_victim, rc_ok, perm_attr,
793 valid_ra, perm_ok, access_ok, req_op, req_go,
794 tlb_pte_way,
795 tlb_hit, tlb_hit_way, tlb_valid_way, cache_tag_set,
796 cancel_store, req_same_tag, r0_stall, early_req_row):
797 """Cache request parsing and hit detection
798 """
799
800 comb = m.d.comb
801 sync = m.d.sync
802 m_in, d_in = self.m_in, self.d_in
803
804 is_hit = Signal()
805 hit_way = Signal(WAY_BITS)
806 op = Signal(Op)
807 opsel = Signal(3)
808 go = Signal()
809 nc = Signal()
810 hit_set = Array(Signal() for i in range(TLB_NUM_WAYS))
811 cache_valid_idx = Signal(INDEX_BITS)
812
813 # Extract line, row and tag from request
814 comb += req_index.eq(get_index(r0.req.addr))
815 comb += req_row.eq(get_row(r0.req.addr))
816 comb += req_tag.eq(get_tag(ra))
817
818 comb += go.eq(r0_valid & ~(r0.tlbie | r0.tlbld) & ~r1.ls_error)
819 comb += cache_valid_idx.eq(cache_valid_bits[req_index])
820
821 m.submodules.dcache_pend = dc = DCachePendingHit(tlb_pte_way,
822 tlb_valid_way, tlb_hit_way,
823 cache_valid_idx, cache_tag_set,
824 r0.req.addr,
825 hit_set)
826
827 comb += dc.tlb_hit.eq(tlb_hit)
828 comb += dc.reload_tag.eq(r1.reload_tag)
829 comb += dc.virt_mode.eq(r0.req.virt_mode)
830 comb += dc.go.eq(go)
831 comb += dc.req_index.eq(req_index)
832 comb += is_hit.eq(dc.is_hit)
833 comb += hit_way.eq(dc.hit_way)
834 comb += req_same_tag.eq(dc.rel_match)
835
836 # See if the request matches the line currently being reloaded
837 with m.If((r1.state == State.RELOAD_WAIT_ACK) &
838 (req_index == r1.store_index) & req_same_tag):
839 # For a store, consider this a hit even if the row isn't
840 # valid since it will be by the time we perform the store.
841 # For a load, check the appropriate row valid bit.
842 valid = r1.rows_valid[req_row % ROW_PER_LINE]
843 comb += is_hit.eq(~r0.req.load | valid)
844 comb += hit_way.eq(replace_way)
845
846 # Whether to use forwarded data for a load or not
847 comb += use_forward1_next.eq(0)
848 with m.If((get_row(r1.req.real_addr) == req_row) &
849 (r1.req.hit_way == hit_way)):
850 # Only need to consider r1.write_bram here, since if we
851 # are writing refill data here, then we don't have a
852 # cache hit this cycle on the line being refilled.
853 # (There is the possibility that the load following the
854 # load miss that started the refill could be to the old
855 # contents of the victim line, since it is a couple of
856 # cycles after the refill starts before we see the updated
857 # cache tag. In that case we don't use the bypass.)
858 comb += use_forward1_next.eq(r1.write_bram)
859 comb += use_forward2_next.eq(0)
860 with m.If((r1.forward_row1 == req_row) & (r1.forward_way1 == hit_way)):
861 comb += use_forward2_next.eq(r1.forward_valid1)
862
863 # The way that matched on a hit
864 comb += req_hit_way.eq(hit_way)
865
866 # The way to replace on a miss
867 with m.If(r1.write_tag):
868 comb += replace_way.eq(plru_victim[r1.store_index])
869 with m.Else():
870 comb += replace_way.eq(r1.store_way)
871
872 # work out whether we have permission for this access
873 # NB we don't yet implement AMR, thus no KUAP
874 comb += rc_ok.eq(perm_attr.reference
875 & (r0.req.load | perm_attr.changed)
876 )
877 comb += perm_ok.eq((r0.req.priv_mode | ~perm_attr.priv) &
878 (perm_attr.wr_perm |
879 (r0.req.load & perm_attr.rd_perm)))
880 comb += access_ok.eq(valid_ra & perm_ok & rc_ok)
881 # Combine the request and cache hit status to decide what
882 # operation needs to be done
883 comb += nc.eq(r0.req.nc | perm_attr.nocache)
884 comb += op.eq(Op.OP_NONE)
885 with m.If(go):
886 with m.If(~access_ok):
887 comb += op.eq(Op.OP_BAD)
888 with m.Elif(cancel_store):
889 comb += op.eq(Op.OP_STCX_FAIL)
890 with m.Else():
891 comb += opsel.eq(Cat(is_hit, nc, r0.req.load))
892 with m.Switch(opsel):
893 with m.Case(0b101):
894 comb += op.eq(Op.OP_LOAD_HIT)
895 with m.Case(0b100):
896 comb += op.eq(Op.OP_LOAD_MISS)
897 with m.Case(0b110):
898 comb += op.eq(Op.OP_LOAD_NC)
899 with m.Case(0b001):
900 comb += op.eq(Op.OP_STORE_HIT)
901 with m.Case(0b000):
902 comb += op.eq(Op.OP_STORE_MISS)
903 with m.Case(0b010):
904 comb += op.eq(Op.OP_STORE_MISS)
905 with m.Case(0b011):
906 comb += op.eq(Op.OP_BAD)
907 with m.Case(0b111):
908 comb += op.eq(Op.OP_BAD)
909 with m.Default():
910 comb += op.eq(Op.OP_NONE)
911 comb += req_op.eq(op)
912 comb += req_go.eq(go)
913
914 # Version of the row number that is valid one cycle earlier
915 # in the cases where we need to read the cache data BRAM.
916 # If we're stalling then we need to keep reading the last
917 # row requested.
918 with m.If(~r0_stall):
919 with m.If(m_in.valid):
920 comb += early_req_row.eq(get_row(m_in.addr))
921 with m.Else():
922 comb += early_req_row.eq(get_row(d_in.addr))
923 with m.Else():
924 comb += early_req_row.eq(req_row)
925
926 def reservation_comb(self, m, cancel_store, set_rsrv, clear_rsrv,
927 r0_valid, r0, reservation):
928 """Handle load-with-reservation and store-conditional instructions
929 """
930 comb = m.d.comb
931 sync = m.d.sync
932
933 with m.If(r0_valid & r0.req.reserve):
934
935 # XXX generate alignment interrupt if address
936 # is not aligned XXX or if r0.req.nc = '1'
937 with m.If(r0.req.load):
938 comb += set_rsrv.eq(1) # load with reservation
939 with m.Else():
940 comb += clear_rsrv.eq(1) # store conditional
941 with m.If(~reservation.valid | r0.req.addr[LINE_OFF_BITS:64]):
942 comb += cancel_store.eq(1)
943
944 def reservation_reg(self, m, r0_valid, access_ok, set_rsrv, clear_rsrv,
945 reservation, r0):
946
947 comb = m.d.comb
948 sync = m.d.sync
949
950 with m.If(r0_valid & access_ok):
951 with m.If(clear_rsrv):
952 sync += reservation.valid.eq(0)
953 with m.Elif(set_rsrv):
954 sync += reservation.valid.eq(1)
955 sync += reservation.addr.eq(r0.req.addr[LINE_OFF_BITS:64])
956
957 def writeback_control(self, m, r1, cache_out):
958 """Return data for loads & completion control logic
959 """
960 comb = m.d.comb
961 sync = m.d.sync
962 d_out, m_out = self.d_out, self.m_out
963
964 data_out = Signal(64)
965 data_fwd = Signal(64)
966
967 # Use the bypass if are reading the row that was
968 # written 1 or 2 cycles ago, including for the
969 # slow_valid = 1 case (i.e. completing a load
970 # miss or a non-cacheable load).
971 with m.If(r1.use_forward1):
972 comb += data_fwd.eq(r1.forward_data1)
973 with m.Else():
974 comb += data_fwd.eq(r1.forward_data2)
975
976 comb += data_out.eq(cache_out[r1.hit_way])
977
978 for i in range(8):
979 with m.If(r1.forward_sel[i]):
980 dsel = data_fwd.word_select(i, 8)
981 comb += data_out.word_select(i, 8).eq(dsel)
982
983 comb += d_out.valid.eq(r1.ls_valid)
984 comb += d_out.data.eq(data_out)
985 comb += d_out.store_done.eq(~r1.stcx_fail)
986 comb += d_out.error.eq(r1.ls_error)
987 comb += d_out.cache_paradox.eq(r1.cache_paradox)
988
989 # Outputs to MMU
990 comb += m_out.done.eq(r1.mmu_done)
991 comb += m_out.err.eq(r1.mmu_error)
992 comb += m_out.data.eq(data_out)
993
994 # We have a valid load or store hit or we just completed
995 # a slow op such as a load miss, a NC load or a store
996 #
997 # Note: the load hit is delayed by one cycle. However it
998 # can still not collide with r.slow_valid (well unless I
999 # miscalculated) because slow_valid can only be set on a
1000 # subsequent request and not on its first cycle (the state
1001 # machine must have advanced), which makes slow_valid
1002 # at least 2 cycles from the previous hit_load_valid.
1003
1004 # Sanity: Only one of these must be set in any given cycle
1005
1006 if False: # TODO: need Display to get this to work
1007 assert (r1.slow_valid & r1.stcx_fail) != 1, \
1008 "unexpected slow_valid collision with stcx_fail"
1009
1010 assert ((r1.slow_valid | r1.stcx_fail) | r1.hit_load_valid) != 1, \
1011 "unexpected hit_load_delayed collision with slow_valid"
1012
1013 with m.If(~r1.mmu_req):
1014 # Request came from loadstore1...
1015 # Load hit case is the standard path
1016 with m.If(r1.hit_load_valid):
1017 #Display(f"completing load hit data={data_out}")
1018 pass
1019
1020 # error cases complete without stalling
1021 with m.If(r1.ls_error):
1022 # Display("completing ld/st with error")
1023 pass
1024
1025 # Slow ops (load miss, NC, stores)
1026 with m.If(r1.slow_valid):
1027 #Display(f"completing store or load miss data={data_out}")
1028 pass
1029
1030 with m.Else():
1031 # Request came from MMU
1032 with m.If(r1.hit_load_valid):
1033 # Display(f"completing load hit to MMU, data={m_out.data}")
1034 pass
1035 # error cases complete without stalling
1036 with m.If(r1.mmu_error):
1037 #Display("combpleting MMU ld with error")
1038 pass
1039
1040 # Slow ops (i.e. load miss)
1041 with m.If(r1.slow_valid):
1042 #Display("completing MMU load miss, data={m_out.data}")
1043 pass
1044
1045 def rams(self, m, r1, early_req_row, cache_out, replace_way):
1046 """rams
1047 Generate a cache RAM for each way. This handles the normal
1048 reads, writes from reloads and the special store-hit update
1049 path as well.
1050
1051 Note: the BRAMs have an extra read buffer, meaning the output
1052 is pipelined an extra cycle. This differs from the
1053 icache. The writeback logic needs to take that into
1054 account by using 1-cycle delayed signals for load hits.
1055 """
1056 comb = m.d.comb
1057 wb_in = self.wb_in
1058
1059 for i in range(NUM_WAYS):
1060 do_read = Signal()
1061 rd_addr = Signal(ROW_BITS)
1062 do_write = Signal()
1063 wr_addr = Signal(ROW_BITS)
1064 wr_data = Signal(WB_DATA_BITS)
1065 wr_sel = Signal(ROW_SIZE)
1066 wr_sel_m = Signal(ROW_SIZE)
1067 _d_out = Signal(WB_DATA_BITS)
1068
1069 way = CacheRam(ROW_BITS, WB_DATA_BITS, True)
1070 setattr(m.submodules, "cacheram_%d" % i, way)
1071
1072 comb += way.rd_en.eq(do_read)
1073 comb += way.rd_addr.eq(rd_addr)
1074 comb += _d_out.eq(way.rd_data_o)
1075 comb += way.wr_sel.eq(wr_sel_m)
1076 comb += way.wr_addr.eq(wr_addr)
1077 comb += way.wr_data.eq(wr_data)
1078
1079 # Cache hit reads
1080 comb += do_read.eq(1)
1081 comb += rd_addr.eq(early_req_row)
1082 comb += cache_out[i].eq(_d_out)
1083
1084 # Write mux:
1085 #
1086 # Defaults to wishbone read responses (cache refill)
1087 #
1088 # For timing, the mux on wr_data/sel/addr is not
1089 # dependent on anything other than the current state.
1090
1091 with m.If(r1.write_bram):
1092 # Write store data to BRAM. This happens one
1093 # cycle after the store is in r0.
1094 comb += wr_data.eq(r1.req.data)
1095 comb += wr_sel.eq(r1.req.byte_sel)
1096 comb += wr_addr.eq(get_row(r1.req.real_addr))
1097
1098 with m.If(i == r1.req.hit_way):
1099 comb += do_write.eq(1)
1100 with m.Else():
1101 # Otherwise, we might be doing a reload or a DCBZ
1102 with m.If(r1.dcbz):
1103 comb += wr_data.eq(0)
1104 with m.Else():
1105 comb += wr_data.eq(wb_in.dat)
1106 comb += wr_addr.eq(r1.store_row)
1107 comb += wr_sel.eq(~0) # all 1s
1108
1109 with m.If((r1.state == State.RELOAD_WAIT_ACK)
1110 & wb_in.ack & (replace_way == i)):
1111 comb += do_write.eq(1)
1112
1113 # Mask write selects with do_write since BRAM
1114 # doesn't have a global write-enable
1115 with m.If(do_write):
1116 comb += wr_sel_m.eq(wr_sel)
1117
1118 # Cache hit synchronous machine for the easy case.
1119 # This handles load hits.
1120 # It also handles error cases (TLB miss, cache paradox)
1121 def dcache_fast_hit(self, m, req_op, r0_valid, r0, r1,
1122 req_hit_way, req_index, req_tag, access_ok,
1123 tlb_hit, tlb_hit_way, tlb_req_index):
1124
1125 comb = m.d.comb
1126 sync = m.d.sync
1127
1128 with m.If(req_op != Op.OP_NONE):
1129 sync += Display("op:%d addr:%x nc: %d idx: %x tag: %x way: %x",
1130 req_op, r0.req.addr, r0.req.nc,
1131 req_index, req_tag, req_hit_way)
1132
1133 with m.If(r0_valid):
1134 sync += r1.mmu_req.eq(r0.mmu_req)
1135
1136 # Fast path for load/store hits.
1137 # Set signals for the writeback controls.
1138 sync += r1.hit_way.eq(req_hit_way)
1139 sync += r1.hit_index.eq(req_index)
1140
1141 with m.If(req_op == Op.OP_LOAD_HIT):
1142 sync += r1.hit_load_valid.eq(1)
1143 with m.Else():
1144 sync += r1.hit_load_valid.eq(0)
1145
1146 with m.If((req_op == Op.OP_LOAD_HIT) | (req_op == Op.OP_STORE_HIT)):
1147 sync += r1.cache_hit.eq(1)
1148 with m.Else():
1149 sync += r1.cache_hit.eq(0)
1150
1151 with m.If(req_op == Op.OP_BAD):
1152 # Display(f"Signalling ld/st error valid_ra={valid_ra}"
1153 # f"rc_ok={rc_ok} perm_ok={perm_ok}"
1154 sync += r1.ls_error.eq(~r0.mmu_req)
1155 sync += r1.mmu_error.eq(r0.mmu_req)
1156 sync += r1.cache_paradox.eq(access_ok)
1157
1158 with m.Else():
1159 sync += r1.ls_error.eq(0)
1160 sync += r1.mmu_error.eq(0)
1161 sync += r1.cache_paradox.eq(0)
1162
1163 with m.If(req_op == Op.OP_STCX_FAIL):
1164 r1.stcx_fail.eq(1)
1165 with m.Else():
1166 sync += r1.stcx_fail.eq(0)
1167
1168 # Record TLB hit information for updating TLB PLRU
1169 sync += r1.tlb_hit.eq(tlb_hit)
1170 sync += r1.tlb_hit_way.eq(tlb_hit_way)
1171 sync += r1.tlb_hit_index.eq(tlb_req_index)
1172
1173 # Memory accesses are handled by this state machine:
1174 #
1175 # * Cache load miss/reload (in conjunction with "rams")
1176 # * Load hits for non-cachable forms
1177 # * Stores (the collision case is handled in "rams")
1178 #
1179 # All wishbone requests generation is done here.
1180 # This machine operates at stage 1.
1181 def dcache_slow(self, m, r1, use_forward1_next, use_forward2_next,
1182 cache_valid_bits, r0, replace_way,
1183 req_hit_way, req_same_tag,
1184 r0_valid, req_op, cache_tag, req_go, ra):
1185
1186 comb = m.d.comb
1187 sync = m.d.sync
1188 wb_in = self.wb_in
1189
1190 req = MemAccessRequest("mreq_ds")
1191 acks = Signal(3)
1192 adjust_acks = Signal(3)
1193 stbs_done = Signal()
1194
1195 sync += r1.use_forward1.eq(use_forward1_next)
1196 sync += r1.forward_sel.eq(0)
1197
1198 with m.If(use_forward1_next):
1199 sync += r1.forward_sel.eq(r1.req.byte_sel)
1200 with m.Elif(use_forward2_next):
1201 sync += r1.forward_sel.eq(r1.forward_sel1)
1202
1203 sync += r1.forward_data2.eq(r1.forward_data1)
1204 with m.If(r1.write_bram):
1205 sync += r1.forward_data1.eq(r1.req.data)
1206 sync += r1.forward_sel1.eq(r1.req.byte_sel)
1207 sync += r1.forward_way1.eq(r1.req.hit_way)
1208 sync += r1.forward_row1.eq(get_row(r1.req.real_addr))
1209 sync += r1.forward_valid1.eq(1)
1210 with m.Else():
1211 with m.If(r1.dcbz):
1212 sync += r1.forward_data1.eq(0)
1213 with m.Else():
1214 sync += r1.forward_data1.eq(wb_in.dat)
1215 sync += r1.forward_sel1.eq(~0) # all 1s
1216 sync += r1.forward_way1.eq(replace_way)
1217 sync += r1.forward_row1.eq(r1.store_row)
1218 sync += r1.forward_valid1.eq(0)
1219
1220 # One cycle pulses reset
1221 sync += r1.slow_valid.eq(0)
1222 sync += r1.write_bram.eq(0)
1223 sync += r1.inc_acks.eq(0)
1224 sync += r1.dec_acks.eq(0)
1225
1226 sync += r1.ls_valid.eq(0)
1227 # complete tlbies and TLB loads in the third cycle
1228 sync += r1.mmu_done.eq(r0_valid & (r0.tlbie | r0.tlbld))
1229
1230 with m.If((req_op == Op.OP_LOAD_HIT)
1231 | (req_op == Op.OP_STCX_FAIL)):
1232 with m.If(~r0.mmu_req):
1233 sync += r1.ls_valid.eq(1)
1234 with m.Else():
1235 sync += r1.mmu_done.eq(1)
1236
1237 with m.If(r1.write_tag):
1238 # Store new tag in selected way
1239 for i in range(NUM_WAYS):
1240 with m.If(i == replace_way):
1241 ct = Signal(TAG_RAM_WIDTH)
1242 comb += ct.eq(cache_tag[r1.store_index])
1243 comb += ct.word_select(i, TAG_WIDTH).eq(r1.reload_tag)
1244 sync += cache_tag[r1.store_index].eq(ct)
1245 sync += r1.store_way.eq(replace_way)
1246 sync += r1.write_tag.eq(0)
1247
1248 # Take request from r1.req if there is one there,
1249 # else from req_op, ra, etc.
1250 with m.If(r1.full):
1251 comb += req.eq(r1.req)
1252 with m.Else():
1253 comb += req.op.eq(req_op)
1254 comb += req.valid.eq(req_go)
1255 comb += req.mmu_req.eq(r0.mmu_req)
1256 comb += req.dcbz.eq(r0.req.dcbz)
1257 comb += req.real_addr.eq(ra)
1258
1259 with m.If(~r0.req.dcbz):
1260 comb += req.data.eq(r0.req.data)
1261 with m.Else():
1262 comb += req.data.eq(0)
1263
1264 # Select all bytes for dcbz
1265 # and for cacheable loads
1266 with m.If(r0.req.dcbz | (r0.req.load & ~r0.req.nc)):
1267 comb += req.byte_sel.eq(~0) # all 1s
1268 with m.Else():
1269 comb += req.byte_sel.eq(r0.req.byte_sel)
1270 comb += req.hit_way.eq(req_hit_way)
1271 comb += req.same_tag.eq(req_same_tag)
1272
1273 # Store the incoming request from r0,
1274 # if it is a slow request
1275 # Note that r1.full = 1 implies req_op = OP_NONE
1276 with m.If((req_op == Op.OP_LOAD_MISS)
1277 | (req_op == Op.OP_LOAD_NC)
1278 | (req_op == Op.OP_STORE_MISS)
1279 | (req_op == Op.OP_STORE_HIT)):
1280 sync += r1.req.eq(req)
1281 sync += r1.full.eq(1)
1282
1283 # Main state machine
1284 with m.Switch(r1.state):
1285
1286 with m.Case(State.IDLE):
1287 # XXX check 'left downto. probably means len(r1.wb.adr)
1288 # r1.wb.adr <= req.real_addr(
1289 # r1.wb.adr'left downto 0
1290 # );
1291 sync += r1.wb.adr.eq(req.real_addr)
1292 sync += r1.wb.sel.eq(req.byte_sel)
1293 sync += r1.wb.dat.eq(req.data)
1294 sync += r1.dcbz.eq(req.dcbz)
1295
1296 # Keep track of our index and way
1297 # for subsequent stores.
1298 sync += r1.store_index.eq(get_index(req.real_addr))
1299 sync += r1.store_row.eq(get_row(req.real_addr))
1300 sync += r1.end_row_ix.eq(
1301 get_row_of_line(get_row(req.real_addr))
1302 )
1303 sync += r1.reload_tag.eq(get_tag(req.real_addr))
1304 sync += r1.req.same_tag.eq(1)
1305
1306 with m.If(req.op == Op.OP_STORE_HIT):
1307 sync += r1.store_way.eq(req.hit_way)
1308
1309 # Reset per-row valid bits,
1310 # ready for handling OP_LOAD_MISS
1311 for i in range(ROW_PER_LINE):
1312 sync += r1.rows_valid[i].eq(0)
1313
1314 with m.If(req_op != Op.OP_NONE):
1315 sync += Display("cache op %d", req.op)
1316
1317 with m.Switch(req.op):
1318 with m.Case(Op.OP_LOAD_HIT):
1319 # stay in IDLE state
1320 pass
1321
1322 with m.Case(Op.OP_LOAD_MISS):
1323 #Display(f"cache miss real addr:" \
1324 # f"{req_real_addr}" \
1325 # f" idx:{get_index(req_real_addr)}" \
1326 # f" tag:{get_tag(req.real_addr)}")
1327 pass
1328
1329 # Start the wishbone cycle
1330 sync += r1.wb.we.eq(0)
1331 sync += r1.wb.cyc.eq(1)
1332 sync += r1.wb.stb.eq(1)
1333
1334 # Track that we had one request sent
1335 sync += r1.state.eq(State.RELOAD_WAIT_ACK)
1336 sync += r1.write_tag.eq(1)
1337
1338 with m.Case(Op.OP_LOAD_NC):
1339 sync += r1.wb.cyc.eq(1)
1340 sync += r1.wb.stb.eq(1)
1341 sync += r1.wb.we.eq(0)
1342 sync += r1.state.eq(State.NC_LOAD_WAIT_ACK)
1343
1344 with m.Case(Op.OP_STORE_HIT, Op.OP_STORE_MISS):
1345 with m.If(~req.dcbz):
1346 sync += r1.state.eq(State.STORE_WAIT_ACK)
1347 sync += r1.acks_pending.eq(1)
1348 sync += r1.full.eq(0)
1349 sync += r1.slow_valid.eq(1)
1350
1351 with m.If(~req.mmu_req):
1352 sync += r1.ls_valid.eq(1)
1353 with m.Else():
1354 sync += r1.mmu_done.eq(1)
1355
1356 with m.If(req.op == Op.OP_STORE_HIT):
1357 sync += r1.write_bram.eq(1)
1358 with m.Else():
1359 sync += r1.state.eq(State.RELOAD_WAIT_ACK)
1360
1361 with m.If(req.op == Op.OP_STORE_MISS):
1362 sync += r1.write_tag.eq(1)
1363
1364 sync += r1.wb.we.eq(1)
1365 sync += r1.wb.cyc.eq(1)
1366 sync += r1.wb.stb.eq(1)
1367
1368 # OP_NONE and OP_BAD do nothing
1369 # OP_BAD & OP_STCX_FAIL were
1370 # handled above already
1371 with m.Case(Op.OP_NONE):
1372 pass
1373 with m.Case(Op.OP_BAD):
1374 pass
1375 with m.Case(Op.OP_STCX_FAIL):
1376 pass
1377
1378 with m.Case(State.RELOAD_WAIT_ACK):
1379 # Requests are all sent if stb is 0
1380 comb += stbs_done.eq(~r1.wb.stb)
1381
1382 with m.If(~wb_in.stall & ~stbs_done):
1383 # That was the last word?
1384 # We are done sending.
1385 # Clear stb and set stbs_done
1386 # so we can handle an eventual
1387 # last ack on the same cycle.
1388 with m.If(is_last_row_addr(
1389 r1.wb.adr, r1.end_row_ix)):
1390 sync += r1.wb.stb.eq(0)
1391 comb += stbs_done.eq(0)
1392
1393 # Calculate the next row address in the current cache line
1394 rarange = r1.wb.adr[ROW_OFF_BITS : LINE_OFF_BITS]
1395 sync += rarange.eq(rarange + 1)
1396
1397 # Incoming acks processing
1398 sync += r1.forward_valid1.eq(wb_in.ack)
1399 with m.If(wb_in.ack):
1400 # XXX needs an Array bit-accessor here
1401 sync += r1.rows_valid[r1.store_row % ROW_PER_LINE].eq(1)
1402
1403 # If this is the data we were looking for,
1404 # we can complete the request next cycle.
1405 # Compare the whole address in case the
1406 # request in r1.req is not the one that
1407 # started this refill.
1408 with m.If(r1.full & r1.req.same_tag &
1409 ((r1.dcbz & r1.req.dcbz) |
1410 (~r1.dcbz & (r1.req.op == Op.OP_LOAD_MISS))) &
1411 (r1.store_row == get_row(r1.req.real_addr))):
1412 sync += r1.full.eq(0)
1413 sync += r1.slow_valid.eq(1)
1414 with m.If(~r1.mmu_req):
1415 sync += r1.ls_valid.eq(1)
1416 with m.Else():
1417 sync += r1.mmu_done.eq(1)
1418 sync += r1.forward_sel.eq(~0) # all 1s
1419 sync += r1.use_forward1.eq(1)
1420
1421 # Check for completion
1422 with m.If(stbs_done & is_last_row(r1.store_row,
1423 r1.end_row_ix)):
1424 # Complete wishbone cycle
1425 sync += r1.wb.cyc.eq(0)
1426
1427 # Cache line is now valid
1428 cv = Signal(INDEX_BITS)
1429 sync += cv.eq(cache_valid_bits[r1.store_index])
1430 sync += cv.bit_select(r1.store_way, 1).eq(1)
1431 sync += r1.state.eq(State.IDLE)
1432
1433 # Increment store row counter
1434 sync += r1.store_row.eq(next_row(r1.store_row))
1435
1436 with m.Case(State.STORE_WAIT_ACK):
1437 comb += stbs_done.eq(~r1.wb.stb)
1438 comb += acks.eq(r1.acks_pending)
1439
1440 with m.If(r1.inc_acks != r1.dec_acks):
1441 with m.If(r1.inc_acks):
1442 comb += adjust_acks.eq(acks + 1)
1443 with m.Else():
1444 comb += adjust_acks.eq(acks - 1)
1445 with m.Else():
1446 comb += adjust_acks.eq(acks)
1447
1448 sync += r1.acks_pending.eq(adjust_acks)
1449
1450 # Clear stb when slave accepted request
1451 with m.If(~wb_in.stall):
1452 # See if there is another store waiting
1453 # to be done which is in the same real page.
1454 with m.If(req.valid):
1455 ra = req.real_addr[0:SET_SIZE_BITS]
1456 sync += r1.wb.adr[0:SET_SIZE_BITS].eq(ra)
1457 sync += r1.wb.dat.eq(req.data)
1458 sync += r1.wb.sel.eq(req.byte_sel)
1459
1460 with m.Elif((adjust_acks < 7) & req.same_tag &
1461 ((req.op == Op.OP_STORE_MISS)
1462 | (req.op == Op.OP_STORE_HIT))):
1463 sync += r1.wb.stb.eq(1)
1464 comb += stbs_done.eq(0)
1465
1466 with m.If(req.op == Op.OP_STORE_HIT):
1467 sync += r1.write_bram.eq(1)
1468 sync += r1.full.eq(0)
1469 sync += r1.slow_valid.eq(1)
1470
1471 # Store requests never come from the MMU
1472 sync += r1.ls_valid.eq(1)
1473 comb += stbs_done.eq(0)
1474 sync += r1.inc_acks.eq(1)
1475 with m.Else():
1476 sync += r1.wb.stb.eq(0)
1477 comb += stbs_done.eq(1)
1478
1479 # Got ack ? See if complete.
1480 with m.If(wb_in.ack):
1481 with m.If(stbs_done & (adjust_acks == 1)):
1482 sync += r1.state.eq(State.IDLE)
1483 sync += r1.wb.cyc.eq(0)
1484 sync += r1.wb.stb.eq(0)
1485 sync += r1.dec_acks.eq(1)
1486
1487 with m.Case(State.NC_LOAD_WAIT_ACK):
1488 # Clear stb when slave accepted request
1489 with m.If(~wb_in.stall):
1490 sync += r1.wb.stb.eq(0)
1491
1492 # Got ack ? complete.
1493 with m.If(wb_in.ack):
1494 sync += r1.state.eq(State.IDLE)
1495 sync += r1.full.eq(0)
1496 sync += r1.slow_valid.eq(1)
1497
1498 with m.If(~r1.mmu_req):
1499 sync += r1.ls_valid.eq(1)
1500 with m.Else():
1501 sync += r1.mmu_done.eq(1)
1502
1503 sync += r1.forward_sel.eq(~0) # all 1s
1504 sync += r1.use_forward1.eq(1)
1505 sync += r1.wb.cyc.eq(0)
1506 sync += r1.wb.stb.eq(0)
1507
1508 def dcache_log(self, m, r1, valid_ra, tlb_hit_way, stall_out):
1509
1510 sync = m.d.sync
1511 d_out, wb_in, log_out = self.d_out, self.wb_in, self.log_out
1512
1513 sync += log_out.eq(Cat(r1.state[:3], valid_ra, tlb_hit_way[:3],
1514 stall_out, req_op[:3], d_out.valid, d_out.error,
1515 r1.wb.cyc, r1.wb.stb, wb_in.ack, wb_in.stall,
1516 r1.wb.adr[3:6]))
1517
1518 def elaborate(self, platform):
1519
1520 m = Module()
1521 comb = m.d.comb
1522
1523 # Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
1524 cache_tags = CacheTagArray()
1525 cache_tag_set = Signal(TAG_RAM_WIDTH)
1526 cache_valid_bits = CacheValidBitsArray()
1527
1528 # TODO attribute ram_style : string;
1529 # TODO attribute ram_style of cache_tags : signal is "distributed";
1530
1531 """note: these are passed to nmigen.hdl.Memory as "attributes".
1532 don't know how, just that they are.
1533 """
1534 dtlb_valid_bits = TLBValidBitsArray()
1535 dtlb_tags = TLBTagsArray()
1536 dtlb_ptes = TLBPtesArray()
1537 # TODO attribute ram_style of
1538 # dtlb_tags : signal is "distributed";
1539 # TODO attribute ram_style of
1540 # dtlb_ptes : signal is "distributed";
1541
1542 r0 = RegStage0("r0")
1543 r0_full = Signal()
1544
1545 r1 = RegStage1("r1")
1546
1547 reservation = Reservation()
1548
1549 # Async signals on incoming request
1550 req_index = Signal(INDEX_BITS)
1551 req_row = Signal(ROW_BITS)
1552 req_hit_way = Signal(WAY_BITS)
1553 req_tag = Signal(TAG_BITS)
1554 req_op = Signal(Op)
1555 req_data = Signal(64)
1556 req_same_tag = Signal()
1557 req_go = Signal()
1558
1559 early_req_row = Signal(ROW_BITS)
1560
1561 cancel_store = Signal()
1562 set_rsrv = Signal()
1563 clear_rsrv = Signal()
1564
1565 r0_valid = Signal()
1566 r0_stall = Signal()
1567
1568 use_forward1_next = Signal()
1569 use_forward2_next = Signal()
1570
1571 cache_out = CacheRamOut()
1572
1573 plru_victim = PLRUOut()
1574 replace_way = Signal(WAY_BITS)
1575
1576 # Wishbone read/write/cache write formatting signals
1577 bus_sel = Signal(8)
1578
1579 # TLB signals
1580 tlb_tag_way = Signal(TLB_TAG_WAY_BITS)
1581 tlb_pte_way = Signal(TLB_PTE_WAY_BITS)
1582 tlb_valid_way = Signal(TLB_NUM_WAYS)
1583 tlb_req_index = Signal(TLB_SET_BITS)
1584 tlb_hit = Signal()
1585 tlb_hit_way = Signal(TLB_WAY_BITS)
1586 pte = Signal(TLB_PTE_BITS)
1587 ra = Signal(REAL_ADDR_BITS)
1588 valid_ra = Signal()
1589 perm_attr = PermAttr("dc_perms")
1590 rc_ok = Signal()
1591 perm_ok = Signal()
1592 access_ok = Signal()
1593
1594 tlb_plru_victim = TLBPLRUOut()
1595
1596 # we don't yet handle collisions between loadstore1 requests
1597 # and MMU requests
1598 comb += self.m_out.stall.eq(0)
1599
1600 # Hold off the request in r0 when r1 has an uncompleted request
1601 comb += r0_stall.eq(r0_full & r1.full)
1602 comb += r0_valid.eq(r0_full & ~r1.full)
1603 comb += self.stall_out.eq(r0_stall)
1604
1605 # Wire up wishbone request latch out of stage 1
1606 comb += self.wb_out.eq(r1.wb)
1607
1608 # call sub-functions putting everything together, using shared
1609 # signals established above
1610 self.stage_0(m, r0, r1, r0_full)
1611 self.tlb_read(m, r0_stall, tlb_valid_way,
1612 tlb_tag_way, tlb_pte_way, dtlb_valid_bits,
1613 dtlb_tags, dtlb_ptes)
1614 self.tlb_search(m, tlb_req_index, r0, r0_valid,
1615 tlb_valid_way, tlb_tag_way, tlb_hit_way,
1616 tlb_pte_way, pte, tlb_hit, valid_ra, perm_attr, ra)
1617 self.tlb_update(m, r0_valid, r0, dtlb_valid_bits, tlb_req_index,
1618 tlb_hit_way, tlb_hit, tlb_plru_victim, tlb_tag_way,
1619 dtlb_tags, tlb_pte_way, dtlb_ptes)
1620 self.maybe_plrus(m, r1, plru_victim)
1621 self.maybe_tlb_plrus(m, r1, tlb_plru_victim)
1622 self.cache_tag_read(m, r0_stall, req_index, cache_tag_set, cache_tags)
1623 self.dcache_request(m, r0, ra, req_index, req_row, req_tag,
1624 r0_valid, r1, cache_valid_bits, replace_way,
1625 use_forward1_next, use_forward2_next,
1626 req_hit_way, plru_victim, rc_ok, perm_attr,
1627 valid_ra, perm_ok, access_ok, req_op, req_go,
1628 tlb_pte_way,
1629 tlb_hit, tlb_hit_way, tlb_valid_way, cache_tag_set,
1630 cancel_store, req_same_tag, r0_stall, early_req_row)
1631 self.reservation_comb(m, cancel_store, set_rsrv, clear_rsrv,
1632 r0_valid, r0, reservation)
1633 self.reservation_reg(m, r0_valid, access_ok, set_rsrv, clear_rsrv,
1634 reservation, r0)
1635 self.writeback_control(m, r1, cache_out)
1636 self.rams(m, r1, early_req_row, cache_out, replace_way)
1637 self.dcache_fast_hit(m, req_op, r0_valid, r0, r1,
1638 req_hit_way, req_index, req_tag, access_ok,
1639 tlb_hit, tlb_hit_way, tlb_req_index)
1640 self.dcache_slow(m, r1, use_forward1_next, use_forward2_next,
1641 cache_valid_bits, r0, replace_way,
1642 req_hit_way, req_same_tag,
1643 r0_valid, req_op, cache_tags, req_go, ra)
1644 #self.dcache_log(m, r1, valid_ra, tlb_hit_way, stall_out)
1645
1646 return m
1647
1648 def dcache_load(dut, addr, nc=0):
1649 yield dut.d_in.load.eq(1)
1650 yield dut.d_in.nc.eq(nc)
1651 yield dut.d_in.addr.eq(addr)
1652 yield dut.d_in.valid.eq(1)
1653 yield
1654 yield dut.d_in.valid.eq(0)
1655 yield
1656 while not (yield dut.d_out.valid):
1657 yield
1658 data = yield dut.d_out.data
1659 return data
1660
1661
1662 def dcache_store(dut, addr, data, nc=0):
1663 yield dut.d_in.load.eq(0)
1664 yield dut.d_in.nc.eq(nc)
1665 yield dut.d_in.data.eq(data)
1666 yield dut.d_in.addr.eq(addr)
1667 yield dut.d_in.valid.eq(1)
1668 yield
1669 yield dut.d_in.valid.eq(0)
1670 yield
1671 while not (yield dut.d_out.valid):
1672 yield
1673
1674
1675 def dcache_sim(dut):
1676 # clear stuff
1677 yield dut.d_in.valid.eq(0)
1678 yield dut.d_in.load.eq(0)
1679 yield dut.d_in.priv_mode.eq(1)
1680 yield dut.d_in.nc.eq(0)
1681 yield dut.d_in.addr.eq(0)
1682 yield dut.d_in.data.eq(0)
1683 yield dut.m_in.valid.eq(0)
1684 yield dut.m_in.addr.eq(0)
1685 yield dut.m_in.pte.eq(0)
1686 # wait 4 * clk_period
1687 yield
1688 yield
1689 yield
1690 yield
1691
1692 # Cacheable read of address 4
1693 data = yield from dcache_load(dut, 0x4)
1694 addr = yield dut.d_in.addr
1695 assert data == 0x0000000100000000, \
1696 f"data @%x=%x expected 0x0000000100000000" % (addr, data)
1697
1698 # Cacheable read of address 30
1699 data = yield from dcache_load(dut, 0x30)
1700 addr = yield dut.d_in.addr
1701 assert data == 0x0000000D0000000C, \
1702 f"data @%x=%x expected 0000000D0000000C" % (addr, data)
1703
1704 # 2nd Cacheable read of address 30
1705 data = yield from dcache_load(dut, 0x30)
1706 addr = yield dut.d_in.addr
1707 assert data == 0x0000000D0000000C, \
1708 f"data @%x=%x expected 0000000D0000000C" % (addr, data)
1709
1710 # Non-cacheable read of address 100
1711 data = yield from dcache_load(dut, 0x100, nc=1)
1712 addr = yield dut.d_in.addr
1713 assert data == 0x0000004100000040, \
1714 f"data @%x=%x expected 0000004100000040" % (addr, data)
1715
1716 # Store at address 30
1717 yield from dcache_store(dut, 0x30, 0x12345678)
1718
1719 yield
1720 yield
1721 yield
1722 yield
1723 yield
1724 yield
1725 yield
1726 yield
1727
1728 # 3nd Cacheable read of address 30
1729 data = yield from dcache_load(dut, 0x30)
1730 addr = yield dut.d_in.addr
1731 assert data == 0x12345678, \
1732 f"data @%x=%x expected 0x12345678" % (addr, data)
1733
1734 yield
1735 yield
1736 yield
1737 yield
1738
1739
1740 def test_dcache():
1741 dut = DCache()
1742 vl = rtlil.convert(dut, ports=[])
1743 with open("test_dcache.il", "w") as f:
1744 f.write(vl)
1745
1746 mem = []
1747 for i in range(0,128):
1748 mem.append((i*2)| ((i*2+1)<<32))
1749 memory = Memory(width=64, depth=16*8, init=mem)
1750 sram = SRAM(memory=memory, granularity=8)
1751
1752 m = Module()
1753 m.submodules.dcache = dut
1754 m.submodules.sram = sram
1755
1756 m.d.comb += sram.bus.cyc.eq(dut.wb_out.cyc)
1757 m.d.comb += sram.bus.stb.eq(dut.wb_out.stb)
1758 m.d.comb += sram.bus.we.eq(dut.wb_out.we)
1759 m.d.comb += sram.bus.sel.eq(dut.wb_out.sel)
1760 m.d.comb += sram.bus.adr.eq(dut.wb_out.adr[3:])
1761 m.d.comb += sram.bus.dat_w.eq(dut.wb_out.dat)
1762
1763 m.d.comb += dut.wb_in.ack.eq(sram.bus.ack)
1764 m.d.comb += dut.wb_in.dat.eq(sram.bus.dat_r)
1765
1766 # nmigen Simulation
1767 sim = Simulator(m)
1768 sim.add_clock(1e-6)
1769
1770 sim.add_sync_process(wrap(dcache_sim(dut)))
1771 with sim.write_vcd('test_dcache.vcd'):
1772 sim.run()
1773
1774 if __name__ == '__main__':
1775 test_dcache()
1776