3 based on Anton Blanchard microwatt dcache.vhdl
7 from enum
import Enum
, unique
9 from nmigen
import Module
, Signal
, Elaboratable
, Cat
, Repl
, Array
, Const
11 from nmigen
.hdl
.ast
import Display
16 from random
import randint
18 from nmigen
.cli
import main
19 from nmutil
.iocontrol
import RecordObject
20 from nmutil
.util
import wrap
21 from nmigen
.utils
import log2_int
22 from soc
.experiment
.mem_types
import (LoadStore1ToDCacheType
,
23 DCacheToLoadStore1Type
,
27 from soc
.experiment
.wb_types
import (WB_ADDR_BITS
, WB_DATA_BITS
, WB_SEL_BITS
,
28 WBAddrType
, WBDataType
, WBSelType
,
29 WBMasterOut
, WBSlaveOut
,
30 WBMasterOutVector
, WBSlaveOutVector
,
31 WBIOMasterOut
, WBIOSlaveOut
)
33 from soc
.experiment
.cache_ram
import CacheRam
34 from soc
.experiment
.plru
import PLRU
37 from nmigen_soc
.wishbone
.sram
import SRAM
38 from nmigen
import Memory
39 from nmigen
.cli
import rtlil
41 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
43 from nmigen
.sim
.cxxsim
import Simulator
, Delay
, Settle
46 # TODO: make these parameters of DCache at some point
47 LINE_SIZE
= 64 # Line size in bytes
48 NUM_LINES
= 16 # Number of lines in a set
49 NUM_WAYS
= 4 # Number of ways
50 TLB_SET_SIZE
= 64 # L1 DTLB entries per set
51 TLB_NUM_WAYS
= 2 # L1 DTLB number of sets
52 TLB_LG_PGSZ
= 12 # L1 DTLB log_2(page_size)
53 LOG_LENGTH
= 0 # Non-zero to enable log data collection
55 # BRAM organisation: We never access more than
56 # -- WB_DATA_BITS at a time so to save
57 # -- resources we make the array only that wide, and
58 # -- use consecutive indices for to make a cache "line"
60 # -- ROW_SIZE is the width in bytes of the BRAM
61 # -- (based on WB, so 64-bits)
62 ROW_SIZE
= WB_DATA_BITS
// 8;
64 # ROW_PER_LINE is the number of row (wishbone
65 # transactions) in a line
66 ROW_PER_LINE
= LINE_SIZE
// ROW_SIZE
68 # BRAM_ROWS is the number of rows in BRAM needed
69 # to represent the full dcache
70 BRAM_ROWS
= NUM_LINES
* ROW_PER_LINE
73 # Bit fields counts in the address
75 # REAL_ADDR_BITS is the number of real address
79 # ROW_BITS is the number of bits to select a row
80 ROW_BITS
= log2_int(BRAM_ROWS
)
82 # ROW_LINE_BITS is the number of bits to select
84 ROW_LINE_BITS
= log2_int(ROW_PER_LINE
)
86 # LINE_OFF_BITS is the number of bits for
87 # the offset in a cache line
88 LINE_OFF_BITS
= log2_int(LINE_SIZE
)
90 # ROW_OFF_BITS is the number of bits for
92 ROW_OFF_BITS
= log2_int(ROW_SIZE
)
94 # INDEX_BITS is the number if bits to
96 INDEX_BITS
= log2_int(NUM_LINES
)
98 # SET_SIZE_BITS is the log base 2 of the set size
99 SET_SIZE_BITS
= LINE_OFF_BITS
+ INDEX_BITS
101 # TAG_BITS is the number of bits of
102 # the tag part of the address
103 TAG_BITS
= REAL_ADDR_BITS
- SET_SIZE_BITS
105 # TAG_WIDTH is the width in bits of each way of the tag RAM
106 TAG_WIDTH
= TAG_BITS
+ 7 - ((TAG_BITS
+ 7) % 8)
108 # WAY_BITS is the number of bits to select a way
109 WAY_BITS
= log2_int(NUM_WAYS
)
111 # Example of layout for 32 lines of 64 bytes:
113 # .. tag |index| line |
115 # .. | |---| | ROW_LINE_BITS (3)
116 # .. | |--- - --| LINE_OFF_BITS (6)
117 # .. | |- --| ROW_OFF_BITS (3)
118 # .. |----- ---| | ROW_BITS (8)
119 # .. |-----| | INDEX_BITS (5)
120 # .. --------| | TAG_BITS (45)
122 TAG_RAM_WIDTH
= TAG_WIDTH
* NUM_WAYS
125 return Array(Signal(TAG_RAM_WIDTH
, name
="cachetag_%d" % x
) \
126 for x
in range(NUM_LINES
))
128 def CacheValidBitsArray():
129 return Array(Signal(INDEX_BITS
, name
="cachevalid_%d" % x
) \
130 for x
in range(NUM_LINES
))
132 def RowPerLineValidArray():
133 return Array(Signal(name
="rows_valid%d" % x
) \
134 for x
in range(ROW_PER_LINE
))
137 TLB_SET_BITS
= log2_int(TLB_SET_SIZE
)
138 TLB_WAY_BITS
= log2_int(TLB_NUM_WAYS
)
139 TLB_EA_TAG_BITS
= 64 - (TLB_LG_PGSZ
+ TLB_SET_BITS
)
140 TLB_TAG_WAY_BITS
= TLB_NUM_WAYS
* TLB_EA_TAG_BITS
142 TLB_PTE_WAY_BITS
= TLB_NUM_WAYS
* TLB_PTE_BITS
;
144 assert (LINE_SIZE
% ROW_SIZE
) == 0, "LINE_SIZE not multiple of ROW_SIZE"
145 assert (LINE_SIZE
% 2) == 0, "LINE_SIZE not power of 2"
146 assert (NUM_LINES
% 2) == 0, "NUM_LINES not power of 2"
147 assert (ROW_PER_LINE
% 2) == 0, "ROW_PER_LINE not power of 2"
148 assert ROW_BITS
== (INDEX_BITS
+ ROW_LINE_BITS
), "geometry bits don't add up"
149 assert (LINE_OFF_BITS
== ROW_OFF_BITS
+ ROW_LINE_BITS
), \
150 "geometry bits don't add up"
151 assert REAL_ADDR_BITS
== (TAG_BITS
+ INDEX_BITS
+ LINE_OFF_BITS
), \
152 "geometry bits don't add up"
153 assert REAL_ADDR_BITS
== (TAG_BITS
+ ROW_BITS
+ ROW_OFF_BITS
), \
154 "geometry bits don't add up"
155 assert 64 == WB_DATA_BITS
, "Can't yet handle wb width that isn't 64-bits"
156 assert SET_SIZE_BITS
<= TLB_LG_PGSZ
, "Set indexed by virtual address"
159 def TLBValidBitsArray():
160 return Array(Signal(TLB_NUM_WAYS
) for x
in range(TLB_SET_SIZE
))
163 return Array(Signal(TLB_EA_TAG_BITS
) for x
in range (TLB_NUM_WAYS
))
166 return Array(Signal(TLB_TAG_WAY_BITS
) for x
in range (TLB_SET_SIZE
))
169 return Array(Signal(TLB_PTE_WAY_BITS
) for x
in range(TLB_SET_SIZE
))
172 return Array(Signal(WAY_BITS
, name
="hitway_%d" % x
) \
173 for x
in range(TLB_NUM_WAYS
))
175 # Cache RAM interface
177 return Array(Signal(WB_DATA_BITS
, name
="cache_out%d" % x
) \
178 for x
in range(NUM_WAYS
))
180 # PLRU output interface
182 return Array(Signal(WAY_BITS
) for x
in range(NUM_LINES
))
184 # TLB PLRU output interface
186 return Array(Signal(TLB_WAY_BITS
) for x
in range(TLB_SET_SIZE
))
188 # Helper functions to decode incoming requests
190 # Return the cache line index (tag index) for an address
192 return addr
[LINE_OFF_BITS
:SET_SIZE_BITS
]
194 # Return the cache row index (data memory) for an address
196 return addr
[ROW_OFF_BITS
:SET_SIZE_BITS
]
198 # Return the index of a row within a line
199 def get_row_of_line(row
):
200 return row
[:ROW_LINE_BITS
]
202 # Returns whether this is the last row of a line
203 def is_last_row_addr(addr
, last
):
204 return addr
[ROW_OFF_BITS
:LINE_OFF_BITS
] == last
206 # Returns whether this is the last row of a line
207 def is_last_row(row
, last
):
208 return get_row_of_line(row
) == last
210 # Return the next row in the current cache line. We use a
211 # dedicated function in order to limit the size of the
212 # generated adder to be only the bits within a cache line
213 # (3 bits with default settings)
215 row_v
= row
[0:ROW_LINE_BITS
] + 1
216 return Cat(row_v
[:ROW_LINE_BITS
], row
[ROW_LINE_BITS
:])
218 # Get the tag value from the address
220 return addr
[SET_SIZE_BITS
:REAL_ADDR_BITS
]
222 # Read a tag from a tag memory row
223 def read_tag(way
, tagset
):
224 return tagset
.word_select(way
, TAG_WIDTH
)[:TAG_BITS
]
226 # Read a TLB tag from a TLB tag memory row
227 def read_tlb_tag(way
, tags
):
228 return tags
.word_select(way
, TLB_EA_TAG_BITS
)
230 # Write a TLB tag to a TLB tag memory row
231 def write_tlb_tag(way
, tags
, tag
):
232 return read_tlb_tag(way
, tags
).eq(tag
)
234 # Read a PTE from a TLB PTE memory row
235 def read_tlb_pte(way
, ptes
):
236 return ptes
.word_select(way
, TLB_PTE_BITS
)
238 def write_tlb_pte(way
, ptes
, newpte
):
239 return read_tlb_pte(way
, ptes
).eq(newpte
)
242 # Record for storing permission, attribute, etc. bits from a PTE
243 class PermAttr(RecordObject
):
244 def __init__(self
, name
=None):
245 super().__init
__(name
=name
)
246 self
.reference
= Signal()
247 self
.changed
= Signal()
248 self
.nocache
= Signal()
250 self
.rd_perm
= Signal()
251 self
.wr_perm
= Signal()
254 def extract_perm_attr(pte
):
256 pa
.reference
= pte
[8]
265 # Type of operation on a "valid" input
269 OP_BAD
= 1 # NC cache hit, TLB miss, prot/RC failure
270 OP_STCX_FAIL
= 2 # conditional store w/o reservation
271 OP_LOAD_HIT
= 3 # Cache hit on load
272 OP_LOAD_MISS
= 4 # Load missing cache
273 OP_LOAD_NC
= 5 # Non-cachable load
274 OP_STORE_HIT
= 6 # Store hitting cache
275 OP_STORE_MISS
= 7 # Store missing cache
278 # Cache state machine
281 IDLE
= 0 # Normal load hit processing
282 RELOAD_WAIT_ACK
= 1 # Cache reload wait ack
283 STORE_WAIT_ACK
= 2 # Store wait ack
284 NC_LOAD_WAIT_ACK
= 3 # Non-cachable load wait ack
289 # In order to make timing, we use the BRAMs with
290 # an output buffer, which means that the BRAM
291 # output is delayed by an extra cycle.
293 # Thus, the dcache has a 2-stage internal pipeline
294 # for cache hits with no stalls.
296 # All other operations are handled via stalling
297 # in the first stage.
299 # The second stage can thus complete a hit at the same
300 # time as the first stage emits a stall for a complex op.
302 # Stage 0 register, basically contains just the latched request
304 class RegStage0(RecordObject
):
305 def __init__(self
, name
=None):
306 super().__init
__(name
=name
)
307 self
.req
= LoadStore1ToDCacheType(name
="lsmem")
308 self
.tlbie
= Signal()
309 self
.doall
= Signal()
310 self
.tlbld
= Signal()
311 self
.mmu_req
= Signal() # indicates source of request
314 class MemAccessRequest(RecordObject
):
315 def __init__(self
, name
=None):
316 super().__init
__(name
=name
)
318 self
.valid
= Signal()
320 self
.real_addr
= Signal(REAL_ADDR_BITS
)
321 self
.data
= Signal(64)
322 self
.byte_sel
= Signal(8)
323 self
.hit_way
= Signal(WAY_BITS
)
324 self
.same_tag
= Signal()
325 self
.mmu_req
= Signal()
328 # First stage register, contains state for stage 1 of load hits
329 # and for the state machine used by all other operations
330 class RegStage1(RecordObject
):
331 def __init__(self
, name
=None):
332 super().__init
__(name
=name
)
333 # Info about the request
334 self
.full
= Signal() # have uncompleted request
335 self
.mmu_req
= Signal() # request is from MMU
336 self
.req
= MemAccessRequest(name
="reqmem")
339 self
.hit_way
= Signal(WAY_BITS
)
340 self
.hit_load_valid
= Signal()
341 self
.hit_index
= Signal(INDEX_BITS
)
342 self
.cache_hit
= Signal()
345 self
.tlb_hit
= Signal()
346 self
.tlb_hit_way
= Signal(TLB_NUM_WAYS
)
347 self
.tlb_hit_index
= Signal(TLB_WAY_BITS
)
349 # 2-stage data buffer for data forwarded from writes to reads
350 self
.forward_data1
= Signal(64)
351 self
.forward_data2
= Signal(64)
352 self
.forward_sel1
= Signal(8)
353 self
.forward_valid1
= Signal()
354 self
.forward_way1
= Signal(WAY_BITS
)
355 self
.forward_row1
= Signal(ROW_BITS
)
356 self
.use_forward1
= Signal()
357 self
.forward_sel
= Signal(8)
359 # Cache miss state (reload state machine)
360 self
.state
= Signal(State
)
362 self
.write_bram
= Signal()
363 self
.write_tag
= Signal()
364 self
.slow_valid
= Signal()
365 self
.wb
= WBMasterOut()
366 self
.reload_tag
= Signal(TAG_BITS
)
367 self
.store_way
= Signal(WAY_BITS
)
368 self
.store_row
= Signal(ROW_BITS
)
369 self
.store_index
= Signal(INDEX_BITS
)
370 self
.end_row_ix
= Signal(ROW_LINE_BITS
)
371 self
.rows_valid
= RowPerLineValidArray()
372 self
.acks_pending
= Signal(3)
373 self
.inc_acks
= Signal()
374 self
.dec_acks
= Signal()
376 # Signals to complete (possibly with error)
377 self
.ls_valid
= Signal()
378 self
.ls_error
= Signal()
379 self
.mmu_done
= Signal()
380 self
.mmu_error
= Signal()
381 self
.cache_paradox
= Signal()
383 # Signal to complete a failed stcx.
384 self
.stcx_fail
= Signal()
387 # Reservation information
388 class Reservation(RecordObject
):
391 self
.valid
= Signal()
392 self
.addr
= Signal(64-LINE_OFF_BITS
)
395 class DTLBUpdate(Elaboratable
):
397 self
.tlbie
= Signal()
398 self
.tlbwe
= Signal()
399 self
.doall
= Signal()
400 self
.updated
= Signal()
401 self
.v_updated
= Signal()
402 self
.tlb_hit
= Signal()
403 self
.tlb_req_index
= Signal(TLB_SET_BITS
)
405 self
.tlb_hit_way
= Signal(TLB_WAY_BITS
)
406 self
.tlb_tag_way
= Signal(TLB_TAG_WAY_BITS
)
407 self
.tlb_pte_way
= Signal(TLB_PTE_WAY_BITS
)
408 self
.repl_way
= Signal(TLB_WAY_BITS
)
409 self
.eatag
= Signal(TLB_EA_TAG_BITS
)
410 self
.pte_data
= Signal(TLB_PTE_BITS
)
412 self
.dv
= Signal(TLB_PTE_WAY_BITS
)
414 self
.tb_out
= Signal(TLB_TAG_WAY_BITS
)
415 self
.pb_out
= Signal(TLB_NUM_WAYS
)
416 self
.db_out
= Signal(TLB_PTE_WAY_BITS
)
418 def elaborate(self
, platform
):
423 tagset
= Signal(TLB_TAG_WAY_BITS
)
424 pteset
= Signal(TLB_PTE_WAY_BITS
)
426 tb_out
, pb_out
, db_out
= self
.tb_out
, self
.pb_out
, self
.db_out
428 with m
.If(self
.tlbie
& self
.doall
):
429 pass # clear all back in parent
430 with m
.Elif(self
.tlbie
):
431 with m
.If(self
.tlb_hit
):
432 comb
+= db_out
.eq(self
.dv
)
433 comb
+= db_out
.bit_select(self
.tlb_hit_way
, 1).eq(1)
434 comb
+= self
.v_updated
.eq(1)
436 with m
.Elif(self
.tlbwe
):
438 comb
+= tagset
.eq(self
.tlb_tag_way
)
439 comb
+= write_tlb_tag(self
.repl_way
, tagset
, self
.eatag
)
440 comb
+= tb_out
.eq(tagset
)
442 comb
+= pteset
.eq(self
.tlb_pte_way
)
443 comb
+= write_tlb_pte(self
.repl_way
, pteset
, self
.pte_data
)
444 comb
+= pb_out
.eq(pteset
)
446 comb
+= db_out
.bit_select(self
.repl_way
, 1).eq(1)
448 comb
+= self
.updated
.eq(1)
449 comb
+= self
.v_updated
.eq(1)
453 def dcache_request(self
, m
, r0
, ra
, req_index
, req_row
, req_tag
,
454 r0_valid
, r1
, cache_valid_bits
, replace_way
,
455 use_forward1_next
, use_forward2_next
,
456 req_hit_way
, plru_victim
, rc_ok
, perm_attr
,
457 valid_ra
, perm_ok
, access_ok
, req_op
, req_go
,
459 tlb_hit
, tlb_hit_way
, tlb_valid_way
, cache_tag_set
,
460 cancel_store
, req_same_tag
, r0_stall
, early_req_row
):
461 """Cache request parsing and hit detection
464 class DCachePendingHit(Elaboratable
):
466 def __init__(self
, tlb_pte_way
, tlb_valid_way
, tlb_hit_way
,
467 cache_valid_idx
, cache_tag_set
,
472 self
.virt_mode
= Signal()
473 self
.is_hit
= Signal()
474 self
.tlb_hit
= Signal()
475 self
.hit_way
= Signal(WAY_BITS
)
476 self
.rel_match
= Signal()
477 self
.req_index
= Signal(INDEX_BITS
)
478 self
.reload_tag
= Signal(TAG_BITS
)
480 self
.tlb_hit_way
= tlb_hit_way
481 self
.tlb_pte_way
= tlb_pte_way
482 self
.tlb_valid_way
= tlb_valid_way
483 self
.cache_valid_idx
= cache_valid_idx
484 self
.cache_tag_set
= cache_tag_set
485 self
.req_addr
= req_addr
486 self
.hit_set
= hit_set
488 def elaborate(self
, platform
):
494 virt_mode
= self
.virt_mode
496 tlb_pte_way
= self
.tlb_pte_way
497 tlb_valid_way
= self
.tlb_valid_way
498 cache_valid_idx
= self
.cache_valid_idx
499 cache_tag_set
= self
.cache_tag_set
500 req_addr
= self
.req_addr
501 tlb_hit_way
= self
.tlb_hit_way
502 tlb_hit
= self
.tlb_hit
503 hit_set
= self
.hit_set
504 hit_way
= self
.hit_way
505 rel_match
= self
.rel_match
506 req_index
= self
.req_index
507 reload_tag
= self
.reload_tag
509 rel_matches
= Array(Signal(name
="rel_matches_%d" % i
) \
510 for i
in range(TLB_NUM_WAYS
))
511 hit_way_set
= HitWaySet()
513 # Test if pending request is a hit on any way
514 # In order to make timing in virtual mode,
515 # when we are using the TLB, we compare each
516 # way with each of the real addresses from each way of
517 # the TLB, and then decide later which match to use.
519 with m
.If(virt_mode
):
520 for j
in range(TLB_NUM_WAYS
):
521 s_tag
= Signal(TAG_BITS
, name
="s_tag%d" % j
)
523 s_pte
= Signal(TLB_PTE_BITS
)
524 s_ra
= Signal(REAL_ADDR_BITS
)
525 comb
+= s_pte
.eq(read_tlb_pte(j
, tlb_pte_way
))
526 comb
+= s_ra
.eq(Cat(req_addr
[0:TLB_LG_PGSZ
],
527 s_pte
[TLB_LG_PGSZ
:REAL_ADDR_BITS
]))
528 comb
+= s_tag
.eq(get_tag(s_ra
))
530 for i
in range(NUM_WAYS
):
531 is_tag_hit
= Signal(name
="is_tag_hit_%d_%d" % (j
, i
))
532 comb
+= is_tag_hit
.eq(go
& cache_valid_idx
[i
] &
533 (read_tag(i
, cache_tag_set
) == s_tag
)
535 with m
.If(is_tag_hit
):
536 comb
+= hit_way_set
[j
].eq(i
)
538 comb
+= hit_set
[j
].eq(s_hit
)
539 with m
.If(s_tag
== reload_tag
):
540 comb
+= rel_matches
[j
].eq(1)
542 comb
+= is_hit
.eq(hit_set
[tlb_hit_way
])
543 comb
+= hit_way
.eq(hit_way_set
[tlb_hit_way
])
544 comb
+= rel_match
.eq(rel_matches
[tlb_hit_way
])
546 s_tag
= Signal(TAG_BITS
)
547 comb
+= s_tag
.eq(get_tag(req_addr
))
548 for i
in range(NUM_WAYS
):
549 is_tag_hit
= Signal(name
="is_tag_hit_%d" % i
)
550 comb
+= is_tag_hit
.eq(go
& cache_valid_idx
[i
] &
551 (read_tag(i
, cache_tag_set
) == s_tag
))
552 with m
.If(is_tag_hit
):
553 comb
+= hit_way
.eq(i
)
555 with m
.If(s_tag
== reload_tag
):
556 comb
+= rel_match
.eq(1)
561 class DCache(Elaboratable
):
562 """Set associative dcache write-through
563 TODO (in no specific order):
564 * See list in icache.vhdl
565 * Complete load misses on the cycle when WB data comes instead of
566 at the end of line (this requires dealing with requests coming in
570 self
.d_in
= LoadStore1ToDCacheType("d_in")
571 self
.d_out
= DCacheToLoadStore1Type("d_out")
573 self
.m_in
= MMUToDCacheType("m_in")
574 self
.m_out
= DCacheToMMUType("m_out")
576 self
.stall_out
= Signal()
578 self
.wb_out
= WBMasterOut()
579 self
.wb_in
= WBSlaveOut()
581 self
.log_out
= Signal(20)
583 def stage_0(self
, m
, r0
, r1
, r0_full
):
584 """Latch the request in r0.req as long as we're not stalling
588 d_in
, d_out
, m_in
= self
.d_in
, self
.d_out
, self
.m_in
590 r
= RegStage0("stage0")
592 # TODO, this goes in unit tests and formal proofs
593 with m
.If(~
(d_in
.valid
& m_in
.valid
)):
594 #sync += Display("request collision loadstore vs MMU")
597 with m
.If(m_in
.valid
):
598 sync
+= r
.req
.valid
.eq(1)
599 sync
+= r
.req
.load
.eq(~
(m_in
.tlbie | m_in
.tlbld
))
600 sync
+= r
.req
.dcbz
.eq(0)
601 sync
+= r
.req
.nc
.eq(0)
602 sync
+= r
.req
.reserve
.eq(0)
603 sync
+= r
.req
.virt_mode
.eq(1)
604 sync
+= r
.req
.priv_mode
.eq(1)
605 sync
+= r
.req
.addr
.eq(m_in
.addr
)
606 sync
+= r
.req
.data
.eq(m_in
.pte
)
607 sync
+= r
.req
.byte_sel
.eq(~
0) # Const -1 sets all to 0b111....
608 sync
+= r
.tlbie
.eq(m_in
.tlbie
)
609 sync
+= r
.doall
.eq(m_in
.doall
)
610 sync
+= r
.tlbld
.eq(m_in
.tlbld
)
611 sync
+= r
.mmu_req
.eq(1)
613 sync
+= r
.req
.eq(d_in
)
614 sync
+= r
.tlbie
.eq(0)
615 sync
+= r
.doall
.eq(0)
616 sync
+= r
.tlbld
.eq(0)
617 sync
+= r
.mmu_req
.eq(0)
618 with m
.If(~
(r1
.full
& r0_full
)):
620 sync
+= r0_full
.eq(r
.req
.valid
)
622 def tlb_read(self
, m
, r0_stall
, tlb_valid_way
,
623 tlb_tag_way
, tlb_pte_way
, dtlb_valid_bits
,
624 dtlb_tags
, dtlb_ptes
):
626 Operates in the second cycle on the request latched in r0.req.
627 TLB updates write the entry at the end of the second cycle.
631 m_in
, d_in
= self
.m_in
, self
.d_in
633 index
= Signal(TLB_SET_BITS
)
634 addrbits
= Signal(TLB_SET_BITS
)
637 amax
= TLB_LG_PGSZ
+ TLB_SET_BITS
639 with m
.If(m_in
.valid
):
640 comb
+= addrbits
.eq(m_in
.addr
[amin
: amax
])
642 comb
+= addrbits
.eq(d_in
.addr
[amin
: amax
])
643 comb
+= index
.eq(addrbits
)
645 # If we have any op and the previous op isn't finished,
646 # then keep the same output for next cycle.
647 with m
.If(~r0_stall
):
648 sync
+= tlb_valid_way
.eq(dtlb_valid_bits
[index
])
649 sync
+= tlb_tag_way
.eq(dtlb_tags
[index
])
650 sync
+= tlb_pte_way
.eq(dtlb_ptes
[index
])
652 def maybe_tlb_plrus(self
, m
, r1
, tlb_plru_victim
):
653 """Generate TLB PLRUs
658 if TLB_NUM_WAYS
== 0:
660 for i
in range(TLB_SET_SIZE
):
662 tlb_plru
= PLRU(WAY_BITS
)
663 setattr(m
.submodules
, "maybe_plru_%d" % i
, tlb_plru
)
664 tlb_plru_acc_en
= Signal()
666 comb
+= tlb_plru_acc_en
.eq(r1
.tlb_hit
& (r1
.tlb_hit_index
== i
))
667 comb
+= tlb_plru
.acc_en
.eq(tlb_plru_acc_en
)
668 comb
+= tlb_plru
.acc
.eq(r1
.tlb_hit_way
)
669 comb
+= tlb_plru_victim
[i
].eq(tlb_plru
.lru_o
)
671 def tlb_search(self
, m
, tlb_req_index
, r0
, r0_valid
,
672 tlb_valid_way
, tlb_tag_way
, tlb_hit_way
,
673 tlb_pte_way
, pte
, tlb_hit
, valid_ra
, perm_attr
, ra
):
678 hitway
= Signal(TLB_WAY_BITS
)
680 eatag
= Signal(TLB_EA_TAG_BITS
)
682 TLB_LG_END
= TLB_LG_PGSZ
+ TLB_SET_BITS
683 comb
+= tlb_req_index
.eq(r0
.req
.addr
[TLB_LG_PGSZ
: TLB_LG_END
])
684 comb
+= eatag
.eq(r0
.req
.addr
[TLB_LG_END
: 64 ])
686 for i
in range(TLB_NUM_WAYS
):
687 is_tag_hit
= Signal()
688 comb
+= is_tag_hit
.eq(tlb_valid_way
[i
]
689 & read_tlb_tag(i
, tlb_tag_way
) == eatag
)
690 with m
.If(is_tag_hit
):
694 comb
+= tlb_hit
.eq(hit
& r0_valid
)
695 comb
+= tlb_hit_way
.eq(hitway
)
698 comb
+= pte
.eq(read_tlb_pte(hitway
, tlb_pte_way
))
701 comb
+= valid_ra
.eq(tlb_hit | ~r0
.req
.virt_mode
)
702 with m
.If(r0
.req
.virt_mode
):
703 comb
+= ra
.eq(Cat(Const(0, ROW_OFF_BITS
),
704 r0
.req
.addr
[ROW_OFF_BITS
:TLB_LG_PGSZ
],
705 pte
[TLB_LG_PGSZ
:REAL_ADDR_BITS
]))
706 comb
+= perm_attr
.eq(extract_perm_attr(pte
))
708 comb
+= ra
.eq(Cat(Const(0, ROW_OFF_BITS
),
709 r0
.req
.addr
[ROW_OFF_BITS
:REAL_ADDR_BITS
]))
711 comb
+= perm_attr
.reference
.eq(1)
712 comb
+= perm_attr
.changed
.eq(1)
713 comb
+= perm_attr
.nocache
.eq(0)
714 comb
+= perm_attr
.priv
.eq(1)
715 comb
+= perm_attr
.rd_perm
.eq(1)
716 comb
+= perm_attr
.wr_perm
.eq(1)
718 def tlb_update(self
, m
, r0_valid
, r0
, dtlb_valid_bits
, tlb_req_index
,
719 tlb_hit_way
, tlb_hit
, tlb_plru_victim
, tlb_tag_way
,
720 dtlb_tags
, tlb_pte_way
, dtlb_ptes
):
728 comb
+= tlbie
.eq(r0_valid
& r0
.tlbie
)
729 comb
+= tlbwe
.eq(r0_valid
& r0
.tlbld
)
731 m
.submodules
.tlb_update
= d
= DTLBUpdate()
732 with m
.If(tlbie
& r0
.doall
):
733 # clear all valid bits at once
734 for i
in range(TLB_SET_SIZE
):
735 sync
+= dtlb_valid_bits
[i
].eq(0)
736 with m
.If(d
.updated
):
737 sync
+= dtlb_tags
[tlb_req_index
].eq(d
.tb_out
)
738 sync
+= dtlb_ptes
[tlb_req_index
].eq(d
.pb_out
)
739 with m
.If(d
.v_updated
):
740 sync
+= dtlb_valid_bits
[tlb_req_index
].eq(d
.db_out
)
742 comb
+= d
.dv
.eq(dtlb_valid_bits
[tlb_req_index
])
744 comb
+= d
.tlbie
.eq(tlbie
)
745 comb
+= d
.tlbwe
.eq(tlbwe
)
746 comb
+= d
.doall
.eq(r0
.doall
)
747 comb
+= d
.tlb_hit
.eq(tlb_hit
)
748 comb
+= d
.tlb_hit_way
.eq(tlb_hit_way
)
749 comb
+= d
.tlb_tag_way
.eq(tlb_tag_way
)
750 comb
+= d
.tlb_pte_way
.eq(tlb_pte_way
)
751 comb
+= d
.tlb_req_index
.eq(tlb_req_index
)
754 comb
+= d
.repl_way
.eq(tlb_hit_way
)
756 comb
+= d
.repl_way
.eq(tlb_plru_victim
[tlb_req_index
])
757 comb
+= d
.eatag
.eq(r0
.req
.addr
[TLB_LG_PGSZ
+ TLB_SET_BITS
:64])
758 comb
+= d
.pte_data
.eq(r0
.req
.data
)
760 def maybe_plrus(self
, m
, r1
, plru_victim
):
766 if TLB_NUM_WAYS
== 0:
769 for i
in range(NUM_LINES
):
771 plru
= PLRU(WAY_BITS
)
772 setattr(m
.submodules
, "plru%d" % i
, plru
)
773 plru_acc_en
= Signal()
775 comb
+= plru_acc_en
.eq(r1
.cache_hit
& (r1
.hit_index
== i
))
776 comb
+= plru
.acc_en
.eq(plru_acc_en
)
777 comb
+= plru
.acc
.eq(r1
.hit_way
)
778 comb
+= plru_victim
[i
].eq(plru
.lru_o
)
780 def cache_tag_read(self
, m
, r0_stall
, req_index
, cache_tag_set
, cache_tags
):
781 """Cache tag RAM read port
785 m_in
, d_in
= self
.m_in
, self
.d_in
787 index
= Signal(INDEX_BITS
)
790 comb
+= index
.eq(req_index
)
791 with m
.Elif(m_in
.valid
):
792 comb
+= index
.eq(get_index(m_in
.addr
))
794 comb
+= index
.eq(get_index(d_in
.addr
))
795 sync
+= cache_tag_set
.eq(cache_tags
[index
])
797 def dcache_request(self
, m
, r0
, ra
, req_index
, req_row
, req_tag
,
798 r0_valid
, r1
, cache_valid_bits
, replace_way
,
799 use_forward1_next
, use_forward2_next
,
800 req_hit_way
, plru_victim
, rc_ok
, perm_attr
,
801 valid_ra
, perm_ok
, access_ok
, req_op
, req_go
,
803 tlb_hit
, tlb_hit_way
, tlb_valid_way
, cache_tag_set
,
804 cancel_store
, req_same_tag
, r0_stall
, early_req_row
):
805 """Cache request parsing and hit detection
810 m_in
, d_in
= self
.m_in
, self
.d_in
813 hit_way
= Signal(WAY_BITS
)
818 hit_set
= Array(Signal(name
="hit_set_%d" % i
) \
819 for i
in range(TLB_NUM_WAYS
))
820 cache_valid_idx
= Signal(INDEX_BITS
)
822 # Extract line, row and tag from request
823 comb
+= req_index
.eq(get_index(r0
.req
.addr
))
824 comb
+= req_row
.eq(get_row(r0
.req
.addr
))
825 comb
+= req_tag
.eq(get_tag(ra
))
827 comb
+= go
.eq(r0_valid
& ~
(r0
.tlbie | r0
.tlbld
) & ~r1
.ls_error
)
828 comb
+= cache_valid_idx
.eq(cache_valid_bits
[req_index
])
830 m
.submodules
.dcache_pend
= dc
= DCachePendingHit(tlb_pte_way
,
831 tlb_valid_way
, tlb_hit_way
,
832 cache_valid_idx
, cache_tag_set
,
836 comb
+= dc
.tlb_hit
.eq(tlb_hit
)
837 comb
+= dc
.reload_tag
.eq(r1
.reload_tag
)
838 comb
+= dc
.virt_mode
.eq(r0
.req
.virt_mode
)
840 comb
+= dc
.req_index
.eq(req_index
)
841 comb
+= is_hit
.eq(dc
.is_hit
)
842 comb
+= hit_way
.eq(dc
.hit_way
)
843 comb
+= req_same_tag
.eq(dc
.rel_match
)
845 # See if the request matches the line currently being reloaded
846 with m
.If((r1
.state
== State
.RELOAD_WAIT_ACK
) &
847 (req_index
== r1
.store_index
) & req_same_tag
):
848 # For a store, consider this a hit even if the row isn't
849 # valid since it will be by the time we perform the store.
850 # For a load, check the appropriate row valid bit.
851 valid
= r1
.rows_valid
[req_row
% ROW_PER_LINE
]
852 comb
+= is_hit
.eq(~r0
.req
.load | valid
)
853 comb
+= hit_way
.eq(replace_way
)
855 # Whether to use forwarded data for a load or not
856 with m
.If((get_row(r1
.req
.real_addr
) == req_row
) &
857 (r1
.req
.hit_way
== hit_way
)):
858 # Only need to consider r1.write_bram here, since if we
859 # are writing refill data here, then we don't have a
860 # cache hit this cycle on the line being refilled.
861 # (There is the possibility that the load following the
862 # load miss that started the refill could be to the old
863 # contents of the victim line, since it is a couple of
864 # cycles after the refill starts before we see the updated
865 # cache tag. In that case we don't use the bypass.)
866 comb
+= use_forward1_next
.eq(r1
.write_bram
)
867 with m
.If((r1
.forward_row1
== req_row
) & (r1
.forward_way1
== hit_way
)):
868 comb
+= use_forward2_next
.eq(r1
.forward_valid1
)
870 # The way that matched on a hit
871 comb
+= req_hit_way
.eq(hit_way
)
873 # The way to replace on a miss
874 with m
.If(r1
.write_tag
):
875 comb
+= replace_way
.eq(plru_victim
[r1
.store_index
])
877 comb
+= replace_way
.eq(r1
.store_way
)
879 # work out whether we have permission for this access
880 # NB we don't yet implement AMR, thus no KUAP
881 comb
+= rc_ok
.eq(perm_attr
.reference
882 & (r0
.req
.load | perm_attr
.changed
)
884 comb
+= perm_ok
.eq((r0
.req
.priv_mode | ~perm_attr
.priv
) &
886 (r0
.req
.load
& perm_attr
.rd_perm
)))
887 comb
+= access_ok
.eq(valid_ra
& perm_ok
& rc_ok
)
888 # Combine the request and cache hit status to decide what
889 # operation needs to be done
890 comb
+= nc
.eq(r0
.req
.nc | perm_attr
.nocache
)
891 comb
+= op
.eq(Op
.OP_NONE
)
893 with m
.If(~access_ok
):
894 comb
+= op
.eq(Op
.OP_BAD
)
895 with m
.Elif(cancel_store
):
896 comb
+= op
.eq(Op
.OP_STCX_FAIL
)
898 comb
+= opsel
.eq(Cat(is_hit
, nc
, r0
.req
.load
))
899 with m
.Switch(opsel
):
901 comb
+= op
.eq(Op
.OP_LOAD_HIT
)
903 comb
+= op
.eq(Op
.OP_LOAD_MISS
)
905 comb
+= op
.eq(Op
.OP_LOAD_NC
)
907 comb
+= op
.eq(Op
.OP_STORE_HIT
)
909 comb
+= op
.eq(Op
.OP_STORE_MISS
)
911 comb
+= op
.eq(Op
.OP_STORE_MISS
)
913 comb
+= op
.eq(Op
.OP_BAD
)
915 comb
+= op
.eq(Op
.OP_BAD
)
917 comb
+= op
.eq(Op
.OP_NONE
)
918 comb
+= req_op
.eq(op
)
919 comb
+= req_go
.eq(go
)
921 # Version of the row number that is valid one cycle earlier
922 # in the cases where we need to read the cache data BRAM.
923 # If we're stalling then we need to keep reading the last
925 with m
.If(~r0_stall
):
926 with m
.If(m_in
.valid
):
927 comb
+= early_req_row
.eq(get_row(m_in
.addr
))
929 comb
+= early_req_row
.eq(get_row(d_in
.addr
))
931 comb
+= early_req_row
.eq(req_row
)
933 def reservation_comb(self
, m
, cancel_store
, set_rsrv
, clear_rsrv
,
934 r0_valid
, r0
, reservation
):
935 """Handle load-with-reservation and store-conditional instructions
940 with m
.If(r0_valid
& r0
.req
.reserve
):
942 # XXX generate alignment interrupt if address
943 # is not aligned XXX or if r0.req.nc = '1'
944 with m
.If(r0
.req
.load
):
945 comb
+= set_rsrv
.eq(1) # load with reservation
947 comb
+= clear_rsrv
.eq(1) # store conditional
948 with m
.If(~reservation
.valid | r0
.req
.addr
[LINE_OFF_BITS
:64]):
949 comb
+= cancel_store
.eq(1)
951 def reservation_reg(self
, m
, r0_valid
, access_ok
, set_rsrv
, clear_rsrv
,
957 with m
.If(r0_valid
& access_ok
):
958 with m
.If(clear_rsrv
):
959 sync
+= reservation
.valid
.eq(0)
960 with m
.Elif(set_rsrv
):
961 sync
+= reservation
.valid
.eq(1)
962 sync
+= reservation
.addr
.eq(r0
.req
.addr
[LINE_OFF_BITS
:64])
964 def writeback_control(self
, m
, r1
, cache_out
):
965 """Return data for loads & completion control logic
969 d_out
, m_out
= self
.d_out
, self
.m_out
971 data_out
= Signal(64)
972 data_fwd
= Signal(64)
974 # Use the bypass if are reading the row that was
975 # written 1 or 2 cycles ago, including for the
976 # slow_valid = 1 case (i.e. completing a load
977 # miss or a non-cacheable load).
978 with m
.If(r1
.use_forward1
):
979 comb
+= data_fwd
.eq(r1
.forward_data1
)
981 comb
+= data_fwd
.eq(r1
.forward_data2
)
983 comb
+= data_out
.eq(cache_out
[r1
.hit_way
])
986 with m
.If(r1
.forward_sel
[i
]):
987 dsel
= data_fwd
.word_select(i
, 8)
988 comb
+= data_out
.word_select(i
, 8).eq(dsel
)
990 comb
+= d_out
.valid
.eq(r1
.ls_valid
)
991 comb
+= d_out
.data
.eq(data_out
)
992 comb
+= d_out
.store_done
.eq(~r1
.stcx_fail
)
993 comb
+= d_out
.error
.eq(r1
.ls_error
)
994 comb
+= d_out
.cache_paradox
.eq(r1
.cache_paradox
)
997 comb
+= m_out
.done
.eq(r1
.mmu_done
)
998 comb
+= m_out
.err
.eq(r1
.mmu_error
)
999 comb
+= m_out
.data
.eq(data_out
)
1001 # We have a valid load or store hit or we just completed
1002 # a slow op such as a load miss, a NC load or a store
1004 # Note: the load hit is delayed by one cycle. However it
1005 # can still not collide with r.slow_valid (well unless I
1006 # miscalculated) because slow_valid can only be set on a
1007 # subsequent request and not on its first cycle (the state
1008 # machine must have advanced), which makes slow_valid
1009 # at least 2 cycles from the previous hit_load_valid.
1011 # Sanity: Only one of these must be set in any given cycle
1013 if False: # TODO: need Display to get this to work
1014 assert (r1
.slow_valid
& r1
.stcx_fail
) != 1, \
1015 "unexpected slow_valid collision with stcx_fail"
1017 assert ((r1
.slow_valid | r1
.stcx_fail
) | r1
.hit_load_valid
) != 1, \
1018 "unexpected hit_load_delayed collision with slow_valid"
1020 with m
.If(~r1
.mmu_req
):
1021 # Request came from loadstore1...
1022 # Load hit case is the standard path
1023 with m
.If(r1
.hit_load_valid
):
1024 sync
+= Display("completing load hit data=%x", data_out
)
1026 # error cases complete without stalling
1027 with m
.If(r1
.ls_error
):
1028 sync
+= Display("completing ld/st with error")
1030 # Slow ops (load miss, NC, stores)
1031 with m
.If(r1
.slow_valid
):
1032 sync
+= Display("completing store or load miss data=%x",
1036 # Request came from MMU
1037 with m
.If(r1
.hit_load_valid
):
1038 sync
+= Display("completing load hit to MMU, data=%x",
1040 # error cases complete without stalling
1041 with m
.If(r1
.mmu_error
):
1042 sync
+= Display("combpleting MMU ld with error")
1044 # Slow ops (i.e. load miss)
1045 with m
.If(r1
.slow_valid
):
1046 sync
+= Display("completing MMU load miss, data=%x",
1049 def rams(self
, m
, r1
, early_req_row
, cache_out
, replace_way
):
1051 Generate a cache RAM for each way. This handles the normal
1052 reads, writes from reloads and the special store-hit update
1055 Note: the BRAMs have an extra read buffer, meaning the output
1056 is pipelined an extra cycle. This differs from the
1057 icache. The writeback logic needs to take that into
1058 account by using 1-cycle delayed signals for load hits.
1063 for i
in range(NUM_WAYS
):
1064 do_read
= Signal(name
="do_rd%d" % i
)
1065 rd_addr
= Signal(ROW_BITS
)
1066 do_write
= Signal(name
="do_wr%d" % i
)
1067 wr_addr
= Signal(ROW_BITS
)
1068 wr_data
= Signal(WB_DATA_BITS
)
1069 wr_sel
= Signal(ROW_SIZE
)
1070 wr_sel_m
= Signal(ROW_SIZE
)
1071 _d_out
= Signal(WB_DATA_BITS
, name
="dout_%d" % i
)
1073 way
= CacheRam(ROW_BITS
, WB_DATA_BITS
, True)
1074 setattr(m
.submodules
, "cacheram_%d" % i
, way
)
1076 comb
+= way
.rd_en
.eq(do_read
)
1077 comb
+= way
.rd_addr
.eq(rd_addr
)
1078 comb
+= _d_out
.eq(way
.rd_data_o
)
1079 comb
+= way
.wr_sel
.eq(wr_sel_m
)
1080 comb
+= way
.wr_addr
.eq(wr_addr
)
1081 comb
+= way
.wr_data
.eq(wr_data
)
1084 comb
+= do_read
.eq(1)
1085 comb
+= rd_addr
.eq(early_req_row
[:ROW_BITS
])
1086 comb
+= cache_out
[i
].eq(_d_out
)
1090 # Defaults to wishbone read responses (cache refill)
1092 # For timing, the mux on wr_data/sel/addr is not
1093 # dependent on anything other than the current state.
1095 with m
.If(r1
.write_bram
):
1096 # Write store data to BRAM. This happens one
1097 # cycle after the store is in r0.
1098 comb
+= wr_data
.eq(r1
.req
.data
)
1099 comb
+= wr_sel
.eq(r1
.req
.byte_sel
)
1100 comb
+= wr_addr
.eq(get_row(r1
.req
.real_addr
))
1102 with m
.If(i
== r1
.req
.hit_way
):
1103 comb
+= do_write
.eq(1)
1105 # Otherwise, we might be doing a reload or a DCBZ
1107 comb
+= wr_data
.eq(0)
1109 comb
+= wr_data
.eq(wb_in
.dat
)
1110 comb
+= wr_addr
.eq(r1
.store_row
)
1111 comb
+= wr_sel
.eq(~
0) # all 1s
1113 with m
.If((r1
.state
== State
.RELOAD_WAIT_ACK
)
1114 & wb_in
.ack
& (replace_way
== i
)):
1115 comb
+= do_write
.eq(1)
1117 # Mask write selects with do_write since BRAM
1118 # doesn't have a global write-enable
1119 with m
.If(do_write
):
1120 comb
+= wr_sel_m
.eq(wr_sel
)
1122 # Cache hit synchronous machine for the easy case.
1123 # This handles load hits.
1124 # It also handles error cases (TLB miss, cache paradox)
1125 def dcache_fast_hit(self
, m
, req_op
, r0_valid
, r0
, r1
,
1126 req_hit_way
, req_index
, req_tag
, access_ok
,
1127 tlb_hit
, tlb_hit_way
, tlb_req_index
):
1132 with m
.If(req_op
!= Op
.OP_NONE
):
1133 sync
+= Display("op:%d addr:%x nc: %d idx: %x tag: %x way: %x",
1134 req_op
, r0
.req
.addr
, r0
.req
.nc
,
1135 req_index
, req_tag
, req_hit_way
)
1137 with m
.If(r0_valid
):
1138 sync
+= r1
.mmu_req
.eq(r0
.mmu_req
)
1140 # Fast path for load/store hits.
1141 # Set signals for the writeback controls.
1142 sync
+= r1
.hit_way
.eq(req_hit_way
)
1143 sync
+= r1
.hit_index
.eq(req_index
)
1145 with m
.If(req_op
== Op
.OP_LOAD_HIT
):
1146 sync
+= r1
.hit_load_valid
.eq(1)
1148 sync
+= r1
.hit_load_valid
.eq(0)
1150 with m
.If((req_op
== Op
.OP_LOAD_HIT
) |
(req_op
== Op
.OP_STORE_HIT
)):
1151 sync
+= r1
.cache_hit
.eq(1)
1153 sync
+= r1
.cache_hit
.eq(0)
1155 with m
.If(req_op
== Op
.OP_BAD
):
1156 # Display(f"Signalling ld/st error valid_ra={valid_ra}"
1157 # f"rc_ok={rc_ok} perm_ok={perm_ok}"
1158 sync
+= r1
.ls_error
.eq(~r0
.mmu_req
)
1159 sync
+= r1
.mmu_error
.eq(r0
.mmu_req
)
1160 sync
+= r1
.cache_paradox
.eq(access_ok
)
1163 sync
+= r1
.ls_error
.eq(0)
1164 sync
+= r1
.mmu_error
.eq(0)
1165 sync
+= r1
.cache_paradox
.eq(0)
1167 with m
.If(req_op
== Op
.OP_STCX_FAIL
):
1170 sync
+= r1
.stcx_fail
.eq(0)
1172 # Record TLB hit information for updating TLB PLRU
1173 sync
+= r1
.tlb_hit
.eq(tlb_hit
)
1174 sync
+= r1
.tlb_hit_way
.eq(tlb_hit_way
)
1175 sync
+= r1
.tlb_hit_index
.eq(tlb_req_index
)
1177 # Memory accesses are handled by this state machine:
1179 # * Cache load miss/reload (in conjunction with "rams")
1180 # * Load hits for non-cachable forms
1181 # * Stores (the collision case is handled in "rams")
1183 # All wishbone requests generation is done here.
1184 # This machine operates at stage 1.
1185 def dcache_slow(self
, m
, r1
, use_forward1_next
, use_forward2_next
,
1186 cache_valid_bits
, r0
, replace_way
,
1187 req_hit_way
, req_same_tag
,
1188 r0_valid
, req_op
, cache_tags
, req_go
, ra
):
1194 req
= MemAccessRequest("mreq_ds")
1196 adjust_acks
= Signal(3)
1198 sync
+= r1
.use_forward1
.eq(use_forward1_next
)
1199 sync
+= r1
.forward_sel
.eq(0)
1201 with m
.If(use_forward1_next
):
1202 sync
+= r1
.forward_sel
.eq(r1
.req
.byte_sel
)
1203 with m
.Elif(use_forward2_next
):
1204 sync
+= r1
.forward_sel
.eq(r1
.forward_sel1
)
1206 sync
+= r1
.forward_data2
.eq(r1
.forward_data1
)
1207 with m
.If(r1
.write_bram
):
1208 sync
+= r1
.forward_data1
.eq(r1
.req
.data
)
1209 sync
+= r1
.forward_sel1
.eq(r1
.req
.byte_sel
)
1210 sync
+= r1
.forward_way1
.eq(r1
.req
.hit_way
)
1211 sync
+= r1
.forward_row1
.eq(get_row(r1
.req
.real_addr
))
1212 sync
+= r1
.forward_valid1
.eq(1)
1215 sync
+= r1
.forward_data1
.eq(0)
1217 sync
+= r1
.forward_data1
.eq(wb_in
.dat
)
1218 sync
+= r1
.forward_sel1
.eq(~
0) # all 1s
1219 sync
+= r1
.forward_way1
.eq(replace_way
)
1220 sync
+= r1
.forward_row1
.eq(r1
.store_row
)
1221 sync
+= r1
.forward_valid1
.eq(0)
1223 # One cycle pulses reset
1224 sync
+= r1
.slow_valid
.eq(0)
1225 sync
+= r1
.write_bram
.eq(0)
1226 sync
+= r1
.inc_acks
.eq(0)
1227 sync
+= r1
.dec_acks
.eq(0)
1229 sync
+= r1
.ls_valid
.eq(0)
1230 # complete tlbies and TLB loads in the third cycle
1231 sync
+= r1
.mmu_done
.eq(r0_valid
& (r0
.tlbie | r0
.tlbld
))
1233 with m
.If((req_op
== Op
.OP_LOAD_HIT
)
1234 |
(req_op
== Op
.OP_STCX_FAIL
)):
1235 with m
.If(~r0
.mmu_req
):
1236 sync
+= r1
.ls_valid
.eq(1)
1238 sync
+= r1
.mmu_done
.eq(1)
1240 with m
.If(r1
.write_tag
):
1241 # Store new tag in selected way
1242 for i
in range(NUM_WAYS
):
1243 with m
.If(i
== replace_way
):
1244 ct
= Signal(TAG_RAM_WIDTH
)
1245 comb
+= ct
.eq(cache_tags
[r1
.store_index
])
1246 comb
+= ct
.word_select(i
, TAG_WIDTH
).eq(r1
.reload_tag
)
1247 sync
+= cache_tags
[r1
.store_index
].eq(ct
)
1248 sync
+= r1
.store_way
.eq(replace_way
)
1249 sync
+= r1
.write_tag
.eq(0)
1251 # Take request from r1.req if there is one there,
1252 # else from req_op, ra, etc.
1254 comb
+= req
.eq(r1
.req
)
1256 comb
+= req
.op
.eq(req_op
)
1257 comb
+= req
.valid
.eq(req_go
)
1258 comb
+= req
.mmu_req
.eq(r0
.mmu_req
)
1259 comb
+= req
.dcbz
.eq(r0
.req
.dcbz
)
1260 comb
+= req
.real_addr
.eq(ra
)
1262 with m
.If(~r0
.req
.dcbz
):
1263 comb
+= req
.data
.eq(r0
.req
.data
)
1265 comb
+= req
.data
.eq(0)
1267 # Select all bytes for dcbz
1268 # and for cacheable loads
1269 with m
.If(r0
.req
.dcbz |
(r0
.req
.load
& ~r0
.req
.nc
)):
1270 comb
+= req
.byte_sel
.eq(~
0) # all 1s
1272 comb
+= req
.byte_sel
.eq(r0
.req
.byte_sel
)
1273 comb
+= req
.hit_way
.eq(req_hit_way
)
1274 comb
+= req
.same_tag
.eq(req_same_tag
)
1276 # Store the incoming request from r0,
1277 # if it is a slow request
1278 # Note that r1.full = 1 implies req_op = OP_NONE
1279 with m
.If((req_op
== Op
.OP_LOAD_MISS
)
1280 |
(req_op
== Op
.OP_LOAD_NC
)
1281 |
(req_op
== Op
.OP_STORE_MISS
)
1282 |
(req_op
== Op
.OP_STORE_HIT
)):
1283 sync
+= r1
.req
.eq(req
)
1284 sync
+= r1
.full
.eq(1)
1286 # Main state machine
1287 with m
.Switch(r1
.state
):
1289 with m
.Case(State
.IDLE
):
1290 # XXX check 'left downto. probably means len(r1.wb.adr)
1291 # r1.wb.adr <= req.real_addr(
1292 # r1.wb.adr'left downto 0
1294 sync
+= r1
.wb
.adr
.eq(req
.real_addr
)
1295 sync
+= r1
.wb
.sel
.eq(req
.byte_sel
)
1296 sync
+= r1
.wb
.dat
.eq(req
.data
)
1297 sync
+= r1
.dcbz
.eq(req
.dcbz
)
1299 # Keep track of our index and way
1300 # for subsequent stores.
1301 sync
+= r1
.store_index
.eq(get_index(req
.real_addr
))
1302 sync
+= r1
.store_row
.eq(get_row(req
.real_addr
))
1303 sync
+= r1
.end_row_ix
.eq(
1304 get_row_of_line(get_row(req
.real_addr
))
1306 sync
+= r1
.reload_tag
.eq(get_tag(req
.real_addr
))
1307 sync
+= r1
.req
.same_tag
.eq(1)
1309 with m
.If(req
.op
== Op
.OP_STORE_HIT
):
1310 sync
+= r1
.store_way
.eq(req
.hit_way
)
1312 # Reset per-row valid bits,
1313 # ready for handling OP_LOAD_MISS
1314 for i
in range(ROW_PER_LINE
):
1315 sync
+= r1
.rows_valid
[i
].eq(0)
1317 with m
.If(req_op
!= Op
.OP_NONE
):
1318 sync
+= Display("cache op %d", req
.op
)
1320 with m
.Switch(req
.op
):
1321 with m
.Case(Op
.OP_LOAD_HIT
):
1322 # stay in IDLE state
1325 with m
.Case(Op
.OP_LOAD_MISS
):
1326 #Display(f"cache miss real addr:" \
1327 # f"{req_real_addr}" \
1328 # f" idx:{get_index(req_real_addr)}" \
1329 # f" tag:{get_tag(req.real_addr)}")
1332 # Start the wishbone cycle
1333 sync
+= r1
.wb
.we
.eq(0)
1334 sync
+= r1
.wb
.cyc
.eq(1)
1335 sync
+= r1
.wb
.stb
.eq(1)
1337 # Track that we had one request sent
1338 sync
+= r1
.state
.eq(State
.RELOAD_WAIT_ACK
)
1339 sync
+= r1
.write_tag
.eq(1)
1341 with m
.Case(Op
.OP_LOAD_NC
):
1342 sync
+= r1
.wb
.cyc
.eq(1)
1343 sync
+= r1
.wb
.stb
.eq(1)
1344 sync
+= r1
.wb
.we
.eq(0)
1345 sync
+= r1
.state
.eq(State
.NC_LOAD_WAIT_ACK
)
1347 with m
.Case(Op
.OP_STORE_HIT
, Op
.OP_STORE_MISS
):
1348 with m
.If(~req
.dcbz
):
1349 sync
+= r1
.state
.eq(State
.STORE_WAIT_ACK
)
1350 sync
+= r1
.acks_pending
.eq(1)
1351 sync
+= r1
.full
.eq(0)
1352 sync
+= r1
.slow_valid
.eq(1)
1354 with m
.If(~req
.mmu_req
):
1355 sync
+= r1
.ls_valid
.eq(1)
1357 sync
+= r1
.mmu_done
.eq(1)
1359 with m
.If(req
.op
== Op
.OP_STORE_HIT
):
1360 sync
+= r1
.write_bram
.eq(1)
1362 # dcbz is handled much like a load miss except
1363 # that we are writing to memory instead of reading
1364 sync
+= r1
.state
.eq(State
.RELOAD_WAIT_ACK
)
1366 with m
.If(req
.op
== Op
.OP_STORE_MISS
):
1367 sync
+= r1
.write_tag
.eq(1)
1369 sync
+= r1
.wb
.we
.eq(1)
1370 sync
+= r1
.wb
.cyc
.eq(1)
1371 sync
+= r1
.wb
.stb
.eq(1)
1373 # OP_NONE and OP_BAD do nothing
1374 # OP_BAD & OP_STCX_FAIL were
1375 # handled above already
1376 with m
.Case(Op
.OP_NONE
):
1378 with m
.Case(Op
.OP_BAD
):
1380 with m
.Case(Op
.OP_STCX_FAIL
):
1383 with m
.Case(State
.RELOAD_WAIT_ACK
):
1384 ld_stbs_done
= Signal()
1385 # Requests are all sent if stb is 0
1386 comb
+= ld_stbs_done
.eq(~r1
.wb
.stb
)
1388 with m
.If((~wb_in
.stall
) & r1
.wb
.stb
):
1389 # That was the last word?
1390 # We are done sending.
1391 # Clear stb and set ld_stbs_done
1392 # so we can handle an eventual
1393 # last ack on the same cycle.
1394 with m
.If(is_last_row_addr(r1
.wb
.adr
, r1
.end_row_ix
)):
1395 sync
+= r1
.wb
.stb
.eq(0)
1396 comb
+= ld_stbs_done
.eq(1)
1398 # Calculate the next row address in the current cache line
1399 rarange
= r1
.wb
.adr
[ROW_OFF_BITS
: LINE_OFF_BITS
]
1400 sync
+= rarange
.eq(rarange
+ 1)
1402 # Incoming acks processing
1403 sync
+= r1
.forward_valid1
.eq(wb_in
.ack
)
1404 with m
.If(wb_in
.ack
):
1405 sync
+= r1
.rows_valid
[r1
.store_row
% ROW_PER_LINE
].eq(1)
1407 # If this is the data we were looking for,
1408 # we can complete the request next cycle.
1409 # Compare the whole address in case the
1410 # request in r1.req is not the one that
1411 # started this refill.
1412 with m
.If(r1
.full
& r1
.req
.same_tag
&
1413 ((r1
.dcbz
& r1
.req
.dcbz
) |
1414 (~r1
.dcbz
& (r1
.req
.op
== Op
.OP_LOAD_MISS
))) &
1415 (r1
.store_row
== get_row(r1
.req
.real_addr
))):
1416 sync
+= r1
.full
.eq(0)
1417 sync
+= r1
.slow_valid
.eq(1)
1418 with m
.If(~r1
.mmu_req
):
1419 sync
+= r1
.ls_valid
.eq(1)
1421 sync
+= r1
.mmu_done
.eq(1)
1422 sync
+= r1
.forward_sel
.eq(~
0) # all 1s
1423 sync
+= r1
.use_forward1
.eq(1)
1425 # Check for completion
1426 with m
.If(ld_stbs_done
& is_last_row(r1
.store_row
,
1428 # Complete wishbone cycle
1429 sync
+= r1
.wb
.cyc
.eq(0)
1431 # Cache line is now valid
1432 cv
= Signal(INDEX_BITS
)
1433 comb
+= cv
.eq(cache_valid_bits
[r1
.store_index
])
1434 comb
+= cv
.bit_select(r1
.store_way
, 1).eq(1)
1435 sync
+= cache_valid_bits
[r1
.store_index
].eq(cv
)
1436 sync
+= r1
.state
.eq(State
.IDLE
)
1438 # Increment store row counter
1439 sync
+= r1
.store_row
.eq(next_row(r1
.store_row
))
1441 with m
.Case(State
.STORE_WAIT_ACK
):
1442 st_stbs_done
= Signal()
1443 comb
+= st_stbs_done
.eq(~r1
.wb
.stb
)
1444 comb
+= acks
.eq(r1
.acks_pending
)
1446 with m
.If(r1
.inc_acks
!= r1
.dec_acks
):
1447 with m
.If(r1
.inc_acks
):
1448 comb
+= adjust_acks
.eq(acks
+ 1)
1450 comb
+= adjust_acks
.eq(acks
- 1)
1452 comb
+= adjust_acks
.eq(acks
)
1454 sync
+= r1
.acks_pending
.eq(adjust_acks
)
1456 # Clear stb when slave accepted request
1457 with m
.If(~wb_in
.stall
):
1458 # See if there is another store waiting
1459 # to be done which is in the same real page.
1460 with m
.If(req
.valid
):
1461 ra
= req
.real_addr
[0:SET_SIZE_BITS
]
1462 sync
+= r1
.wb
.adr
[0:SET_SIZE_BITS
].eq(ra
)
1463 sync
+= r1
.wb
.dat
.eq(req
.data
)
1464 sync
+= r1
.wb
.sel
.eq(req
.byte_sel
)
1466 with m
.Elif((adjust_acks
< 7) & req
.same_tag
&
1467 ((req
.op
== Op
.OP_STORE_MISS
)
1468 |
(req
.op
== Op
.OP_STORE_HIT
))):
1469 sync
+= r1
.wb
.stb
.eq(1)
1470 comb
+= st_stbs_done
.eq(0)
1472 with m
.If(req
.op
== Op
.OP_STORE_HIT
):
1473 sync
+= r1
.write_bram
.eq(1)
1474 sync
+= r1
.full
.eq(0)
1475 sync
+= r1
.slow_valid
.eq(1)
1477 # Store requests never come from the MMU
1478 sync
+= r1
.ls_valid
.eq(1)
1479 comb
+= st_stbs_done
.eq(0)
1480 sync
+= r1
.inc_acks
.eq(1)
1482 sync
+= r1
.wb
.stb
.eq(0)
1483 comb
+= st_stbs_done
.eq(1)
1485 # Got ack ? See if complete.
1486 with m
.If(wb_in
.ack
):
1487 with m
.If(st_stbs_done
& (adjust_acks
== 1)):
1488 sync
+= r1
.state
.eq(State
.IDLE
)
1489 sync
+= r1
.wb
.cyc
.eq(0)
1490 sync
+= r1
.wb
.stb
.eq(0)
1491 sync
+= r1
.dec_acks
.eq(1)
1493 with m
.Case(State
.NC_LOAD_WAIT_ACK
):
1494 # Clear stb when slave accepted request
1495 with m
.If(~wb_in
.stall
):
1496 sync
+= r1
.wb
.stb
.eq(0)
1498 # Got ack ? complete.
1499 with m
.If(wb_in
.ack
):
1500 sync
+= r1
.state
.eq(State
.IDLE
)
1501 sync
+= r1
.full
.eq(0)
1502 sync
+= r1
.slow_valid
.eq(1)
1504 with m
.If(~r1
.mmu_req
):
1505 sync
+= r1
.ls_valid
.eq(1)
1507 sync
+= r1
.mmu_done
.eq(1)
1509 sync
+= r1
.forward_sel
.eq(~
0) # all 1s
1510 sync
+= r1
.use_forward1
.eq(1)
1511 sync
+= r1
.wb
.cyc
.eq(0)
1512 sync
+= r1
.wb
.stb
.eq(0)
1514 def dcache_log(self
, m
, r1
, valid_ra
, tlb_hit_way
, stall_out
):
1517 d_out
, wb_in
, log_out
= self
.d_out
, self
.wb_in
, self
.log_out
1519 sync
+= log_out
.eq(Cat(r1
.state
[:3], valid_ra
, tlb_hit_way
[:3],
1520 stall_out
, req_op
[:3], d_out
.valid
, d_out
.error
,
1521 r1
.wb
.cyc
, r1
.wb
.stb
, wb_in
.ack
, wb_in
.stall
,
1524 def elaborate(self
, platform
):
1529 # Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
1530 cache_tags
= CacheTagArray()
1531 cache_tag_set
= Signal(TAG_RAM_WIDTH
)
1532 cache_valid_bits
= CacheValidBitsArray()
1534 # TODO attribute ram_style : string;
1535 # TODO attribute ram_style of cache_tags : signal is "distributed";
1537 """note: these are passed to nmigen.hdl.Memory as "attributes".
1538 don't know how, just that they are.
1540 dtlb_valid_bits
= TLBValidBitsArray()
1541 dtlb_tags
= TLBTagsArray()
1542 dtlb_ptes
= TLBPtesArray()
1543 # TODO attribute ram_style of
1544 # dtlb_tags : signal is "distributed";
1545 # TODO attribute ram_style of
1546 # dtlb_ptes : signal is "distributed";
1548 r0
= RegStage0("r0")
1551 r1
= RegStage1("r1")
1553 reservation
= Reservation()
1555 # Async signals on incoming request
1556 req_index
= Signal(INDEX_BITS
)
1557 req_row
= Signal(ROW_BITS
)
1558 req_hit_way
= Signal(WAY_BITS
)
1559 req_tag
= Signal(TAG_BITS
)
1561 req_data
= Signal(64)
1562 req_same_tag
= Signal()
1565 early_req_row
= Signal(ROW_BITS
)
1567 cancel_store
= Signal()
1569 clear_rsrv
= Signal()
1574 use_forward1_next
= Signal()
1575 use_forward2_next
= Signal()
1577 cache_out
= CacheRamOut()
1579 plru_victim
= PLRUOut()
1580 replace_way
= Signal(WAY_BITS
)
1582 # Wishbone read/write/cache write formatting signals
1586 tlb_tag_way
= Signal(TLB_TAG_WAY_BITS
)
1587 tlb_pte_way
= Signal(TLB_PTE_WAY_BITS
)
1588 tlb_valid_way
= Signal(TLB_NUM_WAYS
)
1589 tlb_req_index
= Signal(TLB_SET_BITS
)
1591 tlb_hit_way
= Signal(TLB_WAY_BITS
)
1592 pte
= Signal(TLB_PTE_BITS
)
1593 ra
= Signal(REAL_ADDR_BITS
)
1595 perm_attr
= PermAttr("dc_perms")
1598 access_ok
= Signal()
1600 tlb_plru_victim
= TLBPLRUOut()
1602 # we don't yet handle collisions between loadstore1 requests
1604 comb
+= self
.m_out
.stall
.eq(0)
1606 # Hold off the request in r0 when r1 has an uncompleted request
1607 comb
+= r0_stall
.eq(r0_full
& r1
.full
)
1608 comb
+= r0_valid
.eq(r0_full
& ~r1
.full
)
1609 comb
+= self
.stall_out
.eq(r0_stall
)
1611 # Wire up wishbone request latch out of stage 1
1612 comb
+= self
.wb_out
.eq(r1
.wb
)
1614 # call sub-functions putting everything together, using shared
1615 # signals established above
1616 self
.stage_0(m
, r0
, r1
, r0_full
)
1617 self
.tlb_read(m
, r0_stall
, tlb_valid_way
,
1618 tlb_tag_way
, tlb_pte_way
, dtlb_valid_bits
,
1619 dtlb_tags
, dtlb_ptes
)
1620 self
.tlb_search(m
, tlb_req_index
, r0
, r0_valid
,
1621 tlb_valid_way
, tlb_tag_way
, tlb_hit_way
,
1622 tlb_pte_way
, pte
, tlb_hit
, valid_ra
, perm_attr
, ra
)
1623 self
.tlb_update(m
, r0_valid
, r0
, dtlb_valid_bits
, tlb_req_index
,
1624 tlb_hit_way
, tlb_hit
, tlb_plru_victim
, tlb_tag_way
,
1625 dtlb_tags
, tlb_pte_way
, dtlb_ptes
)
1626 self
.maybe_plrus(m
, r1
, plru_victim
)
1627 self
.maybe_tlb_plrus(m
, r1
, tlb_plru_victim
)
1628 self
.cache_tag_read(m
, r0_stall
, req_index
, cache_tag_set
, cache_tags
)
1629 self
.dcache_request(m
, r0
, ra
, req_index
, req_row
, req_tag
,
1630 r0_valid
, r1
, cache_valid_bits
, replace_way
,
1631 use_forward1_next
, use_forward2_next
,
1632 req_hit_way
, plru_victim
, rc_ok
, perm_attr
,
1633 valid_ra
, perm_ok
, access_ok
, req_op
, req_go
,
1635 tlb_hit
, tlb_hit_way
, tlb_valid_way
, cache_tag_set
,
1636 cancel_store
, req_same_tag
, r0_stall
, early_req_row
)
1637 self
.reservation_comb(m
, cancel_store
, set_rsrv
, clear_rsrv
,
1638 r0_valid
, r0
, reservation
)
1639 self
.reservation_reg(m
, r0_valid
, access_ok
, set_rsrv
, clear_rsrv
,
1641 self
.writeback_control(m
, r1
, cache_out
)
1642 self
.rams(m
, r1
, early_req_row
, cache_out
, replace_way
)
1643 self
.dcache_fast_hit(m
, req_op
, r0_valid
, r0
, r1
,
1644 req_hit_way
, req_index
, req_tag
, access_ok
,
1645 tlb_hit
, tlb_hit_way
, tlb_req_index
)
1646 self
.dcache_slow(m
, r1
, use_forward1_next
, use_forward2_next
,
1647 cache_valid_bits
, r0
, replace_way
,
1648 req_hit_way
, req_same_tag
,
1649 r0_valid
, req_op
, cache_tags
, req_go
, ra
)
1650 #self.dcache_log(m, r1, valid_ra, tlb_hit_way, stall_out)
1654 def dcache_load(dut
, addr
, nc
=0):
1655 yield dut
.d_in
.load
.eq(1)
1656 yield dut
.d_in
.nc
.eq(nc
)
1657 yield dut
.d_in
.addr
.eq(addr
)
1658 yield dut
.d_in
.valid
.eq(1)
1660 yield dut
.d_in
.valid
.eq(0)
1662 while not (yield dut
.d_out
.valid
):
1664 data
= yield dut
.d_out
.data
1668 def dcache_store(dut
, addr
, data
, nc
=0):
1669 yield dut
.d_in
.load
.eq(0)
1670 yield dut
.d_in
.nc
.eq(nc
)
1671 yield dut
.d_in
.data
.eq(data
)
1672 yield dut
.d_in
.byte_sel
.eq(~
0)
1673 yield dut
.d_in
.addr
.eq(addr
)
1674 yield dut
.d_in
.valid
.eq(1)
1676 yield dut
.d_in
.valid
.eq(0)
1677 yield dut
.d_in
.byte_sel
.eq(0)
1679 while not (yield dut
.d_out
.valid
):
1683 def dcache_random_sim(dut
):
1685 # start with stack of zeros
1689 yield dut
.d_in
.valid
.eq(0)
1690 yield dut
.d_in
.load
.eq(0)
1691 yield dut
.d_in
.priv_mode
.eq(1)
1692 yield dut
.d_in
.nc
.eq(0)
1693 yield dut
.d_in
.addr
.eq(0)
1694 yield dut
.d_in
.data
.eq(0)
1695 yield dut
.m_in
.valid
.eq(0)
1696 yield dut
.m_in
.addr
.eq(0)
1697 yield dut
.m_in
.pte
.eq(0)
1698 # wait 4 * clk_period
1706 for i
in range(256):
1707 addr
= randint(0, 255)
1708 data
= randint(0, (1<<64)-1)
1709 sim_mem
[addr
] = data
1712 print ("testing %x data %x" % (addr
, data
))
1714 yield from dcache_load(dut
, addr
)
1715 yield from dcache_store(dut
, addr
, data
)
1717 addr
= randint(0, 255)
1718 sim_data
= sim_mem
[addr
]
1721 data
= yield from dcache_load(dut
, addr
)
1722 assert data
== sim_data
, \
1723 "check %x data %x != %x" % (addr
, data
, sim_data
)
1725 for addr
in range(8):
1726 data
= yield from dcache_load(dut
, addr
*8)
1727 assert data
== sim_mem
[addr
], \
1728 "final check %x data %x != %x" % (addr
*8, data
, sim_mem
[addr
])
1730 def dcache_sim(dut
):
1732 yield dut
.d_in
.valid
.eq(0)
1733 yield dut
.d_in
.load
.eq(0)
1734 yield dut
.d_in
.priv_mode
.eq(1)
1735 yield dut
.d_in
.nc
.eq(0)
1736 yield dut
.d_in
.addr
.eq(0)
1737 yield dut
.d_in
.data
.eq(0)
1738 yield dut
.m_in
.valid
.eq(0)
1739 yield dut
.m_in
.addr
.eq(0)
1740 yield dut
.m_in
.pte
.eq(0)
1741 # wait 4 * clk_period
1747 # Cacheable read of address 4
1748 data
= yield from dcache_load(dut
, 0x4)
1749 addr
= yield dut
.d_in
.addr
1750 assert data
== 0x0000000100000000, \
1751 f
"data @%x=%x expected 0x0000000100000000" % (addr
, data
)
1753 # Cacheable read of address 30
1754 data
= yield from dcache_load(dut
, 0x530)
1755 addr
= yield dut
.d_in
.addr
1756 assert data
== 0x0000014D0000014C, \
1757 f
"data @%x=%x expected 0000014D0000014C" % (addr
, data
)
1759 # 2nd Cacheable read of address 30
1760 data
= yield from dcache_load(dut
, 0x530)
1761 addr
= yield dut
.d_in
.addr
1762 assert data
== 0x0000014D0000014C, \
1763 f
"data @%x=%x expected 0000014D0000014C" % (addr
, data
)
1765 # Non-cacheable read of address 100
1766 data
= yield from dcache_load(dut
, 0x100, nc
=1)
1767 addr
= yield dut
.d_in
.addr
1768 assert data
== 0x0000004100000040, \
1769 f
"data @%x=%x expected 0000004100000040" % (addr
, data
)
1771 # Store at address 530
1772 yield from dcache_store(dut
, 0x530, 0x121)
1774 # Store at address 30
1775 yield from dcache_store(dut
, 0x530, 0x12345678)
1777 # 3nd Cacheable read of address 530
1778 data
= yield from dcache_load(dut
, 0x530)
1779 addr
= yield dut
.d_in
.addr
1780 assert data
== 0x12345678, \
1781 f
"data @%x=%x expected 0x12345678" % (addr
, data
)
1789 def test_dcache(mem
, test_fn
, test_name
):
1792 memory
= Memory(width
=64, depth
=16*64, init
=mem
)
1793 sram
= SRAM(memory
=memory
, granularity
=8)
1796 m
.submodules
.dcache
= dut
1797 m
.submodules
.sram
= sram
1799 m
.d
.comb
+= sram
.bus
.cyc
.eq(dut
.wb_out
.cyc
)
1800 m
.d
.comb
+= sram
.bus
.stb
.eq(dut
.wb_out
.stb
)
1801 m
.d
.comb
+= sram
.bus
.we
.eq(dut
.wb_out
.we
)
1802 m
.d
.comb
+= sram
.bus
.sel
.eq(dut
.wb_out
.sel
)
1803 m
.d
.comb
+= sram
.bus
.adr
.eq(dut
.wb_out
.adr
[3:])
1804 m
.d
.comb
+= sram
.bus
.dat_w
.eq(dut
.wb_out
.dat
)
1806 m
.d
.comb
+= dut
.wb_in
.ack
.eq(sram
.bus
.ack
)
1807 m
.d
.comb
+= dut
.wb_in
.dat
.eq(sram
.bus
.dat_r
)
1813 sim
.add_sync_process(wrap(test_fn(dut
)))
1814 with sim
.write_vcd('test_dcache_%s.vcd' % test_name
):
1817 if __name__
== '__main__':
1819 vl
= rtlil
.convert(dut
, ports
=[])
1820 with
open("test_dcache.il", "w") as f
:
1824 for i
in range(0,512):
1825 mem
.append((i
*2)|
((i
*2+1)<<32))
1827 test_dcache(mem
, dcache_sim
, "quick")
1828 test_dcache(None, dcache_random_sim
, "random")