src/soc/experiment/mem_types.py

   1 """mem_types
   2
   3 based on Anton Blanchard microwatt common.vhdl
   4
   5 """
   6 from nmutil.iocontrol import RecordObject
   7 from nmigen import Signal
   8
   9 from openpower.exceptions import LDSTException
  10
  11
  12 class DCacheToLoadStore1Type(RecordObject):
  13     def __init__(self, name=None):
  14         super().__init__(name=name)
  15         self.valid         = Signal()
  16         self.data          = Signal(64)
  17         self.store_done    = Signal()
  18         self.error         = Signal()
  19         self.cache_paradox = Signal()
  20
  21
  22 class DCacheToMMUType(RecordObject):
  23     def __init__(self, name=None):
  24         super().__init__(name=name)
  25         self.stall         = Signal()
  26         self.done          = Signal()
  27         self.err           = Signal()
  28         self.data          = Signal(64)
  29
  30
  31 class Fetch1ToICacheType(RecordObject):
  32     def __init__(self, name=None):
  33         super().__init__(name=name)
  34         self.req           = Signal()
  35         self.virt_mode     = Signal()
  36         self.priv_mode     = Signal()
  37         self.stop_mark     = Signal()
  38         self.sequential    = Signal()
  39         self.nia           = Signal(64)
  40
  41
  42 class ICacheToDecode1Type(RecordObject):
  43     def __init__(self, name=None):
  44         super().__init__(name=name)
  45         self.valid         = Signal()
  46         self.stop_mark     = Signal()
  47         self.fetch_failed  = Signal()
  48         self.nia           = Signal(64)
  49         self.insn          = Signal(32)
  50
  51
  52 class LoadStore1ToDCacheType(RecordObject):
  53     def __init__(self, name=None):
  54         super().__init__(name=name)
  55         self.valid         = Signal()
  56         self.load          = Signal() # this is a load
  57         self.dcbz          = Signal()
  58         self.nc            = Signal()
  59         self.reserve       = Signal()
  60         self.virt_mode     = Signal()
  61         self.priv_mode     = Signal()
  62         self.addr          = Signal(64)
  63         self.data          = Signal(64)
  64         self.byte_sel      = Signal(8)
  65
  66
  67 class LoadStore1ToMMUType(RecordObject):
  68     def __init__(self, name=None):
  69         super().__init__(name=name)
  70         self.valid         = Signal()
  71         self.tlbie         = Signal()
  72         self.slbia         = Signal()
  73         self.mtspr         = Signal()
  74         self.iside         = Signal()
  75         self.load          = Signal()
  76         self.priv          = Signal()
  77         self.sprn          = Signal(10)
  78         self.addr          = Signal(64)
  79         self.rs            = Signal(64)
  80
  81
  82 class MMUToLoadStore1Type(RecordObject):
  83     def __init__(self, name=None):
  84         super().__init__(name=name)
  85         self.done          = Signal()
  86         self.err           = Signal()
  87         self.invalid       = Signal()
  88         self.badtree       = Signal()
  89         self.segerr        = Signal()
  90         self.perm_error    = Signal()
  91         self.rc_error      = Signal()
  92         self.sprval        = Signal(64)
  93
  94
  95 class MMUToDCacheType(RecordObject):
  96     def __init__(self, name=None):
  97         super().__init__(name=name)
  98         self.valid         = Signal()
  99         self.tlbie         = Signal()
 100         self.doall         = Signal()
 101         self.tlbld         = Signal()
 102         self.addr          = Signal(64)
 103         self.pte           = Signal(64)
 104
 105
 106 class MMUToICacheType(RecordObject):
 107     def __init__(self, name=None):
 108         super().__init__(name=name)
 109         self.tlbld         = Signal()
 110         self.tlbie         = Signal()
 111         self.doall         = Signal()
 112         self.addr          = Signal(64)
 113         self.pte           = Signal(64)
 114