3 based on Anton Blanchard microwatt mmu.vhdl
6 from enum
import Enum
, unique
7 from nmigen
import (C
, Module
, Signal
, Elaboratable
, Mux
, Cat
, Repl
, Signal
)
8 from nmigen
.cli
import main
9 from nmigen
.cli
import rtlil
10 from nmutil
.iocontrol
import RecordObject
11 from nmutil
.byterev
import byte_reverse
12 from nmutil
.mask
import Mask
13 from nmutil
.util
import Display
16 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
18 from nmigen
.sim
.cxxsim
import Simulator
, Delay
, Settle
19 from nmutil
.util
import wrap
21 from soc
.experiment
.mem_types
import (LoadStore1ToMMUType
,
30 IDLE
= 0 # zero is default on reset for r.state
42 class RegStage(RecordObject
):
43 def __init__(self
, name
=None):
44 super().__init
__(name
=name
)
45 # latched request from loadstore1
50 self
.addr
= Signal(64)
51 self
.inval_all
= Signal()
53 self
.prtbl
= Signal(64)
56 self
.state
= Signal(State
) # resets to IDLE
59 self
.pgtbl0
= Signal(64)
60 self
.pt0_valid
= Signal()
61 self
.pgtbl3
= Signal(64)
62 self
.pt3_valid
= Signal()
63 self
.shift
= Signal(6)
64 self
.mask_size
= Signal(5)
65 self
.pgbase
= Signal(56)
67 self
.invalid
= Signal()
68 self
.badtree
= Signal()
69 self
.segerror
= Signal()
70 self
.perm_err
= Signal()
71 self
.rc_error
= Signal()
74 class MMU(Elaboratable
):
77 Supports 4-level trees as in arch 3.0B, but not the
78 two-step translation for guests under a hypervisor
79 (i.e. there is no gRA -> hRA translation).
82 self
.l_in
= LoadStore1ToMMUType()
83 self
.l_out
= MMUToLoadStore1Type()
84 self
.d_out
= MMUToDCacheType()
85 self
.d_in
= DCacheToMMUType()
86 self
.i_out
= MMUToICacheType()
88 def radix_tree_idle(self
, m
, l_in
, r
, v
):
92 with m
.If(~l_in
.addr
[63]):
93 comb
+= pgtbl
.eq(r
.pgtbl0
)
94 comb
+= pt_valid
.eq(r
.pt0_valid
)
96 comb
+= pgtbl
.eq(r
.pt3_valid
)
97 comb
+= pt_valid
.eq(r
.pt3_valid
)
99 # rts == radix tree size, number of address bits
102 comb
+= rts
.eq(Cat(pgtbl
[5:8], pgtbl
[61:63]))
104 # mbits == number of address bits to index top
107 comb
+= mbits
.eq(pgtbl
[0:5])
109 # set v.shift to rts so that we can use finalmask
110 # for the segment check
111 comb
+= v
.shift
.eq(rts
)
112 comb
+= v
.mask_size
.eq(mbits
[0:5])
113 comb
+= v
.pgbase
.eq(Cat(C(0, 8), pgtbl
[8:56]))
115 with m
.If(l_in
.valid
):
116 comb
+= v
.addr
.eq(l_in
.addr
)
117 comb
+= v
.iside
.eq(l_in
.iside
)
118 comb
+= v
.store
.eq(~
(l_in
.load | l_in
.iside
))
120 with m
.If(l_in
.tlbie
):
121 # Invalidate all iTLB/dTLB entries for
122 # tlbie with RB[IS] != 0 or RB[AP] != 0,
124 comb
+= v
.inval_all
.eq(l_in
.slbia
131 # The RIC field of the tlbie instruction
132 # comes across on the sprn bus as bits 2--3.
133 # RIC=2 flushes process table caches.
134 with m
.If(l_in
.sprn
[3]):
135 comb
+= v
.pt0_valid
.eq(0)
136 comb
+= v
.pt3_valid
.eq(0)
137 comb
+= v
.state
.eq(State
.DO_TLBIE
)
139 comb
+= v
.valid
.eq(1)
140 with m
.If(~pt_valid
):
141 # need to fetch process table entry
142 # set v.shift so we can use finalmask
143 # for generating the process table
145 comb
+= v
.shift
.eq(r
.prtbl
[0:5])
146 comb
+= v
.state
.eq(State
.PROC_TBL_READ
)
149 # Use RPDS = 0 to disable radix tree walks
150 comb
+= v
.state
.eq(State
.RADIX_FINISH
)
151 comb
+= v
.invalid
.eq(1)
153 comb
+= v
.state
.eq(State
.SEGMENT_CHECK
)
155 with m
.If(l_in
.mtspr
):
156 # Move to PID needs to invalidate L1 TLBs
157 # and cached pgtbl0 value. Move to PRTBL
158 # does that plus invalidating the cached
159 # pgtbl3 value as well.
160 with m
.If(~l_in
.sprn
[9]):
161 comb
+= v
.pid
.eq(l_in
.rs
[0:32])
163 comb
+= v
.prtbl
.eq(l_in
.rs
)
164 comb
+= v
.pt3_valid
.eq(0)
166 comb
+= v
.pt0_valid
.eq(0)
167 comb
+= v
.inval_all
.eq(1)
168 comb
+= v
.state
.eq(State
.DO_TLBIE
)
170 def proc_tbl_wait(self
, m
, v
, r
, data
):
172 with m
.If(r
.addr
[63]):
173 comb
+= v
.pgtbl3
.eq(data
)
174 comb
+= v
.pt3_valid
.eq(1)
176 comb
+= v
.pgtbl0
.eq(data
)
177 comb
+= v
.pt0_valid
.eq(1)
178 # rts == radix tree size, # address bits being translated
180 comb
+= rts
.eq(Cat(data
[5:8], data
[61:63]))
182 # mbits == # address bits to index top level of tree
184 comb
+= mbits
.eq(data
[0:5])
185 # set v.shift to rts so that we can use
186 # finalmask for the segment check
187 comb
+= v
.shift
.eq(rts
)
188 comb
+= v
.mask_size
.eq(mbits
[0:5])
189 comb
+= v
.pgbase
.eq(Cat(C(0, 8), data
[8:56]))
192 comb
+= v
.state
.eq(State
.RADIX_FINISH
)
193 comb
+= v
.invalid
.eq(1)
194 comb
+= v
.state
.eq(State
.SEGMENT_CHECK
)
196 def radix_read_wait(self
, m
, v
, r
, d_in
, data
):
198 comb
+= v
.pde
.eq(data
)
202 # check permissions and RC bits
204 comb
+= perm_ok
.eq(0)
205 with m
.If(r
.priv | ~data
[3]):
212 # no IAMR, so no KUEP support
213 # for now deny execute
214 # permission if cache inhibited
215 comb
+= perm_ok
.eq(data
[0] & ~data
[5])
218 comb
+= rc_ok
.eq(data
[8] & (data
[7] |
(~r
.store
)))
219 with m
.If(perm_ok
& rc_ok
):
220 comb
+= v
.state
.eq(State
.RADIX_LOAD_TLB
)
222 comb
+= v
.state
.eq(State
.RADIX_FINISH
)
223 comb
+= v
.perm_err
.eq(~perm_ok
)
224 # permission error takes precedence
226 comb
+= v
.rc_error
.eq(perm_ok
)
229 comb
+= mbits
.eq(data
[0:5])
230 with m
.If((mbits
< 5) |
(mbits
> 16) |
(mbits
> r
.shift
)):
231 comb
+= v
.state
.eq(State
.RADIX_FINISH
)
232 comb
+= v
.badtree
.eq(1)
234 comb
+= v
.shift
.eq(v
.shift
- mbits
)
235 comb
+= v
.mask_size
.eq(mbits
[0:5])
236 comb
+= v
.pgbase
.eq(Cat(C(0, 8), data
[8:56]))
237 comb
+= v
.state
.eq(State
.RADIX_LOOKUP
)
239 def segment_check(self
, m
, v
, r
, data
, finalmask
):
243 comb
+= mbits
.eq(r
.mask_size
)
244 comb
+= v
.shift
.eq(r
.shift
+ (31 - 12) - mbits
)
245 comb
+= nonzero
.eq((r
.addr
[31:62] & ~finalmask
[0:31]).bool())
246 with m
.If((r
.addr
[63] ^ r
.addr
[62]) | nonzero
):
247 comb
+= v
.state
.eq(State
.RADIX_FINISH
)
248 comb
+= v
.segerror
.eq(1)
249 with m
.Elif((mbits
< 5) |
(mbits
> 16) |
250 (mbits
> (r
.shift
+ (31-12)))):
251 comb
+= v
.state
.eq(State
.RADIX_FINISH
)
252 comb
+= v
.badtree
.eq(1)
254 comb
+= v
.state
.eq(State
.RADIX_LOOKUP
)
256 def mmu_0(self
, m
, r
, rin
, l_in
, l_out
, d_out
, addrsh
, mask
):
260 # Multiplex internal SPR values back to loadstore1,
261 # selected by l_in.sprn.
262 with m
.If(l_in
.sprn
[9]):
263 comb
+= l_out
.sprval
.eq(r
.prtbl
)
265 comb
+= l_out
.sprval
.eq(r
.pid
)
267 with m
.If(rin
.valid
):
268 sync
+= Display("MMU got tlb miss for %x", rin
.addr
)
270 with m
.If(l_out
.done
):
271 sync
+= Display("MMU completing op without error")
273 with m
.If(l_out
.err
):
274 sync
+= Display("MMU completing op with err invalid"
275 "%d badtree=%d", l_out
.invalid
, l_out
.badtree
)
277 with m
.If(rin
.state
== State
.RADIX_LOOKUP
):
278 sync
+= Display ("radix lookup shift=%d msize=%d",
279 rin
.shift
, rin
.mask_size
)
281 with m
.If(r
.state
== State
.RADIX_LOOKUP
):
282 sync
+= Display(f
"send load addr=%x addrsh=%d mask=%d",
283 d_out
.addr
, addrsh
, mask
)
286 def elaborate(self
, platform
):
294 finalmask
= Signal(44)
297 rin
= RegStage("r_in")
305 self
.mmu_0(m
, r
, rin
, l_in
, l_out
, d_out
, addrsh
, mask
)
314 prtable_addr
= Signal(64)
315 pgtable_addr
= Signal(64)
317 tlb_data
= Signal(64)
321 comb
+= v
.valid
.eq(0)
325 comb
+= v
.invalid
.eq(0)
326 comb
+= v
.badtree
.eq(0)
327 comb
+= v
.segerror
.eq(0)
328 comb
+= v
.perm_err
.eq(0)
329 comb
+= v
.rc_error
.eq(0)
330 comb
+= tlb_load
.eq(0)
331 comb
+= itlb_load
.eq(0)
332 comb
+= tlbie_req
.eq(0)
333 comb
+= v
.inval_all
.eq(0)
334 comb
+= prtbl_rd
.eq(0)
336 # Radix tree data structures in memory are
337 # big-endian, so we need to byte-swap them
338 data
= byte_reverse(m
, "data", d_in
.data
, 8)
340 # generate mask for extracting address fields for PTE addr generation
341 m
.submodules
.pte_mask
= pte_mask
= Mask(16-5)
342 comb
+= pte_mask
.shift
.eq(r
.mask_size
- 5)
343 comb
+= mask
.eq(Cat(C(0x1f, 5), pte_mask
.mask
))
345 # generate mask for extracting address bits to go in
346 # TLB entry in order to support pages > 4kB
347 m
.submodules
.tlb_mask
= tlb_mask
= Mask(44)
348 comb
+= tlb_mask
.shift
.eq(r
.shift
)
349 comb
+= finalmask
.eq(tlb_mask
.mask
)
351 with m
.Switch(r
.state
):
352 with m
.Case(State
.IDLE
):
353 self
.radix_tree_idle(m
, l_in
, r
, v
)
355 with m
.Case(State
.DO_TLBIE
):
357 comb
+= tlbie_req
.eq(1)
358 comb
+= v
.state
.eq(State
.TLB_WAIT
)
360 with m
.Case(State
.TLB_WAIT
):
361 with m
.If(d_in
.done
):
362 comb
+= v
.state
.eq(State
.RADIX_FINISH
)
364 with m
.Case(State
.PROC_TBL_READ
):
366 comb
+= prtbl_rd
.eq(1)
367 comb
+= v
.state
.eq(State
.PROC_TBL_WAIT
)
369 with m
.Case(State
.PROC_TBL_WAIT
):
370 with m
.If(d_in
.done
):
371 self
.proc_tbl_wait(m
, v
, r
, data
)
374 comb
+= v
.state
.eq(State
.RADIX_FINISH
)
375 comb
+= v
.badtree
.eq(1)
377 with m
.Case(State
.SEGMENT_CHECK
):
378 self
.segment_check(m
, v
, r
, data
, finalmask
)
380 with m
.Case(State
.RADIX_LOOKUP
):
382 comb
+= v
.state
.eq(State
.RADIX_READ_WAIT
)
384 with m
.Case(State
.RADIX_READ_WAIT
):
385 with m
.If(d_in
.done
):
386 self
.radix_read_wait(m
, v
, r
, d_in
, data
)
388 # non-present PTE, generate a DSI
389 comb
+= v
.state
.eq(State
.RADIX_FINISH
)
390 comb
+= v
.invalid
.eq(1)
393 comb
+= v
.state
.eq(State
.RADIX_FINISH
)
394 comb
+= v
.badtree
.eq(1)
396 with m
.Case(State
.RADIX_LOAD_TLB
):
397 comb
+= tlb_load
.eq(1)
400 comb
+= v
.state
.eq(State
.TLB_WAIT
)
402 comb
+= itlb_load
.eq(1)
403 comb
+= v
.state
.eq(State
.IDLE
)
405 with m
.Case(State
.RADIX_FINISH
):
406 comb
+= v
.state
.eq(State
.IDLE
)
408 with m
.If((v
.state
== State
.RADIX_FINISH
) |
409 ((v
.state
== State
.RADIX_LOAD_TLB
) & r
.iside
)):
410 comb
+= v
.err
.eq(v
.invalid | v
.badtree | v
.segerror
411 | v
.perm_err | v
.rc_error
)
412 comb
+= v
.done
.eq(~v
.err
)
414 with m
.If(~r
.addr
[63]):
415 comb
+= effpid
.eq(r
.pid
)
417 comb
+= prtable_addr
.eq(Cat(
420 (r
.prtbl
[12:36] & ~finalmask
[0:24]) |
421 (effpid
[8:32] & finalmask
[0:24]),
425 comb
+= pgtable_addr
.eq(Cat(
427 (r
.pgbase
[3:19] & ~mask
) |
434 (r
.pde
[12:56] & ~finalmask
) |
435 (r
.addr
[12:56] & finalmask
),
442 with m
.If(tlbie_req
):
443 comb
+= addr
.eq(r
.addr
)
444 with m
.Elif(tlb_load
):
445 comb
+= addr
.eq(Cat(C(0, 12), r
.addr
[12:64]))
446 comb
+= tlb_data
.eq(pte
)
447 with m
.Elif(prtbl_rd
):
448 comb
+= addr
.eq(prtable_addr
)
450 comb
+= addr
.eq(pgtable_addr
)
452 comb
+= l_out
.done
.eq(r
.done
)
453 comb
+= l_out
.err
.eq(r
.err
)
454 comb
+= l_out
.invalid
.eq(r
.invalid
)
455 comb
+= l_out
.badtree
.eq(r
.badtree
)
456 comb
+= l_out
.segerr
.eq(r
.segerror
)
457 comb
+= l_out
.perm_error
.eq(r
.perm_err
)
458 comb
+= l_out
.rc_error
.eq(r
.rc_error
)
460 comb
+= d_out
.valid
.eq(dcreq
)
461 comb
+= d_out
.tlbie
.eq(tlbie_req
)
462 comb
+= d_out
.doall
.eq(r
.inval_all
)
463 comb
+= d_out
.tlbld
.eq(tlb_load
)
464 comb
+= d_out
.addr
.eq(addr
)
465 comb
+= d_out
.pte
.eq(tlb_data
)
467 comb
+= i_out
.tlbld
.eq(itlb_load
)
468 comb
+= i_out
.tlbie
.eq(tlbie_req
)
469 comb
+= i_out
.doall
.eq(r
.inval_all
)
470 comb
+= i_out
.addr
.eq(addr
)
471 comb
+= i_out
.pte
.eq(tlb_data
)
478 yield wp
.data_i
.eq(2)
485 data
= yield rp
.data_o
494 yield wp
.data_i
.eq(6)
496 data
= yield rp
.data_o
503 data
= yield rp
.data_o
507 data
= yield rp
.data_o
513 vl
= rtlil
.convert(dut
, ports
=[])#dut.ports())
514 with
open("test_mmu.il", "w") as f
:
518 m
.submodules
.mmu
= dut
524 sim
.add_sync_process(wrap(mmu_sim(dut
)))
525 with sim
.write_vcd('test_mmu.vcd'):
528 if __name__
== '__main__':