src/soc/experiment/pi2ls.py

   1 """PortInterface to LoadStoreUnitInterface adapter
   2
   3     PortInterface   LoadStoreUnitInterface
   4     -------------   ----------------------
   5
   6     is_ld_i/1       x_ld_i
   7     is_st_i/1       x_st_i
   8
   9     data_len/4      x_mask/16  (translate using LenExpand)
  10
  11     busy_o/1        most likely to be x_busy_o
  12     go_die_i/1      rst?
  13     addr.data/48    x_addr_i[4:] (x_addr_i[:4] goes into LenExpand)
  14     addr.ok/1       probably x_valid_i & ~x_stall_i
  15
  16     addr_ok_o/1     no equivalent.  *might* work using x_stall_i
  17     addr_exc_o/2(?) m_load_err_o and m_store_err_o
  18
  19     ld.data/64      m_ld_data_o
  20     ld.ok/1         probably implicit, when x_busy drops low
  21     st.data/64      x_st_data_i
  22     st.ok/1         probably kinda redundant, set to x_st_i
  23 """
  24
  25 from soc.minerva.units.loadstore import LoadStoreUnitInterface
  26 from soc.experiment.pimem import PortInterface
  27 from soc.scoreboard.addr_match import LenExpand
  28
  29 from nmigen import Elaboratable, Module, Signal
  30
  31
  32 class Pi2LSUI(Elaboratable):
  33
  34     def __init__(self, name, regwid=64, addrwid=48):
  35         self.pi = PortInterface(name="%s_pi", regwid, addrwid)
  36         self.lsui = LoadStoreUnitInterface(addrwid, 4, regwid)
  37
  38     def elaborate(self, platform):
  39         m = Module()
  40         m.submodules.lenexp = lenexp = LenExpand(4, 8)
  41
  42         return m