src/soc/experiment/pimem.py

   1 """L0 Cache/Buffer
   2
   3 This first version is intended for prototyping and test purposes:
   4 it has "direct" access to Memory.
   5
   6 The intention is that this version remains an integral part of the
   7 test infrastructure, and, just as with minerva's memory arrangement,
   8 a dynamic runtime config *selects* alternative memory arrangements
   9 rather than *replaces and discards* this code.
  10
  11 Links:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
  14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
  15 * https://bugs.libre-soc.org/show_bug.cgi?id=465 - exception handling
  16
  17 """
  18
  19 from nmigen.compat.sim import run_simulation, Settle
  20 from nmigen.cli import rtlil
  21 from nmigen import Module, Signal, Mux, Elaboratable, Cat, Const
  22 from nmutil.iocontrol import RecordObject
  23 from nmigen.utils import log2_int
  24
  25 from nmutil.latch import SRLatch, latchregister
  26 from nmutil.util import rising_edge
  27 from openpower.decoder.power_decoder2 import Data
  28 from soc.scoreboard.addr_match import LenExpand
  29 from soc.experiment.mem_types import LDSTException
  30
  31 # for testing purposes
  32 from soc.experiment.testmem import TestMemory
  33 #from soc.scoreboard.addr_split import LDSTSplitter
  34 from nmutil.util import Display
  35
  36 import unittest
  37
  38
  39 class PortInterface(RecordObject):
  40     """PortInterface
  41
  42     defines the interface - the API - that the LDSTCompUnit connects
  43     to.  note that this is NOT a "fire-and-forget" interface.  the
  44     LDSTCompUnit *must* be kept appraised that the request is in
  45     progress, and only when it has a 100% successful completion
  46     can the notification be given (busy dropped).
  47
  48     The interface FSM rules are as follows:
  49
  50     * if busy_o is asserted, a LD/ST is in progress.  further
  51       requests may not be made until busy_o is deasserted.
  52
  53     * only one of is_ld_i or is_st_i may be asserted.  busy_o
  54       will immediately be asserted and remain asserted.
  55
  56     * addr.ok is to be asserted when the LD/ST address is known.
  57       addr.data is to be valid on the same cycle.
  58
  59       addr.ok and addr.data must REMAIN asserted until busy_o
  60       is de-asserted.  this ensures that there is no need
  61       for the L0 Cache/Buffer to have an additional address latch
  62       (because the LDSTCompUnit already has it)
  63
  64     * addr_ok_o (or exception.happened) must be waited for.  these will
  65       be asserted *only* for one cycle and one cycle only.
  66
  67     * exception.happened will be asserted if there is no chance that the
  68       memory request may be fulfilled.
  69
  70       busy_o is deasserted on the same cycle as exception.happened is asserted.
  71
  72     * conversely: addr_ok_o must *ONLY* be asserted if there is a
  73       HUNDRED PERCENT guarantee that the memory request will be
  74       fulfilled.
  75
  76     * for a LD, ld.ok will be asserted - for only one clock cycle -
  77       at any point in the future that is acceptable to the underlying
  78       Memory subsystem.  the recipient MUST latch ld.data on that cycle.
  79
  80       busy_o is deasserted on the same cycle as ld.ok is asserted.
  81
  82     * for a ST, st.ok may be asserted only after addr_ok_o had been
  83       asserted, alongside valid st.data at the same time.  st.ok
  84       must only be asserted for one cycle.
  85
  86       the underlying Memory is REQUIRED to pick up that data and
  87       guarantee its delivery.  no back-acknowledgement is required.
  88
  89       busy_o is deasserted on the cycle AFTER st.ok is asserted.
  90     """
  91
  92     def __init__(self, name=None, regwid=64, addrwid=48):
  93
  94         self._regwid = regwid
  95         self._addrwid = addrwid
  96
  97         RecordObject.__init__(self, name=name)
  98
  99         # distinguish op type (ld/st/dcbz)
 100         self.is_ld_i    = Signal(reset_less=True)
 101         self.is_st_i    = Signal(reset_less=True)
 102         self.is_dcbz_i  = Signal(reset_less=True)
 103
 104         # LD/ST data length (TODO: other things may be needed)
 105         self.data_len = Signal(4, reset_less=True)
 106
 107         # common signals
 108         self.busy_o = Signal(reset_less=True)     # do not use if busy
 109         self.go_die_i = Signal(reset_less=True)   # back to reset
 110         self.addr = Data(addrwid, "addr_i")            # addr/addr-ok
 111         # addr is valid (TLB, L1 etc.)
 112         self.addr_ok_o = Signal(reset_less=True)
 113         self.exc_o = LDSTException("exc")
 114
 115         # LD/ST
 116         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
 117         self.st = Data(regwid, "st_data_i")  # ok to be set by CompUnit
 118
 119         # additional "modes"
 120         self.is_nc         = Signal()  # no cacheing
 121         self.msr_pr        = Signal()  # 1==virtual, 0==privileged
 122
 123         # mmu
 124         self.mmu_done          = Signal() # keep for now
 125
 126         # dcache
 127         self.ldst_error        = Signal()
 128         ## Signalling ld/st error - NC cache hit, TLB miss, prot/RC failure
 129         self.cache_paradox     = Signal()
 130
 131     def connect_port(self, inport):
 132         print("connect_port", self, inport)
 133         return [self.is_ld_i.eq(inport.is_ld_i),
 134                 self.is_st_i.eq(inport.is_st_i),
 135                 self.is_nc.eq(inport.is_nc),
 136                 self.is_dcbz_i.eq(inport.is_dcbz_i),
 137                 self.data_len.eq(inport.data_len),
 138                 self.go_die_i.eq(inport.go_die_i),
 139                 self.addr.data.eq(inport.addr.data),
 140                 self.addr.ok.eq(inport.addr.ok),
 141                 self.st.eq(inport.st),
 142                 self.msr_pr.eq(inport.msr_pr),
 143                 inport.ld.eq(self.ld),
 144                 inport.busy_o.eq(self.busy_o),
 145                 inport.addr_ok_o.eq(self.addr_ok_o),
 146                 inport.exc_o.eq(self.exc_o),
 147                 inport.mmu_done.eq(self.mmu_done),
 148                 inport.ldst_error.eq(self.ldst_error),
 149                 inport.cache_paradox.eq(self.cache_paradox)
 150                 ]
 151
 152
 153 class PortInterfaceBase(Elaboratable):
 154     """PortInterfaceBase
 155
 156     Base class for PortInterface-compliant Memory read/writers
 157     """
 158
 159     def __init__(self, regwid=64, addrwid=4):
 160         self.regwid = regwid
 161         self.addrwid = addrwid
 162         self.pi = PortInterface("ldst_port0", regwid, addrwid)
 163
 164     @property
 165     def addrbits(self):
 166         return log2_int(self.regwid//8)
 167
 168     def splitaddr(self, addr):
 169         """split the address into top and bottom bits of the memory granularity
 170         """
 171         return addr[:self.addrbits], addr[self.addrbits:]
 172
 173     def connect_port(self, inport):
 174         return self.pi.connect_port(inport)
 175
 176     def set_wr_addr(self, m, addr, mask, misalign, msr_pr): pass
 177     def set_rd_addr(self, m, addr, mask, misalign, msr_pr): pass
 178     def set_wr_data(self, m, data, wen): pass
 179     def get_rd_data(self, m): pass
 180     def set_dcbz_addr(self, m, addr): pass
 181
 182     def elaborate(self, platform):
 183         m = Module()
 184         comb, sync = m.d.comb, m.d.sync
 185
 186         # state-machine latches
 187         m.submodules.st_active = st_active = SRLatch(False, name="st_active")
 188         m.submodules.st_done = st_done = SRLatch(False, name="st_done")
 189         m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
 190         dcbz_active = SRLatch(False, name="dcbz_active")
 191         m.submodules.dcbz_active = dcbz_active # this one is new and untested
 192         m.submodules.reset_l = reset_l = SRLatch(True, name="reset")
 193         m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
 194         m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
 195         m.submodules.cyc_l = cyc_l = SRLatch(True, name="cyc")
 196
 197         self.busy_l = busy_l
 198
 199         comb += Display("PortInterfaceBase dcbz_active.q=%i",dcbz_active.q)
 200
 201         sync += st_done.s.eq(0)
 202         comb += st_done.r.eq(0)
 203         comb += st_active.r.eq(0)
 204         comb += ld_active.r.eq(0)
 205         comb += dcbz_active.r.eq(0)
 206         comb += cyc_l.s.eq(0)
 207         comb += cyc_l.r.eq(0)
 208         comb += busy_l.s.eq(0)
 209         comb += busy_l.r.eq(0)
 210         sync += adrok_l.s.eq(0)
 211         comb += adrok_l.r.eq(0)
 212
 213         # expand ld/st binary length/addr[:3] into unary bitmap
 214         m.submodules.lenexp = lenexp = LenExpand(4, 8)
 215
 216         lds = Signal(reset_less=True)
 217         sts = Signal(reset_less=True)
 218         dcbzs = Signal(reset_less=True)
 219         pi = self.pi
 220         comb += lds.eq(pi.is_ld_i)  # ld-req signals
 221         comb += sts.eq(pi.is_st_i)  # st-req signals
 222         comb += dcbzs.eq(pi.is_dcbz_i)  # dcbz-req signals (new, untested)
 223         pr = pi.msr_pr # MSR problem state: PR=1 ==> virt, PR==0 ==> priv
 224
 225         # detect busy "edge"
 226         busy_delay = Signal()
 227         busy_edge = Signal()
 228         sync += busy_delay.eq(pi.busy_o)
 229         comb += busy_edge.eq(pi.busy_o & ~busy_delay)
 230
 231         # misalignment detection: bits at end of lenexpand are set.
 232         # when using the L0CacheBuffer "data expander" which splits requests
 233         # into *two* PortInterfaces, this acts as a "safety check".
 234         misalign = Signal()
 235         comb += misalign.eq(lenexp.lexp_o[8:].bool())
 236
 237
 238         # activate mode: only on "edge"
 239         comb += ld_active.s.eq(rising_edge(m, lds))  # activate LD mode
 240         comb += st_active.s.eq(rising_edge(m, sts))  # activate ST mode
 241         comb += dcbz_active.s.eq(rising_edge(m, dcbzs))  # activate DCBZ mode
 242
 243         # LD/ST requested activates "busy" (only if not already busy)
 244         with m.If(self.pi.is_ld_i | self.pi.is_st_i):
 245             comb += busy_l.s.eq(~busy_delay)
 246
 247         # if now in "LD" mode: wait for addr_ok, then send the address out
 248         # to memory, acknowledge address, and send out LD data
 249         with m.If(ld_active.q):
 250             # set up LenExpander with the LD len and lower bits of addr
 251             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 252             comb += lenexp.len_i.eq(pi.data_len)
 253             comb += lenexp.addr_i.eq(lsbaddr)
 254             with m.If(pi.addr.ok & adrok_l.qn):
 255                 self.set_rd_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr)
 256                 comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 257                 sync += adrok_l.s.eq(1)       # and pull "ack" latch
 258
 259         # if now in "DCBZ" mode: wait for addr_ok, then send the address out
 260         # to memory, acknowledge address, and send out LD data
 261         with m.If(dcbz_active.q):
 262             ##comb += Display("dcbz active")
 263             # XXX Please don't do it this way, not without discussion
 264             # the exact same address is required to be set by both
 265             # dcbz and stores, so use the exact same function.
 266             # it would be better to add an extra argument to
 267             # set_wr_addr to indicate "dcbz mode".
 268             self.___use_wr_addr_instead_set_dcbz_addr(m, pi.addr.data)
 269
 270         # if now in "ST" mode: likewise do the same but with "ST"
 271         # to memory, acknowledge address, and send out LD data
 272         with m.If(st_active.q):
 273             # set up LenExpander with the ST len and lower bits of addr
 274             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 275             comb += lenexp.len_i.eq(pi.data_len)
 276             comb += lenexp.addr_i.eq(lsbaddr)
 277             with m.If(pi.addr.ok):
 278                 self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr)
 279                 with m.If(adrok_l.qn):
 280                     comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 281                     sync += adrok_l.s.eq(1)       # and pull "ack" latch
 282
 283         # for LD mode, when addr has been "ok'd", assume that (because this
 284         # is a "Memory" test-class) the memory read data is valid.
 285         comb += reset_l.s.eq(0)
 286         comb += reset_l.r.eq(0)
 287         lddata = Signal(self.regwid, reset_less=True)
 288         data, ldok = self.get_rd_data(m)
 289         comb += lddata.eq((data & lenexp.rexp_o) >>
 290                           (lenexp.addr_i*8))
 291         with m.If(ld_active.q & adrok_l.q):
 292             # shift data down before pushing out.  requires masking
 293             # from the *byte*-expanded version of LenExpand output
 294             comb += pi.ld.data.eq(lddata)  # put data out
 295             comb += pi.ld.ok.eq(ldok)      # indicate data valid
 296             comb += reset_l.s.eq(ldok)     # reset mode after 1 cycle
 297
 298         # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
 299         with m.If(st_active.q & pi.st.ok):
 300             # shift data up before storing.  lenexp *bit* version of mask is
 301             # passed straight through as byte-level "write-enable" lines.
 302             stdata = Signal(self.regwid, reset_less=True)
 303             comb += stdata.eq(pi.st.data << (lenexp.addr_i*8))
 304             # TODO: replace with link to LoadStoreUnitInterface.x_store_data
 305             # and also handle the ready/stall/busy protocol
 306             stok = self.set_wr_data(m, stdata, lenexp.lexp_o)
 307             sync += st_done.s.eq(1)     # store done trigger
 308         with m.If(st_done.q):
 309             comb += reset_l.s.eq(stok)   # reset mode after 1 cycle
 310
 311         # ugly hack, due to simultaneous addr req-go acknowledge
 312         reset_delay = Signal(reset_less=True)
 313         sync += reset_delay.eq(reset_l.q)
 314         with m.If(reset_delay):
 315             comb += adrok_l.r.eq(1)     # address reset
 316
 317         # after waiting one cycle (reset_l is "sync" mode), reset the port
 318         with m.If(reset_l.q):
 319             comb += ld_active.r.eq(1)   # leave the LD active for 1 cycle
 320             comb += st_active.r.eq(1)   # leave the ST active for 1 cycle
 321             comb += dcbz_active.r.eq(1)   # leave the DCBZ active for 1 cycle
 322             comb += reset_l.r.eq(1)     # clear reset
 323             comb += adrok_l.r.eq(1)     # address reset
 324             comb += st_done.r.eq(1)     # store done reset
 325
 326         # monitor for an exception, clear busy immediately
 327         with m.If(self.pi.exc_o.happened):
 328             comb += busy_l.r.eq(1)
 329
 330         # however ST needs one cycle before busy is reset
 331         #with m.If(self.pi.st.ok | self.pi.ld.ok):
 332         with m.If(reset_l.s):
 333             comb += cyc_l.s.eq(1)
 334
 335         with m.If(cyc_l.q):
 336             comb += cyc_l.r.eq(1)
 337             comb += busy_l.r.eq(1)
 338
 339         # busy latch outputs to interface
 340         comb += pi.busy_o.eq(busy_l.q)
 341
 342         return m
 343
 344     def ports(self):
 345         yield from self.pi.ports()
 346
 347
 348 class TestMemoryPortInterface(PortInterfaceBase):
 349     """TestMemoryPortInterface
 350
 351     This is a test class for simple verification of the LDSTCompUnit
 352     and for the simple core, to be able to run unit tests rapidly and
 353     with less other code in the way.
 354
 355     Versions of this which are *compatible* (conform with PortInterface)
 356     will include augmented-Wishbone Bus versions, including ones that
 357     connect to L1, L2, MMU etc. etc. however this is the "base lowest
 358     possible version that complies with PortInterface".
 359     """
 360
 361     def __init__(self, regwid=64, addrwid=4):
 362         super().__init__(regwid, addrwid)
 363         # hard-code memory addressing width to 6 bits
 364         self.mem = TestMemory(regwid, 5, granularity=regwid//8, init=False)
 365
 366     def set_wr_addr(self, m, addr, mask, misalign, msr_pr):
 367         lsbaddr, msbaddr = self.splitaddr(addr)
 368         m.d.comb += self.mem.wrport.addr.eq(msbaddr)
 369
 370     def set_rd_addr(self, m, addr, mask, misalign, msr_pr):
 371         lsbaddr, msbaddr = self.splitaddr(addr)
 372         m.d.comb += self.mem.rdport.addr.eq(msbaddr)
 373
 374     def set_wr_data(self, m, data, wen):
 375         m.d.comb += self.mem.wrport.data.eq(data)  # write st to mem
 376         m.d.comb += self.mem.wrport.en.eq(wen)  # enable writes
 377         return Const(1, 1)
 378
 379     def get_rd_data(self, m):
 380         return self.mem.rdport.data, Const(1, 1)
 381
 382     def elaborate(self, platform):
 383         m = super().elaborate(platform)
 384
 385         # add TestMemory as submodule
 386         m.submodules.mem = self.mem
 387
 388         return m
 389
 390     def ports(self):
 391         yield from super().ports()
 392         # TODO: memory ports