src/soc/experiment/pimem.py

   1 """L0 Cache/Buffer
   2
   3 This first version is intended for prototyping and test purposes:
   4 it has "direct" access to Memory.
   5
   6 The intention is that this version remains an integral part of the
   7 test infrastructure, and, just as with minerva's memory arrangement,
   8 a dynamic runtime config *selects* alternative memory arrangements
   9 rather than *replaces and discards* this code.
  10
  11 Links:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
  14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
  15 * https://bugs.libre-soc.org/show_bug.cgi?id=465 - exception handling
  16
  17 """
  18
  19 from nmigen.compat.sim import run_simulation, Settle
  20 from nmigen.cli import rtlil
  21 from nmigen import Module, Signal, Mux, Elaboratable, Cat, Const
  22 from nmutil.iocontrol import RecordObject
  23 from nmigen.utils import log2_int
  24
  25 from nmutil.latch import SRLatch, latchregister
  26 from nmutil.util import rising_edge
  27 from openpower.decoder.power_decoder2 import Data
  28 from soc.scoreboard.addr_match import LenExpand
  29 from soc.experiment.mem_types import LDSTException
  30
  31 # for testing purposes
  32 from soc.experiment.testmem import TestMemory
  33 #from soc.scoreboard.addr_split import LDSTSplitter
  34 from nmutil.util import Display
  35
  36 import unittest
  37
  38
  39 class PortInterface(RecordObject):
  40     """PortInterface
  41
  42     defines the interface - the API - that the LDSTCompUnit connects
  43     to.  note that this is NOT a "fire-and-forget" interface.  the
  44     LDSTCompUnit *must* be kept appraised that the request is in
  45     progress, and only when it has a 100% successful completion
  46     can the notification be given (busy dropped).
  47
  48     The interface FSM rules are as follows:
  49
  50     * if busy_o is asserted, a LD/ST is in progress.  further
  51       requests may not be made until busy_o is deasserted.
  52
  53     * only one of is_ld_i or is_st_i may be asserted.  busy_o
  54       will immediately be asserted and remain asserted.
  55
  56     * addr.ok is to be asserted when the LD/ST address is known.
  57       addr.data is to be valid on the same cycle.
  58
  59       addr.ok and addr.data must REMAIN asserted until busy_o
  60       is de-asserted.  this ensures that there is no need
  61       for the L0 Cache/Buffer to have an additional address latch
  62       (because the LDSTCompUnit already has it)
  63
  64     * addr_ok_o (or exception.happened) must be waited for.  these will
  65       be asserted *only* for one cycle and one cycle only.
  66
  67     * exception.happened will be asserted if there is no chance that the
  68       memory request may be fulfilled.
  69
  70       busy_o is deasserted on the same cycle as exception.happened is asserted.
  71
  72     * conversely: addr_ok_o must *ONLY* be asserted if there is a
  73       HUNDRED PERCENT guarantee that the memory request will be
  74       fulfilled.
  75
  76     * for a LD, ld.ok will be asserted - for only one clock cycle -
  77       at any point in the future that is acceptable to the underlying
  78       Memory subsystem.  the recipient MUST latch ld.data on that cycle.
  79
  80       busy_o is deasserted on the same cycle as ld.ok is asserted.
  81
  82     * for a ST, st.ok may be asserted only after addr_ok_o had been
  83       asserted, alongside valid st.data at the same time.  st.ok
  84       must only be asserted for one cycle.
  85
  86       the underlying Memory is REQUIRED to pick up that data and
  87       guarantee its delivery.  no back-acknowledgement is required.
  88
  89       busy_o is deasserted on the cycle AFTER st.ok is asserted.
  90     """
  91
  92     def __init__(self, name=None, regwid=64, addrwid=48):
  93
  94         self._regwid = regwid
  95         self._addrwid = addrwid
  96
  97         RecordObject.__init__(self, name=name)
  98
  99         # distinguish op type (ld/st)
 100         self.is_ld_i    = Signal(reset_less=True)
 101         self.is_st_i    = Signal(reset_less=True)
 102
 103         # LD/ST data length (TODO: other things may be needed)
 104         self.data_len = Signal(4, reset_less=True)
 105
 106         # common signals
 107         self.busy_o = Signal(reset_less=True)     # do not use if busy
 108         self.go_die_i = Signal(reset_less=True)   # back to reset
 109         self.addr = Data(addrwid, "addr_i")            # addr/addr-ok
 110         # addr is valid (TLB, L1 etc.)
 111         self.addr_ok_o = Signal(reset_less=True)
 112         self.exc_o = LDSTException("exc")
 113
 114         # LD/ST
 115         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
 116         self.st = Data(regwid, "st_data_i")  # ok to be set by CompUnit
 117
 118         # additional "modes"
 119         self.is_nc         = Signal()  # no cacheing
 120
 121         #only priv_mode = not msr_pr is used currently
 122         # TODO: connect signals
 123         self.virt_mode  = Signal() # ctrl.msr(MSR_DR);
 124         self.priv_mode  = Signal() # not ctrl.msr(MSR_PR);
 125         self.mode_32bit = Signal() # not ctrl.msr(MSR_SF);
 126
 127         self.is_dcbz_i     = Signal(reset_less=True)
 128
 129         # mmu
 130         self.mmu_done          = Signal() # keep for now
 131
 132         # dcache
 133         self.ldst_error        = Signal()
 134         ## Signalling ld/st error - NC cache hit, TLB miss, prot/RC failure
 135         self.cache_paradox     = Signal()
 136
 137     def connect_port(self, inport):
 138         print("connect_port", self, inport)
 139         return [self.is_ld_i.eq(inport.is_ld_i),
 140                 self.is_st_i.eq(inport.is_st_i),
 141                 self.is_nc.eq(inport.is_nc),
 142                 self.is_dcbz_i.eq(inport.is_dcbz_i),
 143                 self.data_len.eq(inport.data_len),
 144                 self.go_die_i.eq(inport.go_die_i),
 145                 self.addr.data.eq(inport.addr.data),
 146                 self.addr.ok.eq(inport.addr.ok),
 147                 self.st.eq(inport.st),
 148                 self.virt_mode.eq(inport.virt_mode),
 149                 self.priv_mode.eq(inport.priv_mode),
 150                 self.mode_32bit.eq(inport.mode_32bit),
 151                 inport.ld.eq(self.ld),
 152                 inport.busy_o.eq(self.busy_o),
 153                 inport.addr_ok_o.eq(self.addr_ok_o),
 154                 inport.exc_o.eq(self.exc_o),
 155                 inport.mmu_done.eq(self.mmu_done),
 156                 inport.ldst_error.eq(self.ldst_error),
 157                 inport.cache_paradox.eq(self.cache_paradox)
 158                 ]
 159
 160
 161 class PortInterfaceBase(Elaboratable):
 162     """PortInterfaceBase
 163
 164     Base class for PortInterface-compliant Memory read/writers
 165     """
 166
 167     def __init__(self, regwid=64, addrwid=4):
 168         self.regwid = regwid
 169         self.addrwid = addrwid
 170         self.pi = PortInterface("ldst_port0", regwid, addrwid)
 171
 172     @property
 173     def addrbits(self):
 174         return log2_int(self.regwid//8)
 175
 176     def splitaddr(self, addr):
 177         """split the address into top and bottom bits of the memory granularity
 178         """
 179         return addr[:self.addrbits], addr[self.addrbits:]
 180
 181     def connect_port(self, inport):
 182         return self.pi.connect_port(inport)
 183
 184     def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz): pass
 185     def set_rd_addr(self, m, addr, mask, misalign, msr_pr): pass
 186     def set_wr_data(self, m, data, wen): pass
 187     def get_rd_data(self, m): pass
 188
 189     def elaborate(self, platform):
 190         m = Module()
 191         comb, sync = m.d.comb, m.d.sync
 192
 193         # state-machine latches
 194         m.submodules.st_active = st_active = SRLatch(False, name="st_active")
 195         m.submodules.st_done = st_done = SRLatch(False, name="st_done")
 196         m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
 197         m.submodules.reset_l = reset_l = SRLatch(True, name="reset")
 198         m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
 199         m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
 200         m.submodules.cyc_l = cyc_l = SRLatch(True, name="cyc")
 201
 202         self.busy_l = busy_l
 203
 204         sync += st_done.s.eq(0)
 205         comb += st_done.r.eq(0)
 206         comb += st_active.r.eq(0)
 207         comb += ld_active.r.eq(0)
 208         comb += cyc_l.s.eq(0)
 209         comb += cyc_l.r.eq(0)
 210         comb += busy_l.s.eq(0)
 211         comb += busy_l.r.eq(0)
 212         sync += adrok_l.s.eq(0)
 213         comb += adrok_l.r.eq(0)
 214
 215         # expand ld/st binary length/addr[:3] into unary bitmap
 216         m.submodules.lenexp = lenexp = LenExpand(4, 8)
 217
 218         lds = Signal(reset_less=True)
 219         sts = Signal(reset_less=True)
 220         pi = self.pi
 221         comb += lds.eq(pi.is_ld_i)  # ld-req signals
 222         comb += sts.eq(pi.is_st_i)  # st-req signals
 223         pr = ~pi.priv_mode
 224
 225         # detect busy "edge"
 226         busy_delay = Signal()
 227         busy_edge = Signal()
 228         sync += busy_delay.eq(pi.busy_o)
 229         comb += busy_edge.eq(pi.busy_o & ~busy_delay)
 230
 231         # misalignment detection: bits at end of lenexpand are set.
 232         # when using the L0CacheBuffer "data expander" which splits requests
 233         # into *two* PortInterfaces, this acts as a "safety check".
 234         misalign = Signal()
 235         comb += misalign.eq(lenexp.lexp_o[8:].bool())
 236
 237
 238         # activate mode: only on "edge"
 239         comb += ld_active.s.eq(rising_edge(m, lds))  # activate LD mode
 240         comb += st_active.s.eq(rising_edge(m, sts))  # activate ST mode
 241
 242         # LD/ST requested activates "busy" (only if not already busy)
 243         with m.If(self.pi.is_ld_i | self.pi.is_st_i):
 244             comb += busy_l.s.eq(~busy_delay)
 245             with m.If(self.pi.exc_o.happened):
 246                 sync += Display("fast exception")
 247
 248         # if now in "LD" mode: wait for addr_ok, then send the address out
 249         # to memory, acknowledge address, and send out LD data
 250         with m.If(ld_active.q):
 251             # set up LenExpander with the LD len and lower bits of addr
 252             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 253             comb += lenexp.len_i.eq(pi.data_len)
 254             comb += lenexp.addr_i.eq(lsbaddr)
 255             with m.If(pi.addr.ok & adrok_l.qn):
 256                 self.set_rd_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr)
 257                 comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 258                 sync += adrok_l.s.eq(1)       # and pull "ack" latch
 259
 260         # if now in "ST" mode: likewise do the same but with "ST"
 261         # to memory, acknowledge address, and send out LD data
 262         with m.If(st_active.q):
 263             # set up LenExpander with the ST len and lower bits of addr
 264             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 265             comb += lenexp.len_i.eq(pi.data_len)
 266             comb += lenexp.addr_i.eq(lsbaddr)
 267             with m.If(pi.addr.ok):
 268                 self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr,
 269                                  pi.is_dcbz_i)
 270                 with m.If(adrok_l.qn & self.pi.exc_o.happened==0):
 271                     comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 272                     sync += adrok_l.s.eq(1)       # and pull "ack" latch
 273
 274         # for LD mode, when addr has been "ok'd", assume that (because this
 275         # is a "Memory" test-class) the memory read data is valid.
 276         comb += reset_l.s.eq(0)
 277         comb += reset_l.r.eq(0)
 278         lddata = Signal(self.regwid, reset_less=True)
 279         data, ldok = self.get_rd_data(m)
 280         comb += lddata.eq((data & lenexp.rexp_o) >>
 281                           (lenexp.addr_i*8))
 282         with m.If(ld_active.q & adrok_l.q):
 283             # shift data down before pushing out.  requires masking
 284             # from the *byte*-expanded version of LenExpand output
 285             comb += pi.ld.data.eq(lddata)  # put data out
 286             comb += pi.ld.ok.eq(ldok)      # indicate data valid
 287             comb += reset_l.s.eq(ldok)     # reset mode after 1 cycle
 288
 289         # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
 290         sync += st_done.s.eq(0)     # store done trigger
 291         with m.If(st_active.q & pi.st.ok):
 292             # shift data up before storing.  lenexp *bit* version of mask is
 293             # passed straight through as byte-level "write-enable" lines.
 294             stdata = Signal(self.regwid, reset_less=True)
 295             comb += stdata.eq(pi.st.data << (lenexp.addr_i*8))
 296             # TODO: replace with link to LoadStoreUnitInterface.x_store_data
 297             # and also handle the ready/stall/busy protocol
 298             stok = self.set_wr_data(m, stdata, lenexp.lexp_o)
 299             sync += st_done.s.eq(~self.pi.exc_o.happened) # store done trigger
 300         with m.If(st_done.q):
 301             comb += reset_l.s.eq(stok)   # reset mode after 1 cycle
 302
 303         # ugly hack, due to simultaneous addr req-go acknowledge
 304         reset_delay = Signal(reset_less=True)
 305         sync += reset_delay.eq(reset_l.q)
 306         with m.If(reset_delay):
 307             comb += adrok_l.r.eq(1)     # address reset
 308
 309         # after waiting one cycle (reset_l is "sync" mode), reset the port
 310         with m.If(reset_l.q):
 311             comb += ld_active.r.eq(1)   # leave the LD active for 1 cycle
 312             comb += st_active.r.eq(1)   # leave the ST active for 1 cycle
 313             comb += reset_l.r.eq(1)     # clear reset
 314             comb += adrok_l.r.eq(1)     # address reset
 315             comb += st_done.r.eq(1)     # store done reset
 316
 317         # monitor for an exception, clear busy immediately
 318         with m.If(self.pi.exc_o.happened):
 319             comb += busy_l.r.eq(1)
 320             comb += reset_l.s.eq(1) # also reset whole unit
 321
 322         # however ST needs one cycle before busy is reset
 323         #with m.If(self.pi.st.ok | self.pi.ld.ok):
 324         with m.If(reset_l.s):
 325             comb += cyc_l.s.eq(1)
 326
 327         with m.If(cyc_l.q):
 328             comb += cyc_l.r.eq(1)
 329             comb += busy_l.r.eq(1)
 330
 331         # busy latch outputs to interface
 332         if hasattr(self, "external_busy"):
 333             # when there is an extra (external) busy, include that here.
 334             # this is used e.g. in LoadStore1 when an instruction fault
 335             # is being processed (instr_fault) and stops Load/Store requests
 336             # from being made until it's done
 337             comb += pi.busy_o.eq(busy_l.q | self.external_busy(m))
 338         else:
 339             comb += pi.busy_o.eq(busy_l.q)
 340
 341         return m
 342
 343     def ports(self):
 344         yield from self.pi.ports()
 345
 346
 347 class TestMemoryPortInterface(PortInterfaceBase):
 348     """TestMemoryPortInterface
 349
 350     This is a test class for simple verification of the LDSTCompUnit
 351     and for the simple core, to be able to run unit tests rapidly and
 352     with less other code in the way.
 353
 354     Versions of this which are *compatible* (conform with PortInterface)
 355     will include augmented-Wishbone Bus versions, including ones that
 356     connect to L1, L2, MMU etc. etc. however this is the "base lowest
 357     possible version that complies with PortInterface".
 358     """
 359
 360     def __init__(self, regwid=64, addrwid=4):
 361         super().__init__(regwid, addrwid)
 362         # hard-code memory addressing width to 6 bits
 363         self.mem = TestMemory(regwid, 5, granularity=regwid//8, init=False)
 364
 365     def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz):
 366         lsbaddr, msbaddr = self.splitaddr(addr)
 367         m.d.comb += self.mem.wrport.addr.eq(msbaddr)
 368
 369     def set_rd_addr(self, m, addr, mask, misalign, msr_pr):
 370         lsbaddr, msbaddr = self.splitaddr(addr)
 371         m.d.comb += self.mem.rdport.addr.eq(msbaddr)
 372
 373     def set_wr_data(self, m, data, wen):
 374         m.d.comb += self.mem.wrport.data.eq(data)  # write st to mem
 375         m.d.comb += self.mem.wrport.en.eq(wen)  # enable writes
 376         return Const(1, 1)
 377
 378     def get_rd_data(self, m):
 379         return self.mem.rdport.data, Const(1, 1)
 380
 381     def elaborate(self, platform):
 382         m = super().elaborate(platform)
 383
 384         # add TestMemory as submodule
 385         m.submodules.mem = self.mem
 386
 387         return m
 388
 389     def ports(self):
 390         yield from super().ports()
 391         # TODO: memory ports