src/soc/experiment/plru.py

   1 # based on microwatt plru.vhdl
   2
   3 from nmigen import Elaboratable, Signal, Array, Module
   4 from nmigen.cli import rtlil
   5
   6
   7 class PLRU(Elaboratable):
   8
   9     def __init__(self, BITS=2):
  10         self.BITS = BITS
  11         self.acc_i = Signal(BITS)
  12         self.acc_en = Signal()
  13         self.lru_o = Signal(BITS)
  14
  15     def elaborate(self, platform):
  16         m = Module()
  17         comb, sync = m.d.comb, m.d.sync
  18
  19         tree = Array(Signal(name="tree%d" % i) for i in range(self.BITS))
  20
  21         # XXX Check if we can turn that into a little ROM instead that
  22         # takes the tree bit vector and returns the LRU. See if it's better
  23         # in term of FPGA resouces usage...
  24         node = Signal(self.BITS)
  25         for i in range(self.BITS):
  26             node_next = Signal(self.BITS)
  27             node2 = Signal(self.BITS)
  28             # report "GET: i:" & integer'image(i) & " node:" &
  29             # integer'image(node) & " val:" & Signal()'image(tree(node))
  30             comb += self.lru_o[self.BITS-1-i].eq(tree[node])
  31             if i != self.BITS-1:
  32                 comb += node2.eq(node << 1)
  33                 with m.If(tree[node2]):
  34                     comb += node_next.eq(node2 + 2)
  35                 with m.Else():
  36                     comb += node_next.eq(node2 + 1)
  37                 node = node_next
  38
  39         with m.If(self.acc_en):
  40             node = Signal(self.BITS)
  41             for i in range(self.BITS):
  42                 node_next = Signal(self.BITS)
  43                 node2 = Signal(self.BITS)
  44                 # report "GET: i:" & integer'image(i) & " node:" &
  45                 # integer'image(node) & " val:" & Signal()'image(tree(node))
  46                 abit = self.acc_i[self.BITS-1-i]
  47                 sync += tree[node].eq(~abit)
  48                 if i != self.BITS-1:
  49                     comb += node2.eq(node << 1)
  50                     with m.If(abit):
  51                         comb += node_next.eq(node2 + 2)
  52                     with m.Else():
  53                         comb += node_next.eq(node2 + 1)
  54                     node = node_next
  55
  56         return m
  57
  58     def ports(self):
  59         return [self.acc_en, self.lru_o, self.acc_i]
  60
  61 if __name__ == '__main__':
  62     dut = PLRU(3)
  63     vl = rtlil.convert(dut, ports=dut.ports())
  64     with open("test_plru.il", "w") as f:
  65         f.write(vl)
  66
  67