1 """Computation Unit (aka "ALU Manager").
3 Manages a Pipeline or FSM, ensuring that the start and end time are 100%
4 monitored. At no time may the ALU proceed without this module notifying
5 the Dependency Matrices. At no time is a result production "abandoned".
6 This module blocks (indicates busy) starting from when it first receives
7 an opcode until it receives notification that
8 its result(s) have been successfully stored in the regfile(s)
10 Documented at http://libre-soc.org/3d_gpu/architecture/compunit
13 from soc
.experiment
.alu_fsm
import Shifter
, CompFSMOpSubset
14 from soc
.fu
.alu
.alu_input_record
import CompALUOpSubset
15 from soc
.experiment
.alu_hier
import ALU
, DummyALU
16 from soc
.experiment
.compalu_multi
import MultiCompUnit
17 from soc
.decoder
.power_enums
import MicrOp
18 from nmutil
.gtkw
import write_gtkw
19 from nmigen
import Module
, Signal
20 from nmigen
.cli
import rtlil
22 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
23 # Also, check out the cxxsim nmigen branch, and latest yosys from git
24 from nmutil
.sim_tmp_alternative
import (Simulator
, Settle
, is_engine_pysim
,
34 class OperandProducer
:
36 Produces an operand when requested by the Computation Unit
37 (`dut` parameter), using the `rel_o` / `go_i` handshake.
39 Attaches itself to the `dut` operand indexed by `op_index`.
41 Has a programmable delay between the assertion of `rel_o` and the
44 Data is presented only during the cycle in which `go_i` is active.
46 It adds itself as a passive process to the simulation (`sim` parameter).
47 Since it is passive, it will not hang the simulation, and does not need a
48 flag to terminate itself.
50 def __init__(self
, sim
, dut
, op_index
):
51 self
.count
= Signal(8, name
=f
"src{op_index + 1}_count")
52 """ transaction counter"""
53 # data and handshake signals from the DUT
54 self
.port
= dut
.src_i
[op_index
]
55 self
.go_i
= dut
.rd
.go_i
[op_index
]
56 self
.rel_o
= dut
.rd
.rel_o
[op_index
]
57 # transaction parameters, passed via signals
58 self
.delay
= Signal(8)
59 self
.data
= Signal
.like(self
.port
)
60 # add ourselves to the simulation process list
61 sim
.add_sync_process(self
._process
)
66 # Settle() is needed to give a quick response to
69 # wait for rel_o to become active
70 while not (yield self
.rel_o
):
73 # read the transaction parameters
74 delay
= (yield self
.delay
)
75 data
= (yield self
.data
)
76 # wait for `delay` cycles
77 for _
in range(delay
):
79 # activate go_i and present data, for one cycle
81 yield self
.port
.eq(data
)
82 yield self
.count
.eq(self
.count
+ 1)
87 def send(self
, data
, delay
):
89 Schedules the module to send some `data`, counting `delay` cycles after
90 `rel_i` becomes active.
92 To be called from the main test-bench process,
93 it returns in the same cycle.
95 Communication with the worker process is done by means of
96 combinatorial simulation-only signals.
99 yield self
.data
.eq(data
)
100 yield self
.delay
.eq(delay
)
103 class ResultConsumer
:
105 Consumes a result when requested by the Computation Unit
106 (`dut` parameter), using the `rel_o` / `go_i` handshake.
108 Attaches itself to the `dut` result indexed by `op_index`.
110 Has a programmable delay between the assertion of `rel_o` and the
113 Data is retrieved only during the cycle in which `go_i` is active.
115 It adds itself as a passive process to the simulation (`sim` parameter).
116 Since it is passive, it will not hang the simulation, and does not need a
117 flag to terminate itself.
119 def __init__(self
, sim
, dut
, op_index
):
120 self
.count
= Signal(8, name
=f
"dest{op_index + 1}_count")
121 """ transaction counter"""
122 # data and handshake signals from the DUT
123 self
.port
= dut
.dest
[op_index
]
124 self
.go_i
= dut
.wr
.go_i
[op_index
]
125 self
.rel_o
= dut
.wr
.rel_o
[op_index
]
126 # transaction parameters, passed via signals
127 self
.delay
= Signal(8)
128 self
.expected
= Signal
.like(self
.port
)
129 # add ourselves to the simulation process list
130 sim
.add_sync_process(self
._process
)
135 # Settle() is needed to give a quick response to
136 # the zero delay case
138 # wait for rel_o to become active
139 while not (yield self
.rel_o
):
142 # read the transaction parameters
143 delay
= (yield self
.delay
)
144 expected
= (yield self
.expected
)
145 # wait for `delay` cycles
146 for _
in range(delay
):
148 # activate go_i for one cycle
149 yield self
.go_i
.eq(1)
150 yield self
.count
.eq(self
.count
+ 1)
152 # check received data against the expected value
153 result
= (yield self
.port
)
154 assert result
== expected
,\
155 f
"expected {expected}, received {result}"
156 yield self
.go_i
.eq(0)
157 yield self
.port
.eq(0)
159 def receive(self
, expected
, delay
):
161 Schedules the module to receive some result,
162 counting `delay` cycles after `rel_i` becomes active.
163 As 'go_i' goes active, check the result with `expected`.
165 To be called from the main test-bench process,
166 it returns in the same cycle.
168 Communication with the worker process is done by means of
169 combinatorial simulation-only signals.
171 yield self
.expected
.eq(expected
)
172 yield self
.delay
.eq(delay
)
175 def op_sim(dut
, a
, b
, op
, inv_a
=0, imm
=0, imm_ok
=0, zero_a
=0):
176 yield dut
.issue_i
.eq(0)
178 yield dut
.src_i
[0].eq(a
)
179 yield dut
.src_i
[1].eq(b
)
180 yield dut
.oper_i
.insn_type
.eq(op
)
181 yield dut
.oper_i
.invert_in
.eq(inv_a
)
182 yield dut
.oper_i
.imm_data
.data
.eq(imm
)
183 yield dut
.oper_i
.imm_data
.ok
.eq(imm_ok
)
184 yield dut
.oper_i
.zero_a
.eq(zero_a
)
185 yield dut
.issue_i
.eq(1)
187 yield dut
.issue_i
.eq(0)
189 if not imm_ok
or not zero_a
:
190 yield dut
.rd
.go_i
.eq(0b11)
193 rd_rel_o
= yield dut
.rd
.rel_o
194 print("rd_rel", rd_rel_o
)
197 yield dut
.rd
.go_i
.eq(0)
201 if len(dut
.src_i
) == 3:
202 yield dut
.rd
.go_i
.eq(0b100)
205 rd_rel_o
= yield dut
.rd
.rel_o
206 print("rd_rel", rd_rel_o
)
209 yield dut
.rd
.go_i
.eq(0)
213 req_rel_o
= yield dut
.wr
.rel_o
214 result
= yield dut
.data_o
215 print("req_rel", req_rel_o
, result
)
217 req_rel_o
= yield dut
.wr
.rel_o
218 result
= yield dut
.data_o
219 print("req_rel", req_rel_o
, result
)
223 yield dut
.wr
.go_i
[0].eq(1)
225 result
= yield dut
.data_o
227 print("result", result
)
228 yield dut
.wr
.go_i
[0].eq(0)
233 def scoreboard_sim_fsm(dut
, producers
, consumers
):
235 # stores the operation count
238 def op_sim_fsm(a
, b
, direction
, expected
, delays
):
239 print("op_sim_fsm", a
, b
, direction
, expected
)
240 yield dut
.issue_i
.eq(0)
242 # forward data and delays to the producers and consumers
243 yield from producers
[0].send(a
, delays
[0])
244 yield from producers
[1].send(b
, delays
[1])
245 yield from consumers
[0].receive(expected
, delays
[2])
246 # submit operation, and assert issue_i for one cycle
247 yield dut
.oper_i
.sdir
.eq(direction
)
248 yield dut
.issue_i
.eq(1)
250 yield dut
.issue_i
.eq(0)
251 # wait for busy to be negated
253 while (yield dut
.busy_o
):
256 # update the operation count
258 op_count
= (op_count
+ 1) & 255
259 # check that producers and consumers have the same count
260 # this assures that no data was left unused or was lost
261 assert (yield producers
[0].count
) == op_count
262 assert (yield producers
[1].count
) == op_count
263 assert (yield consumers
[0].count
) == op_count
266 # operand 1 arrives immediately
267 # operand 2 arrives after operand 1
268 # write data is accepted immediately
269 yield from op_sim_fsm(13, 2, 1, 3, [0, 2, 0])
271 # operand 2 arrives immediately
272 # operand 1 arrives after operand 2
273 # write data is accepted after some delay
274 yield from op_sim_fsm(3, 4, 0, 48, [2, 0, 2])
276 # operands 1 and 2 arrive at the same time
277 # write data is accepted after some delay
278 yield from op_sim_fsm(21, 0, 0, 21, [1, 1, 1])
281 def scoreboard_sim_dummy(dut
):
282 result
= yield from op_sim(dut
, 5, 2, MicrOp
.OP_NOP
, inv_a
=0,
284 assert result
== 5, result
286 result
= yield from op_sim(dut
, 9, 2, MicrOp
.OP_NOP
, inv_a
=0,
288 assert result
== 9, result
291 def scoreboard_sim(dut
):
292 # zero (no) input operands test
293 result
= yield from op_sim(dut
, 5, 2, MicrOp
.OP_ADD
, zero_a
=1,
297 result
= yield from op_sim(dut
, 5, 2, MicrOp
.OP_ADD
, inv_a
=0,
301 result
= yield from op_sim(dut
, 5, 2, MicrOp
.OP_ADD
)
304 result
= yield from op_sim(dut
, 5, 2, MicrOp
.OP_ADD
, inv_a
=1)
305 assert result
== 65532
307 result
= yield from op_sim(dut
, 5, 2, MicrOp
.OP_ADD
, zero_a
=1)
310 # test combinatorial zero-delay operation
311 # In the test ALU, any operation other than ADD, MUL or SHR
312 # is zero-delay, and do a subtraction.
313 result
= yield from op_sim(dut
, 5, 2, MicrOp
.OP_NOP
)
317 def test_compunit_fsm():
318 top
= "top.cu" if is_engine_pysim() else "cu"
321 ('operation port', {'color': 'red'}, [
322 'oper_i_None__sdir', 'cu_issue_i',
324 ('operand 1 port', {'color': 'yellow'}, [
325 ('cu_rd__rel_o[1:0]', {'bit': 1}),
326 ('cu_rd__go_i[1:0]', {'bit': 1}),
328 ('operand 2 port', {'color': 'yellow'}, [
329 ('cu_rd__rel_o[1:0]', {'bit': 0}),
330 ('cu_rd__go_i[1:0]', {'bit': 0}),
332 ('result port', {'color': 'orange'}, [
333 'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[7:0]']),
334 ('alu', {'module': top
+'.alu'}, [
335 'p_data_i[7:0]', 'p_shift_i[7:0]', 'op__sdir',
336 'p_valid_i', 'p_ready_o', 'n_valid_o', 'n_ready_i',
339 ('debug', {'module': 'top'},
340 ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])
344 "test_compunit_fsm1.gtkw",
345 "test_compunit_fsm1.vcd",
351 dut
= MultiCompUnit(8, alu
, CompFSMOpSubset
)
352 m
.submodules
.cu
= dut
354 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
355 with
open("test_compunit_fsm1.il", "w") as f
:
361 # create one operand producer for each input port
362 prod_a
= OperandProducer(sim
, dut
, 0)
363 prod_b
= OperandProducer(sim
, dut
, 1)
364 # create an result consumer for the output port
365 cons
= ResultConsumer(sim
, dut
, 0)
366 sim
.add_sync_process(wrap(scoreboard_sim_fsm(dut
,
369 sim_writer
= sim
.write_vcd('test_compunit_fsm1.vcd',
370 traces
=[prod_a
.count
,
381 dut
= MultiCompUnit(16, alu
, CompALUOpSubset
)
382 m
.submodules
.cu
= dut
384 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
385 with
open("test_compunit1.il", "w") as f
:
391 sim
.add_sync_process(wrap(scoreboard_sim(dut
)))
392 sim_writer
= sim
.write_vcd('test_compunit1.vcd')
397 class CompUnitParallelTest
:
398 def __init__(self
, dut
):
401 # Operation cycle should not take longer than this:
402 self
.MAX_BUSY_WAIT
= 50
404 # Minimum duration in which issue_i will be kept inactive,
405 # during which busy_o must remain low.
406 self
.MIN_BUSY_LOW
= 5
408 # Number of cycles to stall until the assertion of go.
409 # One value, for each port. Can be zero, for no delay.
410 self
.RD_GO_DELAY
= [0, 3]
412 # store common data for the input operation of the processes
415 self
.inv_a
= self
.zero_a
= 0
416 self
.imm
= self
.imm_ok
= 0
417 self
.imm_control
= (0, 0)
418 self
.rdmaskn
= (0, 0)
420 self
.operands
= (0, 0)
422 # Indicates completion of the sub-processes
423 self
.rd_complete
= [False, False]
426 print("Begin parallel test.")
427 yield from self
.operation(5, 2, MicrOp
.OP_ADD
)
429 def operation(self
, a
, b
, op
, inv_a
=0, imm
=0, imm_ok
=0, zero_a
=0,
431 # store data for the operation
432 self
.operands
= (a
, b
)
438 self
.imm_control
= (zero_a
, imm_ok
)
439 self
.rdmaskn
= rdmaskn
441 # Initialize completion flags
442 self
.rd_complete
= [False, False]
444 # trigger operation cycle
445 yield from self
.issue()
447 # check that the sub-processes completed, before the busy_o cycle ended
448 for completion
in self
.rd_complete
:
452 # issue_i starts inactive
453 yield self
.dut
.issue_i
.eq(0)
455 for n
in range(self
.MIN_BUSY_LOW
):
457 # busy_o must remain inactive. It cannot rise on its own.
458 busy_o
= yield self
.dut
.busy_o
461 # activate issue_i to begin the operation cycle
462 yield self
.dut
.issue_i
.eq(1)
464 # at the same time, present the operation
465 yield self
.dut
.oper_i
.insn_type
.eq(self
.op
)
466 yield self
.dut
.oper_i
.invert_in
.eq(self
.inv_a
)
467 yield self
.dut
.oper_i
.imm_data
.data
.eq(self
.imm
)
468 yield self
.dut
.oper_i
.imm_data
.ok
.eq(self
.imm_ok
)
469 yield self
.dut
.oper_i
.zero_a
.eq(self
.zero_a
)
470 rdmaskn
= self
.rdmaskn
[0] |
(self
.rdmaskn
[1] << 1)
471 yield self
.dut
.rdmaskn
.eq(rdmaskn
)
473 # give one cycle for the CompUnit to latch the data
476 # busy_o must keep being low in this cycle, because issue_i was
477 # low on the previous cycle.
478 # It cannot rise on its own.
479 # Also, busy_o and issue_i must never be active at the same time, ever.
480 busy_o
= yield self
.dut
.busy_o
484 yield self
.dut
.issue_i
.eq(0)
486 # deactivate inputs along with issue_i, so we can be sure the data
487 # was latched at the correct cycle
488 # note: rdmaskn must be held, while busy_o is active
489 # TODO: deactivate rdmaskn when the busy_o cycle ends
490 yield self
.dut
.oper_i
.insn_type
.eq(0)
491 yield self
.dut
.oper_i
.invert_in
.eq(0)
492 yield self
.dut
.oper_i
.imm_data
.data
.eq(0)
493 yield self
.dut
.oper_i
.imm_data
.ok
.eq(0)
494 yield self
.dut
.oper_i
.zero_a
.eq(0)
497 # wait for busy_o to lower
498 # timeout after self.MAX_BUSY_WAIT cycles
499 for n
in range(self
.MAX_BUSY_WAIT
):
500 # sample busy_o in the current cycle
501 busy_o
= yield self
.dut
.busy_o
503 # operation cycle ends when busy_o becomes inactive
507 # if busy_o is still active, a timeout has occurred
508 # TODO: Uncomment this, once the test is complete:
512 print("If you are reading this, "
513 "it's because the above test failed, as expected,\n"
514 "with a timeout. It must pass, once the test is complete.")
517 print("If you are reading this, "
518 "it's because the above test unexpectedly passed.")
520 def rd(self
, rd_idx
):
521 # wait for issue_i to rise
523 issue_i
= yield self
.dut
.issue_i
526 # issue_i has not risen yet, so rd must keep low
527 rel
= yield self
.dut
.rd
.rel_o
[rd_idx
]
531 # we do not want rd to rise on an immediate operand
532 # if it is immediate, exit the process
533 # likewise, if the read mask is active
534 # TODO: don't exit the process, monitor rd instead to ensure it
535 # doesn't rise on its own
536 if self
.rdmaskn
[rd_idx
] or self
.imm_control
[rd_idx
]:
537 self
.rd_complete
[rd_idx
] = True
540 # issue_i has risen. rel must rise on the next cycle
541 rel
= yield self
.dut
.rd
.rel_o
[rd_idx
]
544 # stall for additional cycles. Check that rel doesn't fall on its own
545 for n
in range(self
.RD_GO_DELAY
[rd_idx
]):
547 rel
= yield self
.dut
.rd
.rel_o
[rd_idx
]
550 # Before asserting "go", make sure "rel" has risen.
551 # The use of Settle allows "go" to be set combinatorially,
552 # rising on the same cycle as "rel".
554 rel
= yield self
.dut
.rd
.rel_o
[rd_idx
]
557 # assert go for one cycle, passing along the operand value
558 yield self
.dut
.rd
.go_i
[rd_idx
].eq(1)
559 yield self
.dut
.src_i
[rd_idx
].eq(self
.operands
[rd_idx
])
560 # check that the operand was sent to the alu
561 # TODO: Properly check the alu protocol
563 alu_input
= yield self
.dut
.get_in(rd_idx
)
564 assert alu_input
== self
.operands
[rd_idx
]
567 # rel must keep high, since go was inactive in the last cycle
568 rel
= yield self
.dut
.rd
.rel_o
[rd_idx
]
571 # finish the go one-clock pulse
572 yield self
.dut
.rd
.go_i
[rd_idx
].eq(0)
573 yield self
.dut
.src_i
[rd_idx
].eq(0)
576 # rel must have gone low in response to go being high
577 # on the previous cycle
578 rel
= yield self
.dut
.rd
.rel_o
[rd_idx
]
581 self
.rd_complete
[rd_idx
] = True
583 # TODO: check that rel doesn't rise again until the end of the
586 def wr(self
, wr_idx
):
587 # monitor self.dut.wr.req[rd_idx] and sets dut.wr.go[idx] for one cycle
589 # TODO: also when dut.wr.go is set, check the output against the
590 # self.expected_o and assert. use dut.get_out(wr_idx) to do so.
592 def run_simulation(self
, vcd_name
):
594 m
.submodules
.cu
= self
.dut
598 sim
.add_sync_process(wrap(self
.driver()))
599 sim
.add_sync_process(wrap(self
.rd(0)))
600 sim
.add_sync_process(wrap(self
.rd(1)))
601 sim
.add_sync_process(wrap(self
.wr(0)))
602 sim_writer
= sim
.write_vcd(vcd_name
)
607 def test_compunit_regspec2_fsm():
609 inspec
= [('INT', 'data', '0:15'),
610 ('INT', 'shift', '0:15'),
612 outspec
= [('INT', 'data', '0:15'),
615 regspec
= (inspec
, outspec
)
619 dut
= MultiCompUnit(regspec
, alu
, CompFSMOpSubset
)
620 m
.submodules
.cu
= dut
625 # create one operand producer for each input port
626 prod_a
= OperandProducer(sim
, dut
, 0)
627 prod_b
= OperandProducer(sim
, dut
, 1)
628 # create an result consumer for the output port
629 cons
= ResultConsumer(sim
, dut
, 0)
630 sim
.add_sync_process(wrap(scoreboard_sim_fsm(dut
,
633 sim_writer
= sim
.write_vcd('test_compunit_regspec2_fsm.vcd',
634 traces
=[prod_a
.count
,
641 def test_compunit_regspec3():
643 inspec
= [('INT', 'a', '0:15'),
644 ('INT', 'b', '0:15'),
645 ('INT', 'c', '0:15')]
646 outspec
= [('INT', 'o', '0:15'),
649 regspec
= (inspec
, outspec
)
653 dut
= MultiCompUnit(regspec
, alu
, CompALUOpSubset
)
654 m
.submodules
.cu
= dut
659 sim
.add_sync_process(wrap(scoreboard_sim_dummy(dut
)))
660 sim_writer
= sim
.write_vcd('test_compunit_regspec3.vcd')
665 def test_compunit_regspec1():
667 inspec
= [('INT', 'a', '0:15'),
668 ('INT', 'b', '0:15')]
669 outspec
= [('INT', 'o', '0:15'),
672 regspec
= (inspec
, outspec
)
676 dut
= MultiCompUnit(regspec
, alu
, CompALUOpSubset
)
677 m
.submodules
.cu
= dut
679 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
680 with
open("test_compunit_regspec1.il", "w") as f
:
686 sim
.add_sync_process(wrap(scoreboard_sim(dut
)))
687 sim_writer
= sim
.write_vcd('test_compunit_regspec1.vcd')
691 test
= CompUnitParallelTest(dut
)
692 test
.run_simulation("test_compunit_parallel.vcd")
695 if __name__
== '__main__':
698 test_compunit_regspec1()
699 test_compunit_regspec2_fsm()
700 test_compunit_regspec3()